JPH0241941B2 - - Google Patents
Info
- Publication number
- JPH0241941B2 JPH0241941B2 JP56197073A JP19707381A JPH0241941B2 JP H0241941 B2 JPH0241941 B2 JP H0241941B2 JP 56197073 A JP56197073 A JP 56197073A JP 19707381 A JP19707381 A JP 19707381A JP H0241941 B2 JPH0241941 B2 JP H0241941B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- value
- counting
- ringing signal
- signal current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 101100464782 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CMP2 gene Proteins 0.000 description 6
- 101100464779 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CNA1 gene Proteins 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/02—Calling substations, e.g. by ringing
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Devices For Supply Of Signal Current (AREA)
Description
【発明の詳細な説明】
本発明はリングトリツプ方式、特に電話交換機
の呼出信号送出回路におけるリングトリツプ方式
に関す。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ring trip system, and more particularly to a ring trip system in a ring signal sending circuit of a telephone exchange.
第1図は呼出信号送出回路の従来あるリングト
リツプ方式の一例を示す図である。第1図におい
て、呼出信号電源1から抵抗2および7並びに直
流電源6を経由して、端子3および4に接続され
る電話機5に呼出信号電源irが供給され、電鈴を
鳴動させる。電話機5における電鈴回路にはコン
デンサが挿入されているので、加入者が応答せぬ
限り直流電源6から直流電流idは送出されない。
かかる状態においては抵抗7の両端には呼出信号
電流irによる交流電圧のみが生じ、抵抗8および
コンデンサ9により構成される低域波器に阻止
されて、トランジスタ11が付勢されることは無
い。かかる状態で被呼者が応答すると、電話機5
の電鈴回路が除去され、直流ループ回路が形成さ
れるので、前記呼出信号電流irに重畳して直流電
流idが流れ、抵抗7の両端には前記交流電圧と共
に直流電圧が発生する。該直流電圧によりコンデ
ンサ9が充電され、コンデンサ9の端子電圧が定
電圧ダイオード12の降服電圧を上廻ると、トラ
ンジスタ11が付勢されてリレー13が動作し、
接点13′により端子14からリングトリツプ信
号RTOを送出し、公知の方法により処理装置等
に被呼者の応答を通知する。 FIG. 1 is a diagram showing an example of a conventional ring trip method of a calling signal sending circuit. In FIG. 1, a ringing signal power ir is supplied from a ringing signal power source 1 via resistors 2 and 7 and a DC power source 6 to a telephone 5 connected to terminals 3 and 4, causing a bell to ring. Since a capacitor is inserted in the bell circuit of the telephone 5, the DC current id is not sent out from the DC power supply 6 unless the subscriber responds.
In such a state, only an alternating current voltage due to the ringing signal current ir is generated across the resistor 7, and is blocked by the low-frequency wave generator composed of the resistor 8 and the capacitor 9, so that the transistor 11 is not energized. When the called party answers in such a state, the telephone 5
Since the bell circuit is removed and a DC loop circuit is formed, a DC current id flows superimposed on the ringing signal current ir, and a DC voltage is generated across the resistor 7 along with the AC voltage. When the capacitor 9 is charged by the DC voltage and the terminal voltage of the capacitor 9 exceeds the breakdown voltage of the voltage regulator diode 12, the transistor 11 is energized and the relay 13 is operated.
Contact 13' sends out a ring trip signal RTO from terminal 14 to notify a processing device or the like of the called party's response in a known manner.
以上の説明から明らかな如く、従来あるリング
トリツプ方式においては、呼出信号電流irに被呼
者応答時に重畳して流れる直流電流を検出するた
めに大容量コンデンサを用いた低域波器が使用
されているため、LSI技術等による呼出信号送出
回路の小形化を阻害する結果となる。 As is clear from the above explanation, in the conventional ring trip method, a low frequency filter using a large capacitor is used to detect the direct current that flows superimposed on the ringing signal current ir when the called party answers. This results in hindering miniaturization of the calling signal sending circuit using LSI technology or the like.
本発明の目的は、前述の如き従来あるリングト
リツプ方式の欠点を除去し、大形部品を使用する
ことなくLSI技術により実現可能なリングトリツ
プ方式の実現にある。 An object of the present invention is to eliminate the drawbacks of the conventional ring trip method as described above, and to realize a ring trip method that can be realized by LSI technology without using large parts.
この目的は、呼出信号送出回路の送出する一定
周期の呼出信号電流を所定の基準値と比較する第
一の比較回路と、
加算と減算の二つの異なる計数動作が選択可能
で、該呼出信号電流の周期より短い周期のクロツ
クを加算または減算する計数回路と、
該第一の比較回路が該呼出信号電流を該基準値
以上と判定する期間と該基準値以下と判定する期
間との変化点を検出し、該計数回路の計数動作を
加算から減算または減算から加算に切り替える切
替回路と、
該計数回路の計数値を所定の閾値と比較し、該
計数値が該閾値を越えたことにより、該呼出信号
電流に重畳された直流電流を検出して、リングト
リツプ信号を出力する第二の比較回路とを備えた
呼出信号送出回路において、
前記変化点で、前記計数回路の計数値から、予
め定められた補正値を減算する減算器と、
前記計数回路の減算中に、計数値が零を示すこ
とを検出した際、前記切替回路により前記変化点
が検出されるまで、該計数回路の減算を停止させ
る第三の比較回路とを備えることにより達成され
る。 The purpose of this is to provide a first comparator circuit that compares a constant periodic ringing signal current sent out by the ringing signal sending circuit with a predetermined reference value, and a first comparison circuit that can select between two different counting operations, addition and subtraction, for the ringing signal current. a counting circuit that adds or subtracts a clock having a cycle shorter than the cycle of the clock signal; and a counting circuit that calculates a change point between a period in which the calling signal current is determined to be equal to or greater than the reference value and a period in which the first comparison circuit determines that the ringing signal current is equal to or less than the reference value. a switching circuit that detects and switches the counting operation of the counting circuit from addition to subtraction or from subtraction to addition; and a switching circuit that compares the counted value of the counting circuit with a predetermined threshold, and when the counted value exceeds the threshold, and a second comparison circuit that detects a direct current superimposed on the ring signal current and outputs a ring trip signal, wherein at the change point, a predetermined value is determined from the count value of the counting circuit at the change point. a subtracter that subtracts a correction value obtained by the counting circuit; and a subtracter that, when it is detected that the count value indicates zero during the subtraction of the counting circuit, stops the subtraction of the counting circuit until the change point is detected by the switching circuit. This is achieved by providing a third comparator circuit that allows
以下、本発明の一実施例を第2図および第3図
により説明する。第2図は呼出信号送出回路にお
ける本発明の一実施例によるリングトリツプ方式
を示す図であり、第3図は第2図における動作シ
ーケンスを例示する図である。なお、全図を通じ
て同一符号は同一対象を示す。第2図において、
演算増幅器15および16、および抵抗17乃至
20は比較回路CMP1を構成し、計数器23、
減算器24、数値比較器35、シフトレジスタ2
5、フリツプフロツプ26、ゲート27および2
8は計数回路CTRを構成し、またデコーダ29、
フリツプフロツプ回路30は比較回路CMP2を
構成する。第1図同様、第2図においても被呼者
が応答する迄は端子3および4に接続される電話
機5には第3図に示される如き呼出信号電流irの
みが供給される。比較回路CMP1は呼出信号電
流irにより抵抗2の両端に生ずる交流電圧を所定
の基準値例えば0ボルトを基準値として比較し、
前記交流電圧が0ボルト以上の時は比較回路出力
RTPを論理値1に設定し、また前記交流電圧が
0ボルト以下の場合には比較回路出力RTPを論
理値0に設定する。従つて第3図の時点t1乃至t6
に示される呼出信号電流irに対し、比較回路出力
RTPは時点t1乃至t2およびt4乃至t5において論理
値1に、時点t2乃至t4およびt5乃至t6において論
理値0に設定される。この時に呼出信号電流の波
形は正と負における対称性がないことが通例であ
るため、t1からt2の正の期間における時間幅とt2
からt3の負の期間における時間幅とは異なつてい
る。また比較回路CMPを構成している抵抗18
と19,20と17との間で相対値精度、並びに
演算増幅器16での誤差によつても正の時間幅と
負の時間幅とは一致しないことになる。この不一
致は比較回路CMPに繋がる計数回路CTRでの正
常な動作を擾乱することになる。該比較回路出力
RTPは計数回路CTRのフリツプフロツプ26に
より所定の周期例えば8キロヘルツクロツク信号
CLに同期化されたのち、計数器23およびシフ
トレジスタ25に入力される。該計数器23は入
力された同期化された比較回路出力RTPが論理
値1の場合には8キロヘルツクロツク信号CLの
クロツクパルスをひとつづつ加算し、また該比較
回路出力RTPが論理値0の場合には8キロヘル
ツクロツク信号CLのクロツクパルスをひとつづ
つ減算する。このクロツク信号CLによる同期化
の際には所謂サンプリング誤差が発生し、計数値
は常に+/−1カウントだけズレることになる。
このズレは最悪の場合、呼出信号電流の周期(約
16Hz)毎に+1されるため、この差が計数回路の
計数値に誤差として堆積されることになる。比較
回路出力RTPの論理値に応じて、計数回路の加
算動作と減算動作が切替えられ、一種の加算動作
に引き続き実行される一連の減算動作によつて、
計数値は常に0となるように、計数回路CTRが
動作するように設定されている。つまり、トリツ
プされていない状態では、呼出信号電流の一周期
毎に、計数回路の計数値が0となるように設定さ
れているばずである。しかし、現実には、前述の
呼出信号電流の波形の正極性側と負極性側との非
対称性、比較回路のCMPにおける精度および計
数回路でのサンプリング誤差が原因となり、呼出
信号電流の一周期毎に0にはならない。例えば、
呼出信号電流の一周期毎に残る誤差をmとする
と、一周期毎にmが堆積されていく。この堆積に
よる積算値が後述の閾値Ntを越えてしまうと、
トリツプしていないにもかかわらず後述の検出出
力RTOからはトリツプ信号が出力されてしまう。
この誤差メカニズムを解消するために、減算差2
4は計数数器23の計数値Nから予め定められた
数値Mを減ずる。且つ数値比較器35がN−M≧
0であることを判定すると、計数器23に初期設
定値N−Mとして供給し、一方N−M<0と判定
すると計数器23に0を初期設定する。シフトレ
ジスタ25およびゲート27は周知の微分回路を
構成しており、前記比較回路出力RTPの論理値
1から論理値0への変換点(時点t2およびt5)を
検出して、設定信号LDを計数器23へ供給する。
計数器23は該設定信号LDに応動して、減算器
24から供給される初期設定値N−Mに計数値を
設定する。(なお、時間間隔t2乃至t2′およびt5乃
至t8′はシフトレジスタ25の具備する遅延時間
により定まる。)従つて、計数器23の計数値N
は時点t1に0から一つづつ増加し、時点t2にN1に
迄達した後時点t2′に至る迄N1−Mに初期設定さ
れ、以後一つづつ減少して時点t3に0になる。該
計数値Nは比較回路CMP2のデコーダ29にも
伝達される。デコーダ29は受領する計数値Nが
Oになつたことを検出すると、論理値Oの前記比
較回路出力RTPにより通常状態にあるゲート2
8を経由して、計数器23に停止信号IHを伝達
し、計数を停止させる。該停止信号IHは、時点
t3から次の加算開始時(この場合時点t4)まで計
数値NをOに維持する。かくして前記比較回路
RTPが再び論理値1に変換する時点t4から計数
器23は一つづつ加算を開始し、計数値Nが再び
N1に達した時点t5に前記比較回路出力RTPが再
び論理値0に変換することにより加算を停止し、
時点t5に計数値NをN1−Mに初期設定した後、
計数値NがOになるまで、一つづつ減算を行う。
一方、時点t7に被呼者が応答すると、電話機5に
は呼出信号電流irに重畳して直流電流idが供給さ
れる。なお応答による電話機5の内部インピーダ
ンスの減少により、呼出信号電流ir自体も増加す
る(第3図参照)。その結果、比較回路CMP1は
時点t7以後増加した呼出信号電流irおよび直流電
流idにより抵抗2の両端に生ずる電圧を基準値0
ルトと比較し、時点t6乃至t8およびt9乃至t10に比
較回路出力RTPを論理値1に、時点t3乃至t9およ
びt10乃至t11に比較回路出力RTPを論理値0に設
定する。該比較回路出力RTPを受領した計数回
路CTRは、時点t6からt8迄8キロヘルツクロツク
信号CLにより一つづつ加算するが、時間間隔t6
乃至t8が時間間隔t1乃至t2あるいはt4乃至t5に比し
増加しているため時点t8における計数値Nは時点
t2あるいはt5におけるN1よりも高いN2に達する。
以後、前述の如く設定信号LDにより時点t8から
時点t8′に至るまでN2−Mに初期設定された後時
点t9まで、一づつ減算するが、時間間隔t8乃至t9
は時間間隔t6乃至t8に比べ遥かに短縮されている
ため、計数値Nは時点t9迄にN3迄減少するのみ
であり、時点9からはN3を初期値として再び一づ
つ加算することを開始する。その結果計数値Nは
時間と共に増加する。一方、比較回路CMP2の
デコーダ29は受領する計数値Nを予め定められ
た閾値Nt(Nt>N1)と比較し、該閾値Ntを越え
たことを検出すると端子33から処理装置等から
受領する呼出信号送出指示信号SDにより導通状
態にあるゲート30を介してフリツプフロツプ3
2をセツトさせる。その結果、該フリツプフロツ
プ32ら端子34に対しリングトリツプ信号
RTOが出力され(時点t12)処理装置等に被呼者
の応答を通知する。 An embodiment of the present invention will be described below with reference to FIGS. 2 and 3. FIG. 2 is a diagram showing a ring trip system according to an embodiment of the present invention in a calling signal sending circuit, and FIG. 3 is a diagram illustrating the operation sequence in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures. In Figure 2,
Operational amplifiers 15 and 16 and resistors 17 to 20 constitute a comparator circuit CMP1, and a counter 23,
Subtractor 24, numerical comparator 35, shift register 2
5, flip-flop 26, gate 27 and 2
8 constitutes a counting circuit CTR, and a decoder 29,
The flip-flop circuit 30 constitutes a comparison circuit CMP2. Similar to FIG. 1, in FIG. 2, only the ringing signal current ir as shown in FIG. 3 is supplied to the telephone 5 connected to terminals 3 and 4 until the called party answers. The comparison circuit CMP1 compares the AC voltage generated across the resistor 2 by the calling signal current ir with a predetermined reference value, for example, 0 volts as the reference value,
When the AC voltage is 0 volts or more, the comparator circuit outputs
RTP is set to a logical value of 1, and the comparator circuit output RTP is set to a logical value of 0 when the alternating current voltage is less than 0 volts. Therefore, the time points t 1 to t 6 in FIG.
For the ringing signal current ir shown in , the comparator circuit output
RTP is set to logic 1 at times t 1 to t 2 and t 4 to t 5 and to logic 0 at times t 2 to t 4 and t 5 to t 6 . At this time, since the waveform of the ringing signal current usually has no symmetry between positive and negative, the time width in the positive period from t 1 to t 2 and t 2
The time width in the negative period from t to 3 is different. Also, the resistor 18 that constitutes the comparison circuit CMP
The positive time width and the negative time width do not match due to the relative value accuracy between and 19, 20 and 17, as well as the error in the operational amplifier 16. This mismatch disturbs the normal operation of the counting circuit CTR connected to the comparison circuit CMP. The comparison circuit output
RTP is clocked at a predetermined period, for example, by an 8 kHz clock signal, by the flip-flop 26 of the counting circuit CTR.
After being synchronized with CL, it is input to the counter 23 and shift register 25. The counter 23 adds the clock pulses of the 8 kHz clock signal CL one by one when the input synchronized comparator output RTP has a logic value of 1, and adds the clock pulses of the 8 kHz clock signal CL one by one when the input synchronized comparison circuit output RTP has a logic value of 0. The clock pulses of the 8 kHz clock signal CL are subtracted one by one. During synchronization using the clock signal CL, a so-called sampling error occurs, and the counted value always deviates by +/-1 count.
In the worst case, this deviation is caused by the period of the ringing signal current (approximately
16Hz), this difference is accumulated as an error in the count value of the counting circuit. Depending on the logical value of the comparison circuit output RTP, the addition operation and subtraction operation of the counting circuit are switched, and by a series of subtraction operations that are performed following a type of addition operation,
The counting circuit CTR is set to operate so that the counted value is always 0. That is, in the non-tripped state, the count value of the counting circuit should be set to 0 for each cycle of the ringing signal current. However, in reality, due to the aforementioned asymmetry between the positive and negative polarity sides of the waveform of the ringing signal current, the accuracy of the CMP of the comparator circuit, and the sampling error of the counting circuit, every cycle of the ringing signal current does not become 0. for example,
If the error remaining for each cycle of the calling signal current is m, then m is accumulated for each cycle. If the accumulated value due to this accumulation exceeds the threshold value Nt described later,
Even though it is not tripped, a trip signal is output from the detection output RTO, which will be described later.
In order to eliminate this error mechanism, the subtraction difference 2
4 subtracts a predetermined value M from the count value N of the counter 23. And the numerical comparator 35 is N−M≧
If it is determined that it is 0, it is supplied to the counter 23 as an initial setting value N-M, and on the other hand, if it is determined that NM<0, the counter 23 is initially set to 0. The shift register 25 and the gate 27 constitute a well-known differentiating circuit, which detects the conversion point (times t 2 and t 5 ) of the comparison circuit output RTP from logic value 1 to logic value 0, and outputs the setting signal LD. is supplied to the counter 23.
The counter 23 responds to the setting signal LD and sets the count value to the initial setting value NM supplied from the subtracter 24. (The time intervals t 2 to t 2 ' and t 5 to t 8 ' are determined by the delay time provided by the shift register 25.) Therefore, the count value N of the counter 23
increases by one from 0 at time t 1 , reaches N 1 at time t 2 , is initialized to N 1 −M until reaching time t 2 ', and decreases by one after that until time t 3 becomes 0. The count value N is also transmitted to the decoder 29 of the comparator circuit CMP2. When the decoder 29 detects that the received count value N has become O, the gate 2 which is in the normal state according to the comparator circuit output RTP of the logical value O
8, a stop signal IH is transmitted to the counter 23 to stop counting. The stop signal IH is
The count value N is maintained at O from t 3 until the start of the next addition (in this case, time t 4 ). Thus, the comparison circuit
The counter 23 starts adding one by one from time t 4 when RTP converts to logical value 1 again, and the count value N is again
At the time t5 when N1 is reached, the comparator circuit output RTP is again converted to a logical value of 0, thereby stopping the addition;
After initializing the count value N to N 1 −M at time t 5 ,
Subtraction is performed one by one until the count value N becomes O.
On the other hand, when the called party answers at time t7 , the direct current id is supplied to the telephone 5 superimposed on the ringing signal current ir. Note that due to the decrease in the internal impedance of the telephone 5 due to the response, the ringing signal current ir itself also increases (see FIG. 3). As a result, the comparator circuit CMP1 converts the voltage generated across the resistor 2 due to the ringing signal current ir and the DC current id, which have increased after time t7 , to the reference value 0.
The comparison circuit output RTP is set to logic value 1 at time points t 6 to t 8 and t 9 to t 10 , and the comparison circuit output RTP is set to logic value 0 at time points t 3 to t 9 and t 10 to t 11 . Set. The counting circuit CTR that receives the comparator output RTP increments one by one from time t 6 to t 8 using the 8 kHz clock signal CL, but the time interval t 6
Since the time interval t 1 to t 8 is increasing compared to the time interval t 1 to t 2 or t 4 to t 5 , the count value N at time t 8 is
It reaches N 2 higher than N 1 at t 2 or t 5 .
Thereafter, as described above, N2 - M is initially set from time t8 to time t8 ' by the setting signal LD, and then subtracted by one until time t9 , but the time interval t8 to t9
is much shorter than the time interval t 6 to t 8 , so the count value N only decreases to N 3 by time t 9 , and from time 9 onwards, it is added one by one again with N 3 as the initial value. start doing. As a result, the count value N increases with time. On the other hand, the decoder 29 of the comparator circuit CMP2 compares the received count value N with a predetermined threshold value Nt (Nt>N 1 ), and when it detects that the threshold value Nt has been exceeded, the decoder 29 receives the count value N from the processing device etc. from the terminal 33. The flip-flop 3 is connected to the flip-flop 3 via the gate 30 which is in a conductive state due to the calling signal sending instruction signal SD.
Set 2. As a result, a ring trip signal is generated from the flip-flop 32 to the terminal 34.
RTO is output (time t 12 ) and notifies the processing device etc. of the called party's response.
以上の説明から明らかな如く、本実施例によれ
ば比較回路CMP1およびCMP2並びに計数回路
CTRは何れも大容量コンデンサ等の大形部品を
使用せず、高密度実装可能な構成を有している。 As is clear from the above explanation, according to this embodiment, the comparison circuits CMP1 and CMP2 and the counting circuit
All CTRs have a structure that allows high-density mounting without using large components such as large-capacity capacitors.
なお、第2図および第3図はあく迄本発明の一
実施例に過ぎず、例えば計数器23の計数値N
は、時点t2乃至t2′およびt5乃至t5′に初期設定する
ものに限定されることは無く、比較回路出力
RTPの論理値Oから論理値1への変換値1への
変換点、例えば時点t1からシフトレジスタ25の
遅延時間により定まる期間の任意の時点に初期設
定することも考慮されるが、かかる場合にも本発
明の効果は変らない。また計数器23の計数値N
は時点t2およびt5においてMを減算することなく
一づつ減算することを開始し、該減算終了時点に
おける計数値Nの絶対値が所定値以内の時は該計
数値NをOに設定することも考慮されるが、かか
る場合にも本発明の効果は変らない。また比較回
路CMP1,CMP2あるいは計数回路CTRの構成
は図示されるものに限定されることは無く、他に
幾多の変形が考慮されるが、何れの場合にも本発
明の効果は変らない。また呼出信号電流irおよび
直直流電流idの波形は図示されるものに限定され
ることは無く、電話機5を接続する線路条件等に
より種々変化するが、何れの場合にも本発明の効
果は変らない。更に呼出信号を受信する装置は電
話機に限定されぬことは言う迄もない。 Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the count value N of the counter 23
is not limited to what is initially set at time t 2 to t 2 ′ and from t 5 to t 5 ′, and the comparison circuit output
It is also possible to initialize the conversion point from the logical value O of RTP to the logical value 1, for example, at any point in the period determined by the delay time of the shift register 25 from time t1 , but in such a case However, the effect of the present invention remains unchanged. Also, the count value N of the counter 23
starts subtracting M one by one without subtracting M at times t 2 and t 5 , and sets the count N to O when the absolute value of the count N at the end of the subtraction is within a predetermined value. Although this is also considered, the effects of the present invention do not change even in such a case. Further, the configurations of the comparison circuits CMP1, CMP2 or the counting circuit CTR are not limited to those shown in the drawings, and many other modifications may be considered, but the effects of the present invention remain the same in either case. Furthermore, the waveforms of the ringing signal current ir and the DC/DC current id are not limited to those shown in the figure, and may vary depending on the line conditions connecting the telephone 5, etc., but the effects of the present invention will not change in any case. do not have. Furthermore, it goes without saying that the device for receiving the calling signal is not limited to a telephone.
以上、本発明によれば大形部品を使用する必要
のないリングトリツプ方式が実現可能となり、電
話交換機の呼出信号送出回路の小形化・高密度実
装が可能となることに加え、比較回路並びに論理
回路のみで所望の機能を実現できるので集積回路
化が可能な構成を有しており、今日のLSI技術に
よれば単一集積回路上に構成することも可能とな
る。 As described above, according to the present invention, it is possible to realize a ring trip method that does not require the use of large components, and in addition to making it possible to downsize and high-density mounting the ringing signal sending circuit of a telephone exchange, it also enables comparison circuits and logic circuits. It has a configuration that can be integrated into an integrated circuit because it can realize the desired function with only one device, and with today's LSI technology, it can also be configured on a single integrated circuit.
第1図は呼出信号送出回路の従来あるリングト
リツプ方式の一例を示す図、第2図は呼出信号送
出回路における本発明の一実施例によるリングト
リツプ方式を示す図、第3図は第2図における動
作シーケンスを例示する図である。
図において、1は呼出信号電流、2,7,8,
10,17乃至20は抵抗、3,4,14,33
および34は端子、5は電話機、6は直流電源、
9はコンデンサ、11はトランジスタ、12は定
電圧ダイオード、13はリレー、13′は接点、
15および16は演算増幅器、23は計数器、2
4は減算器、25はシフトレジスタ、26および
32はフリツプフロツプ、27,28,30およ
び31はゲート、29はデコーダ、35は数値比
較器、CMP1およびCMP2は比較回路、CTRは
計数回路、irは呼出信号電流、idは直流電流、
RTPは比較回路出力、LDは設定信号、IHは停止
信号、N,N1,N2およびN3は計数値、CLはク
ロツク信号、N−Mは初期値、Ntは閾値、SDは
呼出信号送出指示信号、RTOはリングトリツプ
信号、t1乃至t2およびt2′,t5′,t8′は時点を示す。
FIG. 1 is a diagram showing an example of a conventional ring trip method for a calling signal sending circuit, FIG. 2 is a diagram showing a ring trip method according to an embodiment of the present invention in a calling signal sending circuit, and FIG. 3 is an operation in FIG. 2. It is a figure which illustrates a sequence. In the figure, 1 is the ringing signal current, 2, 7, 8,
10, 17 to 20 are resistors, 3, 4, 14, 33
and 34 is a terminal, 5 is a telephone, 6 is a DC power supply,
9 is a capacitor, 11 is a transistor, 12 is a constant voltage diode, 13 is a relay, 13' is a contact,
15 and 16 are operational amplifiers, 23 is a counter, 2
4 is a subtracter, 25 is a shift register, 26 and 32 are flip-flops, 27, 28, 30 and 31 are gates, 29 is a decoder, 35 is a numerical comparator, CMP1 and CMP2 are comparison circuits, CTR is a counting circuit, and ir is a Ringing signal current, ID is DC current,
RTP is the comparison circuit output, LD is the setting signal, IH is the stop signal, N, N 1 , N 2 and N 3 are the count values, CL is the clock signal, NM is the initial value, Nt is the threshold value, SD is the calling signal The transmission instruction signal RTO is a ring trip signal, and t 1 to t 2 and t 2 ′, t 5 ′, and t 8 ′ indicate time points.
Claims (1)
信号電流を所定の基準値と比較する第一の比較回
路と、 加算と減算の二つの異なる計数動作が選択可能
で、該呼出信号電流の周期より短い周期のクロツ
クを加算または減算する計数回路と、 該第一の比較回路が該呼出信号電流を該基準値
以上と判定する期間と該基準値以下と判定する期
間との変化点を検出し、該計数回路の計数動作を
加算から減算または減算から加算に切り替える切
替回路と、 該計数回路の計数値を所定の閾値と比較し、該
計数値が該閾値を越えたことにより、該呼出信号
電流に重畳された直流電流を検出して、リングト
リツプ信号を出力する第二の比較回路とを備えた
呼出信号送出回路において、 前記変化点で、前記計数回路の計数値から、予
め定められた補正値を減算する減算器と、 前記計数回路の減算動作中に、計数値が零を示
すことを検出した際、前記切替回路により前記変
化点が検出されるまで、該計数回路の減算を停止
させる第三の比較回路とを備えたことを特徴とす
るリングトリツプ回路。[Scope of Claims] 1. A first comparison circuit that compares a constant cycle ringing signal current sent by the ringing signal sending circuit with a predetermined reference value; a counting circuit that adds or subtracts a clock having a cycle shorter than the cycle of the ringing signal current, and a period in which the first comparator circuit determines that the ringing signal current is greater than or equal to the reference value, and a period in which the first comparison circuit determines that the ringing signal current is less than or equal to the reference value; A switching circuit that detects a change point and switches the counting operation of the counting circuit from addition to subtraction or from subtraction to addition; and a switching circuit that compares the count value of the counting circuit with a predetermined threshold value and determines that the count value exceeds the threshold value. Accordingly, in a calling signal sending circuit comprising a second comparison circuit that detects a direct current superimposed on the calling signal current and outputs a ring trip signal, at the change point, from the count value of the counting circuit, a subtracter that subtracts a predetermined correction value; and a subtracter that subtracts a predetermined correction value when the counting circuit detects that the count value indicates zero during the subtraction operation of the counting circuit until the change point is detected by the switching circuit. and a third comparison circuit for stopping the subtraction of the ring trip circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19707381A JPS5897949A (en) | 1981-12-08 | 1981-12-08 | Ring trip system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19707381A JPS5897949A (en) | 1981-12-08 | 1981-12-08 | Ring trip system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5897949A JPS5897949A (en) | 1983-06-10 |
JPH0241941B2 true JPH0241941B2 (en) | 1990-09-20 |
Family
ID=16368260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19707381A Granted JPS5897949A (en) | 1981-12-08 | 1981-12-08 | Ring trip system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5897949A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE9400186D0 (en) * | 1994-01-21 | 1994-01-21 | Ericsson Telefon Ab L M | Procedure in a telecommunications system |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50104509A (en) * | 1974-01-18 | 1975-08-18 | ||
JPS56131246A (en) * | 1980-02-19 | 1981-10-14 | Cselt Centro Studi Lab Telecom | Telephone circuit for generating ringing rhythm and detecting off-hook state |
-
1981
- 1981-12-08 JP JP19707381A patent/JPS5897949A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50104509A (en) * | 1974-01-18 | 1975-08-18 | ||
JPS56131246A (en) * | 1980-02-19 | 1981-10-14 | Cselt Centro Studi Lab Telecom | Telephone circuit for generating ringing rhythm and detecting off-hook state |
Also Published As
Publication number | Publication date |
---|---|
JPS5897949A (en) | 1983-06-10 |
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