JPH024170B2 - - Google Patents
Info
- Publication number
- JPH024170B2 JPH024170B2 JP54156621A JP15662179A JPH024170B2 JP H024170 B2 JPH024170 B2 JP H024170B2 JP 54156621 A JP54156621 A JP 54156621A JP 15662179 A JP15662179 A JP 15662179A JP H024170 B2 JPH024170 B2 JP H024170B2
- Authority
- JP
- Japan
- Prior art keywords
- reference voltage
- logic
- power supply
- voltage
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Dc Digital Transmission (AREA)
Description
【発明の詳細な説明】
本発明は基準電圧発生回路を有する集積回路装
置に係り、特に電流切換型論理回路（CML）に
基準電圧を供給する基準電圧発生回路に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device having a reference voltage generation circuit, and more particularly to a reference voltage generation circuit that supplies a reference voltage to a current switching logic circuit (CML).
近時、集積回路の高速化、低電力化の必要性に
より、より小さい論理振幅の電流切換型論理回路
（CML）が要求されると共に、より安定な論理動
作を保証するための最適な基準電圧の供給に関し
ての重要性が増している。第１図に２入力AND
ゲートに対する従来の基準電圧供給の方法を示
す。２入力ANDゲートＧ１はＧ２，Ｇ３の各ゲ
ートの出力Ａ，ＢをトランジスタQ1，Q2のベー
スに入力し、AND出力Ｃ、NAND出力をそれ
ぞれQ3，Q2のコレクタより出力している。但し、
負論理で考えているので高レベルの信号は論理
“０”、低レベルの信号は、論理“１”である。各
ゲートは定電流Ioを引く定電流源及び、出力負荷
抵抗R1〜R6を有する。論理振幅Vlはすべて同じ
と考えR1〜R6に同じ値Rcをとる。トランジスタ
Q3のベースには基準電圧発生回路IRGより基準
電圧VRIが印加されている。尚、基準電圧VRIは集
積回路外部より印加される場合もある。基準電圧
発生回路は論理レベルの中間値をとるため、ゲー
トと同一の定電流Ioを用いた場合、負荷抵抗は各
ゲートの負荷抵抗値Rcの半分の値を取る。通常
製造変動による基準電圧のずれによる影響を抑え
るため、ゲートの負荷抵抗と同じ値Rcの抵抗R7，
R8を並列接続し使用している。従つて基準電圧
VRI＝IoRc／２となり論理振幅Vl＝IoRcの中間値
が設定される。しかし集積回路内では電源配線に
配線抵抗があることから、電源の電圧降下が生
じ、論理レベルがその電圧降下分だけずれること
が予測される。特に多くの論理素子を集積したチ
ツプサイズの大きいLSIでは電源配線も長く又多
くの電流が流れ、電源のチツプ内での電圧降下が
無視出来ない状態となつている。ゲートＧ１及び
基準電圧発生回路IRGでの電源配線を電位の基準
Ｖ０としてゲートＧ２，Ｇ３の基準に対する電圧
降下をそれぞれ△V2，△V3とするとゲートＧ２，
Ｇ３からの信号Ａ，Ｂに対して基準電圧VRI＝
Vl／２の時の高レベル“０”に対してのマージ
ンVmはそれぞれ
Vm2＝Vl／２−△V2 …(1)
Vm3＝Vl／２−△V3 …(2)
となり、論理振幅Vlに対しとれる最大のマージ
ンVl／２より基準電圧発生回路の電源配線から
の相対電圧下降分△V2，△V3だけマージンが減
少する事となる。従つて電圧降下分△Ｖが大きく
なつた場合、入力論理レベル保証マージンが少く
なくなり不完全な論理動作により次段への論理振
幅が十分得られない可能性が考えられる。論理振
幅の影響を受け易い回路への信号を安定に発生す
るためのゲートに基準電圧を用いず、差動入力で
AND回路を構成する方法がある。第２図に差動
入力を用い、信号ＡとＢのAND論理を実行する
回路を示す。この方法では完全な論理動作が行な
われ、安定した出力振幅が得られるが、基準電圧
を用いた時のAND回路の構成に比べ、レベルシ
フトのためのエミツタホロワの付加、相補出力信
号線の配線など素子数、配線数の増大及び複数な
論理を作る事が難しいという欠点を有する。 Recently, due to the need for faster and lower power integrated circuits, current switching logic circuits (CML) with smaller logic amplitude are required, as well as optimal reference voltages to ensure more stable logic operation. supply is becoming increasingly important. Figure 1 shows two inputs AND
A conventional method of supplying a reference voltage to a gate is shown. The 2-input AND gate G1 inputs the outputs A and B of the gates G2 and G3 to the bases of the transistors Q 1 and Q 2 , and outputs the AND output C and the NAND output from the collectors of Q 3 and Q 2 , respectively. . however,
Since we are considering negative logic, a high level signal is a logic "0" and a low level signal is a logic "1". Each gate has a constant current source drawing a constant current Io and output load resistances R1 to R6 . Considering that all logic amplitudes Vl are the same, the same value Rc is taken for R 1 to R 6 . transistor
A reference voltage V RI is applied to the base of Q 3 from a reference voltage generation circuit IRG. Note that the reference voltage VRI may be applied from outside the integrated circuit. Since the reference voltage generation circuit takes an intermediate value between logic levels, when the same constant current Io as that of the gate is used, the load resistance takes a value half the load resistance value Rc of each gate. In order to suppress the influence of deviations in the reference voltage due to normal manufacturing variations, a resistor R7 with the same value Rc as the gate load resistance is used.
I am using R8 connected in parallel. Therefore the reference voltage
V RI =IoRc/2, and the intermediate value of the logical amplitude Vl = IoRc is set. However, since there is wiring resistance in the power supply wiring within an integrated circuit, a voltage drop in the power supply occurs, and it is expected that the logic level will shift by the amount of the voltage drop. Particularly in large-chip LSIs that integrate many logic elements, the power supply wiring is long and a large amount of current flows, and the voltage drop within the power supply chip cannot be ignored. Assuming that the power supply wiring for gate G1 and reference voltage generation circuit IRG is a potential reference V0, and the voltage drops of gates G2 and G3 with respect to the reference are △V 2 and △V 3 , respectively, gate G2,
Reference voltage V RI = for signals A and B from G3
The margin Vm for the high level “0” when Vl/2 is Vm 2 = Vl/2−△V 2 …(1) Vm 3 = Vl/2−△V 3 …(2), and the logic The margin is reduced by the relative voltage drop △V 2 and △V 3 from the power supply wiring of the reference voltage generation circuit from the maximum margin Vl/2 that can be taken for the amplitude Vl. Therefore, when the voltage drop ΔV increases, the input logic level guarantee margin decreases, and there is a possibility that a sufficient logic amplitude to the next stage cannot be obtained due to incomplete logic operation. In order to stably generate signals to circuits that are easily affected by logic amplitude, a reference voltage is not used for the gate, and differential input is used.
There is a way to configure an AND circuit. FIG. 2 shows a circuit that uses differential inputs and executes AND logic of signals A and B. This method performs complete logic operation and provides stable output amplitude, but compared to the AND circuit configuration when using a reference voltage, it requires the addition of an emitter follower for level shifting and the wiring of complementary output signal lines. This method has the disadvantages of increasing the number of elements and wiring, and making it difficult to create multiple logics.
本発明の目的は電源配線の電圧降下にかかわら
ず、常に最適な基準電圧を供給することにあり、
より安定な論理動作を提供することにある。 The purpose of the present invention is to always supply an optimal reference voltage regardless of the voltage drop in the power supply wiring.
The purpose is to provide more stable logical operation.
本発明は複数個の電流切換型論理回路（CML）
からの信号が入力として与えられるCMLの基準
電圧を供給する回路装置において、前記複数個の
CMLの負荷抵抗が接続されいる電源配線の十分
に近い傍の電位を基準として構成した基準電圧発
生回路で電源配線の電圧降下を基準電圧発生回路
に反映して入力の論理レベルに対し最適な基準電
圧を与え論理動作の安定化を図るという効果があ
る。 The present invention utilizes a plurality of current switching logic circuits (CML).
In a circuit device that supplies a reference voltage of a CML to which a signal from a plurality of
The reference voltage generation circuit is configured based on the potential sufficiently close to the power supply wiring to which the CML load resistor is connected, and reflects the voltage drop of the power supply wiring to the reference voltage generation circuit to create an optimal standard for the input logic level. This has the effect of applying voltage and stabilizing logic operation.
第３図に従来の方法による第１図に対応した
AND回路の本発明による実施例を示す。基準電
圧発生回路の負荷抵抗R7，R8はそれぞれ基準電
圧を与えるゲートＧ１に入力する信号Ａ，Ｂの発
生源であるゲートＧ２，Ｇ３のコレクタ抵抗が接
続されている電源配線の近傍又は同電位の位置か
ら電源を取つている。従つて基準電圧VRIは
VRI＝（Vl＋△V2＋△V3）／２ …(3)
となり入力論理レベルの高レベルに対してマージ
ンVmは
Vm2＝（Vl＋△V2△V3）／２−△V2＝（Vl−△V2
＋△V3）／２…(4)
Vm3＝（Vl＋△V2＋△V3）／２−△V3＝（Vl＋△V
2−△V3）／２…(5)
となる。又低レベルに対してのマージンは
Vml2＝Vl−（Vl−△V2＋△V3）／２＝（Vl＋△V2
−△V3）／２…(6)
Vml3＝Vl−（Vl＋△V2−△V3）／２＝（Vl−△V2
＋△V3）／２…(7)
となる。(4)式、(5)式の和及び(6)式、(7)式の和は
Vlとなり更にVm2＝Vml3、Vm3＝Vml2となる
のでこの基準電圧の設定がゲートＧ２，Ｇ３の両
出力の論理レベルに対して最適なマージンをもた
らしたいる事がわかる。本回路における論理レベ
ルは従来の方法に比べて大巾に改善されている。 Figure 3 corresponds to Figure 1 using the conventional method.
1 shows an embodiment of an AND circuit according to the present invention. The load resistances R 7 and R 8 of the reference voltage generation circuit are located near or on the same side as the power supply wiring to which the collector resistances of the gates G2 and G3, which are the generation sources of the signals A and B input to the gate G1 that provides the reference voltage, are connected. Power is obtained from the position of potential. Therefore, the reference voltage V RI is V RI = (Vl + △V 2 + △V 3 ) / 2 ... (3), and the margin Vm for the high level of the input logic level is Vm 2 = (Vl + △V 2 △V 3 )/2−△V 2 = (Vl−△V 2
+△V 3 )/2…(4) Vm 3 = (Vl+△V 2 +△V 3 )/2-△V 3 = (Vl+△V
2 −△V 3 )/2...(5). Also, the margin for low level is Vml 2 = Vl−(Vl−△V 2 +△V 3 )/2=(Vl+△V 2
−△V 3 )/2…(6) Vml 3 = Vl− (Vl+△V 2 −△V 3 )/2=(Vl−△V 2
+△V 3 )/2...(7). The sum of equations (4) and (5) and the sum of equations (6) and (7) are
Since Vl becomes Vm 2 =Vml 3 and Vm 3 =Vml 2 , it can be seen that this setting of the reference voltage provides an optimal margin for the logic levels of both outputs of gates G2 and G3. The logic level in this circuit is greatly improved compared to conventional methods.
本発明は抵抗値を変える事なく配線だけによ
り、入力レベルのずれた２入力信号に対し最適な
基準電圧を与える特徴があり、マスタースライス
等抵抗値を変更出来ない集積回路に有効であり、
更に温度変動、製造変動による電源電流の変化に
よる電源配線の電圧降下に応じ、その条件で最適
な基準電圧を供給するという長所があり安定な論
理動作に大きな効果をもたらす。なお、本実施例
では２入力ANDゲートの例を示したが、３入力
以上のゲート回路であつても、入力数に応じて基
準電圧発生用の抵抗を分割し、夫々の電流切換型
論理回路の負荷抵抗の近くに分散配置すれば本発
明の効果は得られる。ただし、この場合、分散配
置される抵抗の合成抵抗値が基準電圧を発生する
のに必要な論理レベルの中間値を発生できるよう
な値に設定する必要があることはいうまでもな
い。 The present invention has the feature of providing an optimal reference voltage for two input signals with shifted input levels by just wiring without changing the resistance value, and is effective for integrated circuits such as master slices where the resistance value cannot be changed.
Furthermore, it has the advantage of supplying the optimum reference voltage under the conditions in response to the voltage drop in the power supply wiring due to changes in the power supply current due to temperature fluctuations and manufacturing fluctuations, which has a great effect on stable logic operation. Although this embodiment shows an example of a 2-input AND gate, even in gate circuits with 3 or more inputs, the reference voltage generation resistor is divided according to the number of inputs, and each current switching type logic circuit is The effects of the present invention can be obtained by distributing the resistors near the load resistors. However, in this case, it goes without saying that the combined resistance value of the distributed resistors must be set to a value that can generate an intermediate value of the logic levels necessary to generate the reference voltage.
第１図は従来の基準電圧発生回路を示す回路
図、第３図は本発明による実施例を示す回路図で
ある。第２図は差動CMLによるAND回路を示す
回路図である。図中、Ｇ１〜Ｇ３はゲート、IRG
は基準電圧発生回路、Ａ〜Ｃは信号、Ioは定電流
値、R1〜R3は負荷抵抗、Q1〜Q7はトランジス
タ、Ｖ０，Ｖ１は定電圧源、VRは基準電圧、△
V2及び△V3はそれぞれ電源配線における基準レ
ベル（GND）に対して電位降下を各々示す。
FIG. 1 is a circuit diagram showing a conventional reference voltage generating circuit, and FIG. 3 is a circuit diagram showing an embodiment according to the present invention. FIG. 2 is a circuit diagram showing an AND circuit using differential CML. In the figure, G1 to G3 are gates, IRG
is a reference voltage generation circuit, A to C are signals, Io is a constant current value, R 1 to R 3 are load resistances, Q 1 to Q 7 are transistors, V0 and V1 are constant voltage sources, V R is a reference voltage, △
V 2 and ΔV 3 each represent a potential drop with respect to the reference level (GND) in the power supply wiring.
Claims (1)
理回路から独立に取り出される複数の出力信号を
個個にうける複数の入力トランジスタと基準電圧
が印加されるトランジスタとを有し、前記複数の
電流切換型論理回路とは電源配線の電圧降下によ
り電源電圧が各々異なる程度に離れて配置された
論理ゲート回路を含む集積回路装置において、前
記基準電圧を発生するための基準電圧発生回路の
基準電圧発生用抵抗を前記複数の電流切換型論理
回路の前記負荷抵抗の近くに分散配置することに
より、電流切換型論理回路の各々の負荷抵抗に印
加される電源電圧と同じ電圧が分散配置された前
記基準電圧発生用抵抗にも印加されるようにした
ことを特徴とする集積回路装置。1. It has a plurality of input transistors that individually receive a plurality of output signals taken out independently from a plurality of current switching logic circuits each having a load resistance, and a transistor to which a reference voltage is applied, and the plurality of current switching What is a type logic circuit? A type logic circuit is a reference voltage generating circuit used in a reference voltage generating circuit for generating the reference voltage in an integrated circuit device that includes logic gate circuits that are placed apart from each other so that the power supply voltages differ depending on the voltage drop of the power supply wiring. By distributing resistors near the load resistors of the plurality of current switching logic circuits, the reference voltage is distributed such that the same voltage as the power supply voltage applied to each load resistor of the current switching logic circuits is distributed. An integrated circuit device characterized in that a voltage is also applied to a generating resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15662179A JPS5679531A (en) | 1979-12-03 | 1979-12-03 | Reference voltage generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15662179A JPS5679531A (en) | 1979-12-03 | 1979-12-03 | Reference voltage generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5679531A JPS5679531A (en) | 1981-06-30 |
| JPH024170B2 true JPH024170B2 (en) | 1990-01-26 |
Family
ID=15631708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15662179A Granted JPS5679531A (en) | 1979-12-03 | 1979-12-03 | Reference voltage generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5679531A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3329835A (en) * | 1964-11-20 | 1967-07-04 | Rca Corp | Logic arrangement |
| JPS52114260A (en) * | 1976-03-22 | 1977-09-24 | Hitachi Ltd | Standard voltage generation circuit |
-
1979
- 1979-12-03 JP JP15662179A patent/JPS5679531A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3329835A (en) * | 1964-11-20 | 1967-07-04 | Rca Corp | Logic arrangement |
| JPS52114260A (en) * | 1976-03-22 | 1977-09-24 | Hitachi Ltd | Standard voltage generation circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5679531A (en) | 1981-06-30 |
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