JPH023954A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH023954A JPH023954A JP15440288A JP15440288A JPH023954A JP H023954 A JPH023954 A JP H023954A JP 15440288 A JP15440288 A JP 15440288A JP 15440288 A JP15440288 A JP 15440288A JP H023954 A JPH023954 A JP H023954A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- integrated circuit
- wiring board
- plates
- wiring plates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 229920005989 resin Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 3
- 239000007767 bonding agent Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路装置にかかり、特に一つの封止容器内
に複数個の搭載部品が搭載されている集積回路装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and particularly to an integrated circuit device in which a plurality of components are mounted in one sealed container.
従来、この種の集積回路装置は例えば第１図に示すよう
に単一の成型加工された封止樹脂１とリードフレーム２
とを具備し、第１図のＡ−Ａ’で示す横断面の内部構造
は第４図に示す如きであった。即ちリードフレーム２は
、各々単一の半導体基板９ｉ（ｉ＝ｌ＝ｋ）を搭載すべ
き互いに独立した複数個のダイポンディング領域１２ｉ
（１２１〜ｇ）を具備し、所望の形状に分離形成されて
いるリードフレームと半導体基体との電気的接続は例え
ばワイヤポンディング法による金納線１０ｉ（ｉ＝１〜
ｊ）によって実現されているものである。（例えば特開
昭５４−１２４６９０号）。他の従来例として例えば第
５図に示すように、所望の形状に形成されたリードフレ
ーム２が島状の独立片１３ ｉ （ｉ＝１〜ｐ）を具
備する場合には、この独立片は他のリードフレームにｍ
Ｍされた絶縁性フィルム１４との接着によって機械的に
保持され、しかる後に金細線１０ｉ（ｉ＝１〜ｊ）によ
って半導体基体９１とリードフレーム２、独立片１３ｉ
等とが電気的に接続されるものである（特開昭６２−２
７５４４号）。更にはまた第３の従来例として第６図に
示す例がある。Conventionally, this type of integrated circuit device has a single molded sealing resin 1 and a lead frame 2, as shown in FIG.
The internal structure of the cross section taken along line AA' in FIG. 1 was as shown in FIG. 4. That is, the lead frame 2 has a plurality of mutually independent die bonding regions 12i on which a single semiconductor substrate 9i (i=l=k) is to be mounted.
(121-g), electrical connection between the lead frame and the semiconductor substrate, which are separated and formed into a desired shape, is made by wire bonding, for example, with metal wires 10i (i=1-
j). (For example, JP-A-54-124690). As another conventional example, for example, as shown in FIG. m to other lead frames
It is mechanically held by adhesion to the M-shaped insulating film 14, and then the semiconductor substrate 91, the lead frame 2, and the independent piece 13i are held together by the thin gold wire 10i (i=1 to j).
etc. are electrically connected (Japanese Patent Laid-Open No. 62-2
No. 7544). Furthermore, as a third conventional example, there is an example shown in FIG.
第６図は第１図のＢ−Ｂ’で示す模式的縦断面図の内部
構造をもつ集積回路装置の例である。即ちリードフレー
ムの中央部に配線板４を搭載すべき領域３を配置し、こ
の領域上に個別に所望とされる配線導体を有する単層あ
るいは多層の配線板４を搭載し、更に該配線板４上に複
数個の半導体基体９ｉ（ｉ＝１〜ｋ）あるいはチップコ
ンデンサ等の受動素子基体１１ ｉ （ｉ＝ｌ”ｇ）
を搭載するものである。FIG. 6 is an example of an integrated circuit device having an internal structure shown in a schematic vertical cross-sectional view taken along line BB' in FIG. That is, a region 3 in which the wiring board 4 is to be mounted is arranged in the center of the lead frame, a single-layer or multilayer wiring board 4 having individual desired wiring conductors is mounted on this region, and the wiring board A plurality of semiconductor substrates 9i (i=1 to k) or passive element substrates 11i (i=l''g) such as chip capacitors are mounted on the substrate 4.
It is equipped with.
上述した第４図と第５図に示す従来の集積回路装置は、
搭載すべき半導体基体等の数量が増加した場合あるいは
提供する電子回路の規模が大きくなった場合にはリード
フレームの形状が複雑となり、所望とされるリードフレ
ームは事実上、製造することができなくなるものであっ
た。これに対して第６図に示す集積回路装置は、個別の
電子回路に合致するための単層又は多層の配線板を有し
、而もこの配線板上には半導体基体等が搭載されている
関係上、本集積回路装置は大規模の電子回路を提供する
ことができる反面、プリント板の製作期間が介在するた
めに集積回路装置の開発から出荷迄に多大の時間を要す
るという欠点がある。The conventional integrated circuit device shown in FIGS. 4 and 5 described above is
When the number of semiconductor substrates, etc. to be mounted increases, or when the scale of the electronic circuit to be provided increases, the shape of the lead frame becomes complicated, and it becomes virtually impossible to manufacture the desired lead frame. It was something. On the other hand, the integrated circuit device shown in FIG. 6 has a single-layer or multi-layer wiring board for matching individual electronic circuits, and a semiconductor substrate, etc. is mounted on this wiring board. For this reason, although the present integrated circuit device can provide a large-scale electronic circuit, it has the disadvantage that it takes a lot of time from development to shipment of the integrated circuit device due to the intervening period of manufacturing the printed board.
上述した従来の集積回路装置に対し、本発明は復雑なリ
ードフレームや配線板を個別に製作する必要がなく、し
かも集積回路装置の開発から出荷迄の期間を短時間とす
ることができるという相違点を有するものである。In contrast to the conventional integrated circuit devices described above, the present invention eliminates the need to individually manufacture complicated lead frames and wiring boards, and can shorten the period from development to shipment of integrated circuit devices. They have some differences.
本発明の集積回路装置は第６図に示す構造、を有し、リ
ードフレームと該リードフレーム上に搭載される標準化
された配線板と、該配線板上の半導体基体等とを有し、
前記配線板上は少なくとも２層の配線導電体を有し、し
かも個々の配線導体は少なくとも２点の接続用電極を具
備するものであり、半導体基体は絶縁性接着剤（エポキ
シ樹脂。The integrated circuit device of the present invention has the structure shown in FIG. 6, and includes a lead frame, a standardized wiring board mounted on the lead frame, a semiconductor substrate on the wiring board, etc.
The wiring board has at least two layers of wiring conductors, and each wiring conductor is provided with at least two connection electrodes, and the semiconductor substrate is coated with an insulating adhesive (epoxy resin).
シリコーン樹脂等）により配線板上に搭載されるもので
ある。It is mounted on a wiring board using silicone resin, etc.).
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例（従来例）を示す模式的斜視
図であり、■は封止樹脂、２はリードフレームである。FIG. 1 is a schematic perspective view showing an embodiment (conventional example) of the present invention, in which ▪ indicates a sealing resin and 2 indicates a lead frame.
第２図及び第３図は第１図のＡ−Ａ′で示す横断面の内
部構造を製造工程順に模式的に示した図である。2 and 3 are diagrams schematically showing the internal structure of the cross section taken along the line AA' in FIG. 1 in the order of manufacturing steps.
第２図においてリードフレーム２の中央部に配線板搭載
領域３を設け、この領域上に配線板４を搭載する。配線
板４は例えば２層の導電体パターンを有し５ｉ（ｉ＝１
〜ｎ）は表面の配線導電体（二層目導体）であり、６ｉ
（ｉ＝１〜ｍ）は５ｉ導電体と直交する形状に設けられ
た下層配線導電体（−層目導体）であり、５ｉ、６ｉ導
電体共に黒丸で示す多数のポンディングワイヤ用接続電
極７ｉ（ｉ＝１〜１）を配線板４の表面に有する。In FIG. 2, a wiring board mounting area 3 is provided in the center of the lead frame 2, and a wiring board 4 is mounted on this area. The wiring board 4 has, for example, a two-layer conductor pattern 5i (i=1
~n) is the surface wiring conductor (second layer conductor), and 6i
(i = 1 to m) are lower wiring conductors (-layer conductors) provided in a shape perpendicular to the 5i conductor, and both the 5i and 6i conductors have a number of bonding wire connection electrodes 7i indicated by black circles. (i=1 to 1) on the surface of the wiring board 4.
また所望によりチップコンデンサ等の受動部品搭載用電
極８１，８□を設けることもできる。Moreover, if desired, electrodes 81, 8□ for mounting passive components such as chip capacitors may be provided.
本配線板４をリードフレーム２０所定領域上に搭載した
後に、ＬＳＩやＳＳＩ等の半導体基体９１（ｉ＝１〜ｋ
）を配線板上の所望とする領域上に絶縁性接着剤（エポ
キシ樹脂、シリコーン樹脂等）を用いて搭載する（第３
図）。次に半導体基体と配線板、配線板と配線板、及び
配線板とリードフレームとをポンディングワイヤ１０ｉ
（ｉ＝１〜ｊ）を用いて電気的に相互接続する。After mounting the wiring board 4 on a predetermined area of the lead frame 20, a semiconductor substrate 91 (i=1 to k
) on the desired area on the wiring board using an insulating adhesive (epoxy resin, silicone resin, etc.).
figure). Next, bonding wire 10i is connected between the semiconductor substrate and the wiring board, between the wiring boards and the wiring board, and between the wiring board and the lead frame.
(i=1 to j) for electrical interconnection.
更にはまた、所望により第３図に示すようにチップコン
デンサ１１等の受動部品を配線板上に半田リフロー法等
により搭載し、所望とする回路機能を実現するものであ
る。Furthermore, if desired, as shown in FIG. 3, passive components such as a chip capacitor 11 may be mounted on the wiring board by a solder reflow method or the like to realize a desired circuit function.
本実施例においては配線板導電体を２層導電体として説
明したが、導電体層数は所望により任意の値とすること
ができる。また配線導電体は相互に直交する形状に設け
たが、これらの配線導電体は相互に斜交する形状に設け
ることもできる。In this embodiment, the wiring board conductor is described as a two-layer conductor, but the number of conductor layers can be set to any value as desired. Furthermore, although the wiring conductors are provided in a shape that is orthogonal to each other, these wiring conductors can also be provided in a shape that is oblique to each other.
これらの半導体基体や受動部品等を具備する配線板４は
第１図に示す形状に樹脂封止される。第１図は標準的な
りＩＰ （デュアルインラインパッケージ）構造の形状
であるが、本発明はＳＩＰ（シングルインラインパッケ
ージ）やＱＦＰ （クワッドフラットパッケージ）等の
任意の構造の封止樹脂に対して適用することができる。The wiring board 4 including these semiconductor substrates, passive components, etc. is sealed with resin in the shape shown in FIG. Although Figure 1 shows the shape of a standard IP (dual in-line package) structure, the present invention can be applied to sealing resin of any structure such as SIP (single in-line package) or QFP (quad flat package). be able to.
第２図、第３図から明らかのように、複数の表面配線導
電体５ｉ（ｉ＝１〜ｎ）はたがいに一定の間隔を保って
平行に第１の方向に延在し、複数の下層配線導電体６ｉ
（ｉ＝１〜ｍ）もたがいに一定の間隔を保って平行に第
２の方向に延在している。ここでは第１および第２の方
向は直交している。又、表面導電体に接続され配線板表
面に形成されるポンディングワイヤ用接続電極７ｉ（ｉ
＝１〜１）はたがいに第１および第２の方向においてそ
れぞれ一定の間隔を保ってマトリックス状に点在してい
る。同様に下層配線導電体に接続され配線板表面に形成
されるボンディングワイヤ用接続電極７ｉ（ｉ＝１〜１
）もたがいに第１および第２の方向においてそれぞれ一
定の間隔を保ってマトリックス状に点在している。この
ような配線板は、所定の素子を所定の場所に配置するこ
とにより種々の集積回路装置を得ることが得られるるか
ら汎用性の高いものとなる。本発明の目的を達成するた
めには、上記一定の間隔で平行に延在する両道電体はそ
れぞれ４本以上であることが好ましい。又、それぞれの
両道電体において、そこに接続されマトリックス状に一
定の間隔を保って配置されるボンディング用接続電極は
それぞれ１６個以上であることが好ましい。As is clear from FIGS. 2 and 3, the plurality of surface wiring conductors 5i (i=1 to n) extend parallel to each other in the first direction while maintaining a constant interval, and the plurality of lower layer Wiring conductor 6i
(i=1 to m) also extend parallel to each other in the second direction with a constant interval maintained between them. Here the first and second directions are orthogonal. Further, a bonding wire connection electrode 7i (i) connected to the surface conductor and formed on the surface of the wiring board
=1 to 1) are scattered in a matrix shape with constant intervals maintained in the first and second directions. Similarly, bonding wire connection electrode 7i (i=1 to 1
) are scattered in a matrix shape at constant intervals in the first and second directions. Such a wiring board has high versatility because various integrated circuit devices can be obtained by arranging predetermined elements at predetermined locations. In order to achieve the object of the present invention, it is preferable that the number of both-way electric bodies extending in parallel at a constant interval is four or more. Further, in each of the two-way electric bodies, it is preferable that the number of bonding connection electrodes connected thereto and arranged at regular intervals in a matrix is 16 or more.
以上説明したように本発明は、少なくとも２層の互いに
直交あるいは斜交する配線導電体を具備する配線板をリ
ードフレーム上の所定の位置に搭載し、しかも所望とす
る半導体基体等とを配線板上の任意の位置に絶縁性樹脂
を用いて搭載し、半導体基体−配線板間、配線導電体間
、配線導電体−リードフレーム間等とをボンディングワ
イヤを用いて電気的に接続することにより、複雑なリー
ドフレームや配線板を個別に製作する必要性をなくする
ことができる効果がある。従って本発明によって製造さ
れる集積回路装置は開発から出荷迄の期間が短期間とな
る。As explained above, the present invention mounts a wiring board having at least two layers of wiring conductors perpendicular or oblique to each other at a predetermined position on a lead frame, and furthermore, attaches a desired semiconductor substrate or the like to the wiring board. By mounting an insulating resin at any position on the top and electrically connecting between the semiconductor substrate and the wiring board, between the wiring conductors, between the wiring conductor and the lead frame, etc. using bonding wires, This has the effect of eliminating the need to individually manufacture complicated lead frames and wiring boards. Therefore, the period from development to shipment of the integrated circuit device manufactured according to the present invention is short.
本発明が上記した効果を呈する以上、本発明に用いる材
料や製法、構造、形状等は特に限定を受けるものではな
いことは当然である。As long as the present invention exhibits the above-described effects, it is natural that the materials, manufacturing method, structure, shape, etc. used in the present invention are not particularly limited.
第１図は本発明（従来例を含む）の集積回路装置の模式
的斜視図を示す。第２図及び第３図は第１図のＡ−Ａ’
線の模式的横断面の本発明の実施例の内部構造を製造工
程順に示した図である。第４図及び第５図は従来例の模
式的横断面図であり、第６図は従来例の模式的縦断面図
（第１図Ｂ−Ｂ′線部）である。FIG. 1 shows a schematic perspective view of an integrated circuit device according to the present invention (including a conventional example). Figures 2 and 3 are taken from AA' in Figure 1.
FIG. 3 is a diagram showing the internal structure of an embodiment of the present invention in a schematic cross section of a line in the order of manufacturing steps. 4 and 5 are schematic cross-sectional views of the conventional example, and FIG. 6 is a schematic vertical cross-sectional view of the conventional example (taken along the line B-B' in FIG. 1).
Claims (1)
体を具備する配線板がリードフレーム上の所定の位置に
搭載され、前記配線板上に複数個の半導体基板が絶縁性
樹脂により接着・搭載され、前記複数個の半導体基板が
前記配線板とともに単一の容器内に封止されていること
を特徴とする集積回路装置。A wiring board having at least two layers of wiring conductors that are perpendicular or oblique to each other is mounted at a predetermined position on a lead frame, and a plurality of semiconductor substrates are adhered and mounted on the wiring board using an insulating resin, An integrated circuit device characterized in that the plurality of semiconductor substrates are sealed together with the wiring board in a single container.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15440288A JPH023954A (en) | 1988-06-21 | 1988-06-21 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15440288A JPH023954A (en) | 1988-06-21 | 1988-06-21 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH023954A true JPH023954A (en) | 1990-01-09 |
Family
ID=15583363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15440288A Pending JPH023954A (en) | 1988-06-21 | 1988-06-21 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH023954A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4954755A (en) * | 1982-05-24 | 1990-09-04 | Fusion Systems Corporation | Electrodeless lamp having hybrid cavity |
| EP0400324A2 (en) * | 1989-05-30 | 1990-12-05 | International Business Machines Corporation | Semiconductor package |
-
1988
- 1988-06-21 JP JP15440288A patent/JPH023954A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4954755A (en) * | 1982-05-24 | 1990-09-04 | Fusion Systems Corporation | Electrodeless lamp having hybrid cavity |
| EP0400324A2 (en) * | 1989-05-30 | 1990-12-05 | International Business Machines Corporation | Semiconductor package |
| EP0400324A3 (en) * | 1989-05-30 | 1992-04-15 | International Business Machines Corporation | Semiconductor package |
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