JPH023945A - Estimation method of semiconductor chip on wafer - Google Patents
Estimation method of semiconductor chip on waferInfo
- Publication number
- JPH023945A JPH023945A JP63152809A JP15280988A JPH023945A JP H023945 A JPH023945 A JP H023945A JP 63152809 A JP63152809 A JP 63152809A JP 15280988 A JP15280988 A JP 15280988A JP H023945 A JPH023945 A JP H023945A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- parallel connections
- estimation
- semiconductor chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 8
- 238000005259 measurement Methods 0.000 claims abstract description 23
- 238000011156 evaluation Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000000691 measurement method Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Measuring Leads Or Probes (AREA)
- Measurement Of Resistance Or Impedance (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はウェハー上における半導体チップの評価方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for evaluating semiconductor chips on a wafer.
半導体チップは非常に小さい形状を有する為、ウェハー
」二にＸ方向及びＹ方向に繰り返し配置形成し、チップ
特性を評価した後個々に切り出すのが通常である９この
チップ特性の評価に当っては、ウェハー上の測定配線に
直接針を当てたり、切り出した半導体チップを個々にパ
ッケージに組むなどして数々の測定を行っている。一方
、従来から測定精度を向上させる為に評価用パターンの
構成及び測定方法に色々の工夫がなされて来た。Because semiconductor chips have very small shapes, it is common practice to repeatedly form them on a wafer in the X and Y directions, and then cut them out individually after evaluating the chip characteristics9. A number of measurements are carried out by applying a needle directly to the measurement wiring on the wafer, and by assembling cut-out semiconductor chips into individual packages. On the other hand, various improvements have been made to the configuration of evaluation patterns and measurement methods in order to improve measurement accuracy.
たとえば、容量値を評価する際、チップ個々の容量素子
単体の容量値が小さく、しかも測定精度が要求される場
合には、チップ内における容量素子の並列接続数が異な
る測定径路についてそれぞれ測定し、それぞれの径路で
得られた測定値の差を並列接続数で割る所謂差分評価法
と呼ばれる測定方法を採用することにりより、チップ容
量値を精度高く求めることが行われて来た。For example, when evaluating the capacitance value, if the capacitance value of a single capacitor element in each chip is small and high measurement accuracy is required, each measurement path with a different number of parallel connection of capacitor elements within the chip is measured, Chip capacitance values have been determined with high accuracy by employing a measurement method called the so-called differential evaluation method, in which the difference between the measured values obtained on each path is divided by the number of parallel connections.
第３図および第４図はそれぞれ差分評価法を用いた従来
のチップ容量値の評価方法を示す半導体ウェハー上の評
価用配線パターンの構成図およびそのチップ面の拡大図
である。ここで、Ｃ１は容敬素子の並列接続数が多い側
く測定値大）で、Ｃ２は逆に少ない側（測定鎖車）を示
しており、Ｔ１とＴ２はＣ１を引出す測定用端子、Ｔ２
とＴ３はＣ２を引出した測定端子である（ Ｔ ２はＣ
１とＣ２の共通引出し端子である）。FIGS. 3 and 4 are a configuration diagram of an evaluation wiring pattern on a semiconductor wafer and an enlarged view of the chip surface, respectively, showing a conventional method for evaluating a chip capacitance value using a differential evaluation method. Here, C1 is the side where the number of parallel connections of the capacitive elements is large (the measured value is large), and C2 is the side where there are fewer parallel connections (measurement chain wheel), T1 and T2 are the measurement terminals that draw out C1, and T2
and T3 are the measurement terminals from which C2 is drawn out (T2 is C
1 and C2).
しかしながら、従来の評価方法によれば、評価用配線パ
ターンＡ３ ＋’ Ａ４が何れもチップ２の端部までで
終っているので、測定対象とする素子単体く例えば容量
または抵抗など）の並列接続数や素子単体に条件の異な
る形状などの水準を設ける場合には、この水準数は半導
体チップ２の面積から制限を受けるようになになる。従
って、測定精度を向上させたり、より多くの評価を行う
ことが難しいという欠点がある。However, according to the conventional evaluation method, the evaluation wiring patterns A3 +' A4 all end at the end of the chip 2, so the number of parallel connections of individual elements to be measured (for example, capacitance or resistance) is limited. When providing levels such as shapes with different conditions for each element, the number of levels is limited by the area of the semiconductor chip 2. Therefore, there is a drawback that it is difficult to improve measurement accuracy or perform more evaluations.
本発明の目的は、上記の問題点に鑑み、半導体チップ特
性の測定精度を向上させると共に、より多くの評価を行
うことのできるウェハー上における半導体チップの評価
方法を提供することである。SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for evaluating semiconductor chips on a wafer, which improves the measurement accuracy of semiconductor chip characteristics and allows more evaluations to be performed.
本発明によれば、ウェハ上におけるチップの評価方法は
、半導体チップをＸ方向及びＹ方向に繰り返し配置し隣
接するすべてのチップの測定端子間を共通に配線接続す
るウェハーを準備し、前記半導体チップ内の評価すべき
素子単体の並列接続数を前記ウェハーの全面にまで拡大
して差分評価することを含んで構成される。According to the present invention, a method for evaluating chips on a wafer includes preparing a wafer in which semiconductor chips are repeatedly arranged in the X direction and the Y direction and connecting the measurement terminals of all adjacent chips with a common wiring, and The method includes expanding the number of parallel connections of individual elements to be evaluated to cover the entire surface of the wafer and performing differential evaluation.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図および第２図はそれぞれ本発明を容量値の評価に
実施した場合の一実施例を示す半導体ウェハー上の差分
評価用配線パターン図およびそのチップ面の拡大図であ
る。ここで、従来と同じくＣ１は容量素子単体の並列接
続数が多い側く測定値大）で、Ｃ２は容量素子単体の並
列接続数の少ない側（測定鎖車）を示しており、またＴ
１とＴ２はＣ１を引き出した測定用端子、Ｔ２とＴ３は
Ｃ２を引き出した測定端子をそれぞれ示している。（Ｔ
２はＣ１及びＣ２の共通引き出し端子である〉。FIG. 1 and FIG. 2 are a diagram of a wiring pattern for differential evaluation on a semiconductor wafer and an enlarged view of the chip surface, respectively, showing an example in which the present invention is applied to evaluate a capacitance value. Here, as in the past, C1 indicates the side where the number of parallel connections of single capacitive elements is large (the measured value is large), C2 indicates the side where the number of parallel connections of single capacitive elements is small (measurement chain wheel), and T
1 and T2 indicate measurement terminals from which C1 is drawn, and T2 and T3 indicate measurement terminals from which C2 is drawn. (T
2 is a common lead-out terminal for C1 and C2.
本実施例によれば、評価用配線パターンＡ１゜Ａ２は隣
接する半導体チップ２の測定端子間をチップ端パターン
ａｌ 、Ｃ２、Ｃ３、Ｃ４で示すように共通接続してお
り、スルー・ホールＢで相互に接続される。このような
評価用配線バターＡ、、Ａ２を用いると、一つの半導体
チップ２の測定端子Ｔ、−Ｔ２間及びＴ２−Ｔ３間の測
定値は、素子単体の並列接続数がウェハー上の半導体チ
ップ数倍されたものとして得ることができる。According to this embodiment, the evaluation wiring patterns A1 and A2 commonly connect the measurement terminals of adjacent semiconductor chips 2 as shown by chip end patterns al, C2, C3, and C4, and the through holes B interconnected. When such evaluation wiring patterns A, A2 are used, the measured values between the measurement terminals T, -T2 and T2-T3 of one semiconductor chip 2 are as follows: It can be obtained multiple times.
従って、製造方法や測定方法を変更すること無く並列接
続数の増加を行うことができ、差分評価における測定精
度を向上せしめることができる。また、ウェハー上にお
ける並列接続数の増加を見越して一つの半導体チップ内
の並列接続数を減らすこともでき、この減らした分を素
子単体に条件の異なる形状などの水準を設ける場合の水
準数にあてることもできるので、条件の異なる水準を容
易に増やすことが可能となる。Therefore, the number of parallel connections can be increased without changing the manufacturing method or measurement method, and the measurement accuracy in differential evaluation can be improved. In addition, in anticipation of an increase in the number of parallel connections on a wafer, it is possible to reduce the number of parallel connections within one semiconductor chip, and this reduction can be used to increase the number of levels when providing levels such as shapes with different conditions on a single element. Since it is also possible to apply different conditions, it is possible to easily increase the number of levels with different conditions.
以上は容量測定パターンについて説明したが、これに限
られることなく抵抗値及び伝播遅延時間の評価法として
実施することも可能である。Although the capacitance measurement pattern has been described above, the present invention is not limited to this, and can also be implemented as a method for evaluating resistance values and propagation delay times.
以上説明したように、本発明によれば、ウェハー上の評
価用配線パターンを変更するだけで素子単体の並列接続
数を実質的に増加させることができ、差分評価法による
測定精度をその分だけ向上せしめることができる他、チ
ップ内の素子単体の並列接続数を少なく設定して条件の
差による水準数の増加をはかることもできるので、従来
法に対しより多くの種類の評価を実施することが可能で
ある。As explained above, according to the present invention, the number of parallel connections of individual elements can be substantially increased simply by changing the evaluation wiring pattern on the wafer, and the measurement accuracy by the differential evaluation method can be increased accordingly. In addition, it is possible to increase the number of levels due to differences in conditions by setting the number of parallel connections of individual elements in the chip to a small number, so it is possible to conduct more types of evaluation than conventional methods. is possible.
第１図および第２図はそれぞれ本発明を容量値の評価に
実施した場合の一実施例を示す半導体ウェハー上の差分
評価用配線パターン図およびそのチップ面の拡大図、第
３図および第４図はそれぞれ差分評価法を用いた従来の
チップ容量値の評価方法を示す半導体ウェハー上の評価
用配線バターン図およびそのチップ面の拡大図である。
１・・・半導体ウェハー、２・・・半導体チップ、Ａｌ
Ａ２・・・評価用配線パターン、Ｂ・・・スルー・ホー
ル、ａ １．ａ２ 、ａ３ 、ａ４・・・評価用配線の
チ・ンブ端パターン、Ｔｌ 、Ｔ２ 、Ｔ３・・・測定
用端子。FIGS. 1 and 2 are a diagram of a wiring pattern for differential evaluation on a semiconductor wafer and an enlarged view of its chip surface, respectively, showing one embodiment of the present invention for evaluating capacitance values, and FIGS. The figures are a diagram of a wiring pattern for evaluation on a semiconductor wafer and an enlarged view of the chip surface, respectively, showing a conventional method for evaluating chip capacitance values using a differential evaluation method. 1... Semiconductor wafer, 2... Semiconductor chip, Al
A2...Evaluation wiring pattern, B...Through hole, a1. a2, a3, a4... Chin end pattern of wiring for evaluation, Tl, T2, T3... terminal for measurement.
Claims (1)
するすべてのチップの測定端子間を共通に配線接続する
ウェハーを準備し、前記半導体チップ内の評価すべき素
子単体の並列接続数を前記ウェハーの全面にまで拡大し
て差分評価することを特徴とするウェハー上における半
導体チップの評価方法。A wafer is prepared in which semiconductor chips are repeatedly arranged in the X and Y directions and the measurement terminals of all adjacent chips are commonly connected by wiring, and the number of parallel connections of individual elements to be evaluated in the semiconductor chip is calculated by calculating the number of parallel connections of the individual elements to be evaluated in the semiconductor chip. A method for evaluating semiconductor chips on a wafer, which is characterized by performing differential evaluation by expanding to the entire surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63152809A JPH023945A (en) | 1988-06-20 | 1988-06-20 | Estimation method of semiconductor chip on wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63152809A JPH023945A (en) | 1988-06-20 | 1988-06-20 | Estimation method of semiconductor chip on wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH023945A true JPH023945A (en) | 1990-01-09 |
Family
ID=15548629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63152809A Pending JPH023945A (en) | 1988-06-20 | 1988-06-20 | Estimation method of semiconductor chip on wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH023945A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102175922A (en) * | 2011-01-24 | 2011-09-07 | 重庆大学 | Phasor measurement unit (PMU) measurement data-based power line parameter identification and estimation method |
-
1988
- 1988-06-20 JP JP63152809A patent/JPH023945A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102175922A (en) * | 2011-01-24 | 2011-09-07 | 重庆大学 | Phasor measurement unit (PMU) measurement data-based power line parameter identification and estimation method |
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