JPH0235795A - Board for mounting electronic element - Google Patents
Board for mounting electronic elementInfo
- Publication number
- JPH0235795A JPH0235795A JP18580588A JP18580588A JPH0235795A JP H0235795 A JPH0235795 A JP H0235795A JP 18580588 A JP18580588 A JP 18580588A JP 18580588 A JP18580588 A JP 18580588A JP H0235795 A JPH0235795 A JP H0235795A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- solder
- board
- holes
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 description 27
- 230000002093 peripheral effect Effects 0.000 description 8
- 238000007789 sealing Methods 0.000 description 6
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 241000282472 Canis lupus familiaris Species 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3468—Applying molten solder
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
本発明は、ピングリッドアレイなどの電子素子パッケー
ジに用いられる電子素子実装用基板に関するものである
。The present invention relates to an electronic element mounting substrate used in an electronic element package such as a pin grid array.
ビングリッドアレイなどICチップ等の電子素子7のパ
ッケージは例えば第3図に示すように形成されている。
すなわち、ムfllllt積層板などの電気絶縁性を有
する基板1の上面の中央にキャビティ用凹所8を形成す
ると共に基板1の上面にキャビティ用凹所8を中心とし
た放射状に回路を形成し、基板1に形成したスルーホー
ル2,2・・・に各回路と電気的に接続されたスルーホ
ールメツキを施し、スルーホール2に端子ビン9の基部
を挿入して端子ビン9を基板1の下面に突出させ、そし
てキャビティ用凹所8に電子素子7を実装すると共に電
子素子7と各回路とをボンディングすることによって、
基板1の上面に形成したこの回路を介して電子素子7を
各端子ビン9に電気的に接続させるようにして作成され
る。さらに基板1の上面に封止樹脂10を注入すると共
にリッド11を被せることに上って、パッケージとして
仕上げられるものである。
そして、例えば電子索子7の実装密度が高くなると回路
の本数は基板1の上面だけでは足らなくなって、基板1
の下面にも回路を形成する必要が生じる。このときには
tlIJ3図のようにスルーホール2として端子ビン9
を取り付けるものだけでなく、基板1の上下の回路を接
続するスルーホール2aも形成する必要があり、このス
ルーホール2aの内周に形成するスルーホール/ツキを
介して上下の回路の接続がなされる。しかしこのスルー
ホール2aは基板1の上下に貫通しているために、基板
1の上面に封止樹脂10を注入する際に第3図のように
このスルーホール2aから封止用BW10が漏れてしま
うことになる。
そこで、基板1の下部を半田浴に浸漬してスルーホール
2内に端子ビン9を半田付けする際に、貫通するスルー
ホール2a内にも半田を流入させて半田でこのスルーホ
ール2a内を充填し、封止111(IIWloがこのス
ルーホール2aから漏れることを防止するようにしてい
る。A package of an electronic element 7 such as an IC chip such as a bin grid array is formed as shown in FIG. 3, for example. That is, a cavity recess 8 is formed in the center of the upper surface of a substrate 1 having electrical insulation properties such as a multilayer laminate, and circuits are formed radially around the cavity recess 8 on the upper surface of the substrate 1. Through-hole plating is applied to the through-holes 2, 2... formed on the board 1 to electrically connect each circuit, and the base of the terminal pin 9 is inserted into the through-hole 2, and the terminal pin 9 is connected to the bottom surface of the board 1. By projecting the electronic element 7 into the cavity recess 8 and bonding the electronic element 7 and each circuit,
The electronic device 7 is electrically connected to each terminal pin 9 through this circuit formed on the upper surface of the substrate 1. Furthermore, a sealing resin 10 is injected onto the top surface of the substrate 1 and a lid 11 is placed on the top surface of the substrate 1 to complete the package. For example, when the mounting density of the electronic cables 7 increases, the number of circuits on the top surface of the board 1 is not enough, and
It becomes necessary to form a circuit also on the bottom surface of the . At this time, as shown in the tlIJ3 diagram, the terminal pin 9 is used as the through hole 2.
It is necessary to form not only a through hole 2a to connect the upper and lower circuits of the board 1, but also a through hole 2a to connect the upper and lower circuits of the board 1. Ru. However, since this through hole 2a penetrates the top and bottom of the substrate 1, when the sealing resin 10 is injected onto the top surface of the substrate 1, the sealing BW 10 leaks from the through hole 2a as shown in FIG. It will end up being put away. Therefore, when the lower part of the board 1 is immersed in a solder bath and the terminal pin 9 is soldered inside the through hole 2, the solder is also flowed into the through hole 2a passing through it, and the inside of this through hole 2a is filled with solder. However, sealing 111 (IIWlo) is prevented from leaking from this through hole 2a.
【発明が解決しようとする課題1
しかしながら、スルーホール2a内に半田が流入しなか
ったり、あるいは流入してら基板1を半田浴から引き上
げるとスルーホール2a内の半田が流れ落ちたりするこ
とが多く、スルーホール2a内を半田で確実に埋めるこ
とができず、このスルーホール2aから封止0)脂10
が漏れることを完全に防止することはでさないものであ
りな。
本発明は上記の点に鑑みて為されたものであり、貫通す
るスルーホールを半田によって確実に埋めることができ
る電子素子実装用基板を提供することを目的とするもの
である。
【9題を解決するための手段】
本発明は、基板1に形成したスルーホール2aの周縁に
おいて基板1の下面にスルーホールランド3を設けると
共にスルーホールランド3の箇所を除いて基板1の下面
にソルダーレジスト4を施して形成される電子素子実装
用基板において、スルーホール2aの直径を0 、6
mta以下に、スルーホール2aの開口縁からスルーホ
ールランド3の外周縁までの幅寸法を0 、2 mm以
上に、スルーホールランド3の外周縁とゾルグーレノス
ト4の縁との間の間隙の寸法を0.2 mm+以上にそ
れぞれ設定して成ることを特徴とするものである。Problem to be Solved by the Invention 1 However, the solder in the through holes 2a often does not flow into the through holes 2a, or when the solder flows into the through holes 2a and the board 1 is pulled up from the solder bath, the solder in the through holes 2a flows down. The inside of the hole 2a cannot be reliably filled with solder, and the through hole 2a is sealed 0) Grease 10
It is not possible to completely prevent leakage. The present invention has been made in view of the above points, and it is an object of the present invention to provide a substrate for mounting an electronic device, in which through-holes can be reliably filled with solder. [Means for Solving Problem 9] The present invention provides a through-hole land 3 on the lower surface of the substrate 1 at the periphery of the through-hole 2a formed in the substrate 1, and also provides a through-hole land 3 on the lower surface of the substrate 1 excluding the through-hole land 3. In an electronic device mounting board formed by applying solder resist 4 to
mta or less, the width from the opening edge of the through-hole 2a to the outer periphery of the through-hole land 3 is 0.2 mm or more, and the gap between the outer periphery of the through-hole land 3 and the edge of the solgulenost 4 is set to 2 mm or less. It is characterized by being set to 0.2 mm+ or more.
本発明にあっては、スルーホール2aの直径を0.60
慴以下に、スルーホール2aの開口縁からスルーホール
ランド3の外周縁までの幅寸法を0゜2mm以上に、ス
ルーホールランド3の外周縁とゾルグーレノスト4の縁
との間の間隙の寸法を0゜21以上にそれぞれ設定する
ことによって、基板1の下部を半田浴に浸漬する際にス
ルーホール2a内に半田を良好に流入させることができ
ると共に、基板1を半田浴から引き上げた後にスルーホ
ール2aから半田が流れ落ちることを防止することがで
きる。In the present invention, the diameter of the through hole 2a is set to 0.60.
Below, the width from the opening edge of the through-hole 2a to the outer periphery of the through-hole land 3 should be 0.2 mm or more, and the gap between the outer periphery of the through-hole land 3 and the edge of the solgulenost 4 should be 0. By setting these values to 21° or more, it is possible to make the solder flow well into the through-holes 2a when the lower part of the board 1 is immersed in the solder bath, and also to allow the solder to flow into the through-holes 2a after the board 1 is lifted out of the solder bath. This can prevent solder from flowing down.
以下本発明の詳細な説明する2
基板1は樹脂積層板などプラスチック材料で形成される
ものであり、上面の中央部にキャビティ用凹所8を形成
すると共に上面と下面にそれぞれ放射状に回路が形成し
である。また基[1には多数のスルーホール2が形成し
てあり、各スルーホール2の内周には回路と電気的に接
続されたスルーホールメツキが施しである。スルーホー
ル2のうち一部のものは端子ビン9を取り付けるための
ものであり、他゛のスルーホール2aは基板1の上下の
回路を接続するためのものである。このスルーホール2
aの基板1の下面で開口する周縁部には第2図に示すよ
うに円形のスルーホールランド3が形成してあり、スル
ーホールランド3の周縁の一部から基板の1の下面の回
路が導出されるようにしである。さらに、基板1の下面
には半田が付着するのを防ぐ必要のある部分、すなわち
スルーホールランド3以外の箇所においてツルグーレジ
スト4が印刷などで塗布して施しである。
このように形成される基板1にあって、スルーホール2
a以外のスルーホール2に端子ビン9の頭部を差し込ん
で基板1の下面から端子ビン9を突出させ、この状態で
基板1の下部を半田浴に浸漬して、スルーホール2と端
子ピンクとを牛田付けするものである。そしてキャビテ
ィ用凹所8にICチップなどの電子素子7を実装すると
共に・電子素子7と基板1の上面の回路とをボンディン
グすることによって、基板1の上面に形成したこの回路
を介して電子素子7を各端子ビン9に電気的に接続させ
るらのであり、さらに基板1の上面に封止樹脂10を注
入すると共にリッド11を被せることによって、パフケ
ーノとして仕上げられるものである。
上記のように基板1の下部を半田浴に浸漬して端子ビン
9を半田付けする際に、端子ビン9が差し込まれておら
ず基板1に貫通して形成されて−するスルーホール2a
にその下端の開口から半田を流入させ、第1図に示すよ
うにこのスルーホール2a内に半田12を充填させるも
のであり、このようにスルーホール2aを半田12で埋
めてこの貫通するスルーホール2aから封止樹脂10が
漏れ出ることを防止するものである。ここで、スル−ホ
ール2a内に半田を良好に流入させると共に基板1を半
田浴から引き上げた後にスルーホール2aから半田が流
れ落ちることを防止するために、本発明ではスルーホー
ル2aの直径11を0 、6 ml以下に、スルーホー
ル2aの開口縁からスルーホールランド3の外周縁まで
の幅寸法12を0 、2 I*a+以上に、スルーホー
ルランド3の外周縁とソルダーレノスト4の縁との間の
間隙の寸法l、を0.21以上にそれぞれ設定している
。すなわち、スルーホール2aの直径11が0 、6
armよりも大軽いと、基板1の下部を半田浴に浸漬し
た際にスルーホール2a内に半田が流入しても、基板1
を引き上げるとスルーホール2a内に半田は保持されず
落下してしまうが、0.61以下に設定することによっ
て毛細管現象等の作用でスルーホール2a内に半田を充
填させた状態に保持することができるのである。勿論1
1が小さすぎるとスルーホール2a内に半田が入ること
ができなくなるので、この限度よりはスルーホール2a
の直径は大きく設定されるのはいうまでもない。またス
ルーホール2aの開口縁からスルーホールランド3の外
周縁までの幅寸法12を0.2 mm以上に設定するこ
とによって、スルーホールランド3に対する半田の濡れ
でスルーホール2a内への半田の流入が促進され、基板
1の下部を半田浴に浸漬した際にスルーホール2a内に
半田を確実に充填させることができる。0゜21以下で
あればこのような効果を期待することはできない。さら
にスルーホールランド3の外周縁とツルグーレジスト4
の縁との間の間隙の寸法l、を0 、2 a++a以上
に設定することによって、スルーホール2aからのソル
ダーレジスト4の距離が長くなってスルーホール2aに
半田が流入することをソルダーレジスト4が阻害するよ
うに作用することを防止すると共に、ソルダーレジスト
4の印刷の際に位置ずれでスルーホールランド3の一部
がツルグーレジスト4で覆われてしまうことを防止し、
スルーホールランド3の実質的な12の寸法が0 、2
11101以下になることを防ぐことができる。
0 、2 ma+以下であればこのような効果を期待す
ることはできない。
犬に本発明を実施例によって例証する。
1.2、 1〜3
厚み1.61の両面銅箔張りプラス布エポキシ樹脂積層
板を基板1として用い、この基板1に50個のスルーホ
ール2aをドリル加工で設け、基板1の下面にt14’
Mのエツチング加工で円形のスルーホールランド3を形
成すると共にソルダーレジスト4(7サヒ化研社製CC
R506G)を20μの厚みに印刷して施した。ここで
、スルーホール2aの直径!3、スルーホール2aの開
口縁からスルーホールランド3の外周縁までの幅寸法1
2、スルーホールランド3の外周縁とソルダーレジスト
4の縁との間の間隙の寸法l、をそれぞれ第1表に示す
ように設定した。
そしてこの基板1の下部を280℃の半田浴に4秒間浸
漬して引き上げる試験をおこない、スルーホール2aに
半田が充填されているか否かの半田充填性の試験をおこ
なった。結果を第1表に示す。第1表において分母に観
察したスルーホール2aの個数を、分子に半田が充填さ
れていないスルーホール24の個数を示す。
#S1表にみられるように、スルーホール2aの直径1
1を0 、6 ff1m以下に、スルーホール2aの開
口縁からスルーホールランド3の外周縁までの幅寸法1
2を0 、216m以上に、スルーホールランド3の外
周縁とソルダーレジスト4の縁との開の間隙の寸法ムを
0.2−以上にそれぞれ設定することによってはじめて
、スルーホール2aを半田で確実に埋めることができる
ことが確認される。The present invention will be described in detail below.2 The substrate 1 is made of a plastic material such as a resin laminate, and has a cavity recess 8 formed in the center of the upper surface and circuits radially formed on the upper and lower surfaces respectively. It is. In addition, a large number of through holes 2 are formed in the base 1, and the inner periphery of each through hole 2 is plated with through holes that are electrically connected to a circuit. Some of the through holes 2 are for attaching terminal pins 9, and other through holes 2a are for connecting circuits on the upper and lower sides of the board 1. This through hole 2
As shown in FIG. 2, a circular through-hole land 3 is formed at the peripheral edge opening on the lower surface of the substrate 1 in a, and the circuit on the lower surface of the substrate 1 is connected from a part of the peripheral edge of the through-hole land 3. This is how it is derived. Further, on the lower surface of the substrate 1, a slug resist 4 is applied by printing or the like in areas where it is necessary to prevent adhesion of solder, that is, areas other than the through-hole lands 3. In the substrate 1 formed in this way, the through holes 2
Insert the head of the terminal pin 9 into the through hole 2 other than a to make the terminal pin 9 protrude from the bottom surface of the board 1. In this state, dip the lower part of the board 1 in a solder bath to connect the through hole 2 and the terminal pink. This is what Ushida attaches to. Then, by mounting an electronic element 7 such as an IC chip in the cavity recess 8 and bonding the electronic element 7 and the circuit on the upper surface of the substrate 1, the electronic element 7 is connected to the circuit formed on the upper surface of the substrate 1. 7 are electrically connected to each terminal pin 9, and further, a sealing resin 10 is injected onto the upper surface of the substrate 1 and a lid 11 is placed over the top surface of the substrate 1, thereby completing the structure as a puff case. When the lower part of the board 1 is immersed in a solder bath and the terminal pin 9 is soldered as described above, the terminal pin 9 is not inserted and the through hole 2a is formed to penetrate through the board 1.
The through hole 2a is filled with solder 12 by flowing the solder through the opening at the lower end of the through hole 2a as shown in FIG. This prevents the sealing resin 10 from leaking out from 2a. Here, in order to allow the solder to flow well into the through-hole 2a and to prevent the solder from flowing down from the through-hole 2a after the board 1 is pulled up from the solder bath, in the present invention, the diameter 11 of the through-hole 2a is set to 0. , 6 ml or less, and the width dimension 12 from the opening edge of the through hole 2a to the outer periphery of the through hole land 3 is 0. The dimension l of the gap between the two is set to 0.21 or more. That is, the diameter 11 of the through hole 2a is 0,6
If it is much lighter than the arm, even if solder flows into the through hole 2a when the lower part of the board 1 is immersed in a solder bath, the board 1
If the solder is pulled up, the solder will not be held in the through hole 2a and will fall, but by setting it to 0.61 or less, the through hole 2a can be kept filled with solder due to capillary action, etc. It can be done. Of course 1
If 1 is too small, solder will not be able to enter the through hole 2a, so the through hole 2a
Needless to say, the diameter is set large. In addition, by setting the width dimension 12 from the opening edge of the through-hole 2a to the outer peripheral edge of the through-hole land 3 to 0.2 mm or more, solder can flow into the through-hole 2a by wetting the through-hole land 3 with the solder. is promoted, and when the lower part of the substrate 1 is immersed in a solder bath, the through holes 2a can be reliably filled with solder. If the angle is less than 0°21, such an effect cannot be expected. Furthermore, the outer periphery of the through-hole land 3 and the turret resist 4
By setting the dimension l of the gap between the edge of the solder resist 4 and the edge of the solder resist 4 to 0,2 a++a or more, the distance of the solder resist 4 from the through hole 2a becomes longer and the solder flows into the through hole 2a. This prevents the through-hole land 3 from being partially covered by the solder resist 4 due to misalignment during printing of the solder resist 4.
The substantial 12 dimensions of the through hole land 3 are 0, 2
It is possible to prevent the value from becoming 11101 or less. If it is less than 0.2 ma+, such an effect cannot be expected. The invention is illustrated by way of example in dogs. 1.2, 1-3 A double-sided copper foil-covered plus cloth epoxy resin laminate with a thickness of 1.61 mm is used as the substrate 1, and 50 through holes 2a are drilled on the substrate 1, and t14 holes are formed on the bottom surface of the substrate 1. '
A circular through-hole land 3 is formed by etching M, and a solder resist 4 (7 CC made by Sahi Kaken Co., Ltd.) is formed.
R506G) was printed to a thickness of 20μ. Here, the diameter of through hole 2a! 3. Width dimension 1 from the opening edge of through hole 2a to the outer peripheral edge of through hole land 3
2. The dimension l of the gap between the outer peripheral edge of the through-hole land 3 and the edge of the solder resist 4 was set as shown in Table 1. Then, a test was carried out by immersing the lower part of the substrate 1 in a solder bath at 280° C. for 4 seconds and pulling it up, thereby testing the solder filling property to determine whether the through holes 2a were filled with solder. The results are shown in Table 1. In Table 1, the denominator is the number of through holes 2a observed, and the numerator is the number of through holes 24 not filled with solder. #As seen in table S1, the diameter of through hole 2a is 1
1 to 0, 6 ff1m or less, width dimension 1 from the opening edge of through hole 2a to the outer peripheral edge of through hole land 3
2 to 0, 216 m or more, and the gap between the outer peripheral edge of the through-hole land 3 and the edge of the solder resist 4 to 0.2- or more, the through-hole 2a can be securely filled with solder. It is confirmed that it can be filled in.
上述のように本発明にあっては、スルーホールの直径を
0.6 a11以下に、スルーホールの開口縁からスル
ーホールランドの外周縁までの幅寸法を0.2ω信以上
に、スルーホールランドの外周縁とソルダーレジストの
緑との間の間隙の寸法を0゜21以上にそれぞれ設定す
ることによって、基板の下部を半田浴に浸漬する際にス
ルーホーB、内に半田を良好に流入させることができる
と共に、基板を半田浴から引き上げた後にスルーホール
から半田が流れ落ちることを防止することがて−、スル
ーホールを半田で確実に埋めることができるものである
。As described above, in the present invention, the diameter of the through hole is 0.6 a11 or less, the width dimension from the opening edge of the through hole to the outer peripheral edge of the through hole land is 0.2 ω or more, and the through hole land is By setting the dimensions of the gap between the outer periphery of the board and the green part of the solder resist to 0°21 or more, solder can flow well into the through-hole B when the lower part of the board is immersed in the solder bath. In addition, by preventing the solder from flowing down from the through holes after the board is lifted from the solder bath, the through holes can be reliably filled with solder.
【図面の簡単な説明】
第1図は本発明の一実施例の断面図、第2図は同上の一
部を示す拡大図、第3図は従来例の断面図である。
1は基板、2aはスルーホール、3はスル・−ホールラ
ンド、4はソルダーレジストである。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is an enlarged view of a part of the same, and FIG. 3 is a sectional view of a conventional example. 1 is a substrate, 2a is a through hole, 3 is a through-hole land, and 4 is a solder resist.
Claims (1)
の下面にスルーホールランドを設けると共にスルーホー
ルランドの箇所を除いて基板の下面にソルダーレジスト
を施して形成される電子素子実装用基板において、スル
ーホールの直径を0.6mm以下に、スルーホールの開
口縁からスルーホールランドの外周縁までの幅寸法を0
.2mm以上に、スルーホールランドの外周縁とソルダ
ーレジストの縁との間の間隙の寸法を0.2mm以上に
それぞれ設定して成ることを特徴とする電子素子実装用
基板。(1) A through-hole land is provided on the bottom surface of the board at the periphery of a through-hole formed in the board, and a solder resist is applied to the bottom surface of the board except for the through-hole land. The diameter of the hole should be 0.6 mm or less, and the width from the opening edge of the through hole to the outer periphery of the through hole land should be 0.
.. A board for mounting an electronic device, characterized in that the dimensions of the gap between the outer periphery of the through-hole land and the edge of the solder resist are set to 2 mm or more, and the dimensions of the gap between the outer periphery of the through-hole land and the edge of the solder resist are set to 0.2 mm or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63185805A JPH079954B2 (en) | 1988-07-26 | 1988-07-26 | Electronic element mounting substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63185805A JPH079954B2 (en) | 1988-07-26 | 1988-07-26 | Electronic element mounting substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0235795A true JPH0235795A (en) | 1990-02-06 |
JPH079954B2 JPH079954B2 (en) | 1995-02-01 |
Family
ID=16177198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63185805A Expired - Fee Related JPH079954B2 (en) | 1988-07-26 | 1988-07-26 | Electronic element mounting substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH079954B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008277325A (en) * | 2007-04-25 | 2008-11-13 | Canon Inc | Semiconductor device, and manufacturing method of semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62221136A (en) * | 1986-03-24 | 1987-09-29 | Hitachi Chem Co Ltd | Semiconductor-element mounting wiring board |
-
1988
- 1988-07-26 JP JP63185805A patent/JPH079954B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62221136A (en) * | 1986-03-24 | 1987-09-29 | Hitachi Chem Co Ltd | Semiconductor-element mounting wiring board |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008277325A (en) * | 2007-04-25 | 2008-11-13 | Canon Inc | Semiconductor device, and manufacturing method of semiconductor device |
US8129273B2 (en) | 2007-04-25 | 2012-03-06 | Canon Kabushiki Kaisha | Semiconductor device and method for producing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH079954B2 (en) | 1995-02-01 |
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LAPS | Cancellation because of no payment of annual fees |