JPH023306B2 - - Google Patents
Info
- Publication number
- JPH023306B2 JPH023306B2 JP57012832A JP1283282A JPH023306B2 JP H023306 B2 JPH023306 B2 JP H023306B2 JP 57012832 A JP57012832 A JP 57012832A JP 1283282 A JP1283282 A JP 1283282A JP H023306 B2 JPH023306 B2 JP H023306B2
- Authority
- JP
- Japan
- Prior art keywords
- material layer
- oxidation
- oxide film
- mask
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000463 material Substances 0.000 claims description 64
- 230000003647 oxidation Effects 0.000 claims description 49
- 238000007254 oxidation reaction Methods 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 26
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 26
- 238000002955 isolation Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 2
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 239000012808 vapor phase Substances 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000005755 formation reaction Methods 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 241000293849 Cordylanthus Species 0.000 description 4
- -1 boron ions Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000992 sputter etching Methods 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特に絶
縁物による素子分離技術を改良した相補型MOS
半導体装置の製造方法に係る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a complementary MOS that improves element isolation technology using an insulator.
It relates to a method of manufacturing a semiconductor device.
半導体集積回路における分離技術に関しては高
集積化、製造プロセスの容易化を図るものとして
一般に分離領域を選択酸化技術によつて形成した
酸化膜を使用するものが知られている。この方式
によれば、能動領域の周囲が酸化膜によつて取り
囲まれているため、ベース拡散等においてセルフ
アラインメントが可能で従来のようなマスク合せ
のための不要な部分が省略でき高集積化が可能と
なり、また側面が深い酸化膜により構成されたこ
とによつて接合容量は桁違いに減少する。しかし
ながら、この方式ではシリコン基板中に熱酸化膜
を選択的に埋没させる構造のため、シリコン基板
に大きな歪が生じ、素子の電気的特性を劣化さ
せ、耐酸化性マスクの構造、構成、膜厚及び選択
酸化条件、時にはシリコン基板そのものの材料自
身の選択に著しい制限を与えている。これは、例
えば文献IEDM“High Pressure Oxidation for
Isolation of High Speed Bipolar Devices”
1979年PP340〜343に記載されている。
Regarding isolation technology in semiconductor integrated circuits, it is generally known to use an oxide film formed by selective oxidation technology as an isolation region in order to achieve high integration and ease of manufacturing process. According to this method, since the active region is surrounded by an oxide film, self-alignment is possible in base diffusion, etc., and unnecessary parts for mask alignment can be omitted, allowing for high integration. In addition, since the side surfaces are made of a deep oxide film, the junction capacitance is reduced by an order of magnitude. However, since this method has a structure in which the thermal oxide film is selectively buried in the silicon substrate, large strains occur in the silicon substrate, deteriorating the electrical characteristics of the device, and reducing the structure, composition, and film thickness of the oxidation-resistant mask. Also, selective oxidation conditions, and sometimes the selection of the material of the silicon substrate itself, are severely restricted. This can be seen, for example, in the literature IEDM “High Pressure Oxidation for
Isolation of High Speed Bipolar Devices”
Described in 1979 PP340-343.
また、窒化シリコン膜をマスクとして熱酸化を
行なうと、“ホワイトリボン”と称するシリコン
ナイトライド膜が窒化シリコン膜の下のSi基板中
に形成され、これが素子の耐圧不良の原因とな
る。更に、耐酸化性マスクとして窒化シリコン膜
と酸化膜からなる２重層のものを使用するため、
1μmに近いバーズビークが窒化シリコン膜下に喰
い込み、その結果2μm以下の素子間分離膜の形成
が困難であつた。これは、例えば文献Birds
Beak Configuration and Elimination of Gate
Oxide Thinnig Produced during Selection
Oxidation”1980年P216〜222J，Ｅ，Ｃ，Ｓに記
載されている。 Furthermore, when thermal oxidation is performed using a silicon nitride film as a mask, a silicon nitride film called a "white ribbon" is formed in the Si substrate under the silicon nitride film, which causes a breakdown voltage failure of the device. Furthermore, since a double layer consisting of a silicon nitride film and an oxide film is used as an oxidation-resistant mask,
Bird's beaks close to 1 μm dug into the silicon nitride film, and as a result, it was difficult to form an interelement isolation film of 2 μm or less. This is for example the literature Birds
Beak Configuration and Elimination of Gate
Oxide Thinnig Produced during Selection
Oxidation” 1980, P216-222J, E, C, S.
上記欠点を解消するために本出願人は半導体基
板上に被酸化性材料層を形成し、この材料層上に
直接窒化シリコンからなる耐酸化性マスクを選択
的に形成した後、該マスクを用いて材料層を選択
酸化し、ひきつづき、マスク除去、その下の残存
材料層の少なくとも一部除去を行なうことによつ
て、選択酸化時、半導体基板への熱影響による欠
陥発生を防止し、かつ同選択酸化時のバーズビー
クの発生を抑制すると共に材料層上へのオキシナ
イトライド膜の生成を防止でき、ひいては電気特
性が良好で、変換差の小さい微細素子に適した半
導体装置の製造方法を既に提案した。 In order to eliminate the above-mentioned drawbacks, the applicant formed an oxidizable material layer on a semiconductor substrate, selectively formed an oxidation-resistant mask made of silicon nitride directly on this material layer, and then used the mask. By selectively oxidizing the material layer, followed by removing the mask and removing at least a portion of the remaining material layer underneath, defects can be prevented from occurring due to thermal effects on the semiconductor substrate during selective oxidation, and the same can be achieved. We have already proposed a manufacturing method for semiconductor devices that can suppress the occurrence of bird's beaks during selective oxidation and prevent the formation of oxynitride films on material layers, which in turn has good electrical properties and is suitable for microscopic elements with small conversion differences. did.
しかしながら、窒化シリコンからなる耐酸化マ
スクの厚さにはウエーハのそり発生等による上限
があるため被酸化性材料を通してチヤネルストツ
パ用イオン注入を行う必要のある上記方法を相補
型MOS LSIの製造方法に適用する場合、注入イ
オンが窒化シリコンからなる耐酸化マスクをつき
ぬけて被酸化性材料にまで打ち込まれ、その後の
熱酸化中に基板にまで達し基板表面濃度が変化す
るという問題が発生する。 However, since there is an upper limit to the thickness of the oxidation-resistant mask made of silicon nitride due to wafer warpage, etc., the above method, which requires ion implantation for channel stopper through oxidizable material, is applied to the manufacturing method of complementary MOS LSI. In this case, a problem arises in that the implanted ions penetrate the oxidation-resistant mask made of silicon nitride and are implanted into the oxidizable material, reaching the substrate during subsequent thermal oxidation and changing the substrate surface concentration.
本発明は上記事情に鑑みなされたもので、既に
提案した方法と同様な効果を有すると共に、耐酸
化性材料層のパターンが存在する基板への不純物
の侵入、これによる基板表面濃度の変化を防止し
た相補型MOS半導体装置等の半導体装置の製造
方法を提供しようとするものである。
The present invention has been developed in view of the above circumstances, and has the same effect as the previously proposed method, and also prevents impurities from entering a substrate on which a pattern of an oxidation-resistant material layer exists and changes in the substrate surface concentration caused by this. The present invention aims to provide a method for manufacturing a semiconductor device such as a complementary MOS semiconductor device.
本発明は半導体基板上に被酸化性材料層を形成
する工程と、この材料層上に耐酸化性材料層と不
純物ドーピングマスク材料層からなる二層構造の
パターンを選択的に形成する工程と、このパター
ンをマスクとして半導体基板に不純物をイオン注
入する工程と、前記不純物ドープマスク材料層を
除去した後、耐酸化性材料層のパターンをマスク
として前記被酸化性材料層を少なくとも一部酸化
して酸化膜を形成する工程と、前記半導体基板が
露出するように前記耐酸化性材料層とその下の残
存被酸化性材料層を少なくとも一部除去する工程
とを具備したことを特徴とするものである。
The present invention includes a step of forming an oxidizable material layer on a semiconductor substrate, a step of selectively forming a two-layer structure pattern consisting of an oxidation-resistant material layer and an impurity doping mask material layer on this material layer, A step of ion-implanting impurities into the semiconductor substrate using this pattern as a mask, and after removing the impurity-doped mask material layer, oxidizing at least a portion of the oxidizable material layer using the pattern of the oxidation-resistant material layer as a mask. The method is characterized by comprising a step of forming an oxide film, and a step of removing at least a portion of the oxidation-resistant material layer and the remaining oxidizable material layer thereunder so that the semiconductor substrate is exposed. be.
本発明における被酸化性材料層は選択酸化によ
り素子間分離膜としての酸化膜を形成するために
利用される。かかる材料としては、例えば多結晶
シリコン並びにリン、砒素、ボロンなどの不純物
が高濃度ドープされた多結晶シリコン、或いはモ
リブデンシリサイド、タングステンシリサイド、
タンタルシリサイドなどの金属珪化物等を挙げる
ことができる。なお、材料層を半導体基板上に形
成するにあたつては、酸化膜を介して材料層を形
成してもよい。このように基板と材料層の間に酸
化膜を介在させることにより、特に材料層として
高濃度不純物ドープ多結晶シリコン層を用いた場
合、選択酸化時に該多結晶シリコン層中の不純物
が基板中に拡散するのを該酸化膜により阻止でき
る利点を有する。また、材料層として不純物ドー
プ多結晶シリコン層を用い、この残存多結晶シリ
コン層をエツチングするに際しても、前記酸化膜
が基板に対するエツチングストツパとして作用す
る。 The oxidizable material layer in the present invention is used to form an oxide film as an element isolation film by selective oxidation. Examples of such materials include polycrystalline silicon, polycrystalline silicon heavily doped with impurities such as phosphorus, arsenic, and boron, molybdenum silicide, tungsten silicide,
Examples include metal silicides such as tantalum silicide. Note that when forming the material layer on the semiconductor substrate, the material layer may be formed via an oxide film. By interposing the oxide film between the substrate and the material layer in this way, especially when a highly impurity-doped polycrystalline silicon layer is used as the material layer, impurities in the polycrystalline silicon layer can be absorbed into the substrate during selective oxidation. This oxide film has the advantage of preventing diffusion. Furthermore, when an impurity-doped polycrystalline silicon layer is used as the material layer and the remaining polycrystalline silicon layer is etched, the oxide film acts as an etching stopper for the substrate.
本発明においてはパターンの一部を構成する窒
化シリコンからなる耐酸化性材料層を被酸化性材
料層上に直接形成することを特長とし、かかる状
態において選択酸化を行なうことによつて、耐酸
化性マスク下に酸化膜が喰い込み、いわゆるバー
ズビークを著しく抑制できると共に、マスク下の
材料層表面の一部にオキシナイトライド膜が生成
されるのを防止できる。なお、オキシナイトライ
ド膜が生成されないことによる効果は以下の如く
である。即ち、選択酸化により材料層の露出部付
近に厚い酸化膜を形成し、マスクを除去した後、
残存材料層を除去するが、この除去にあたつては
形成すべき素子間分離膜がオーバーハング構造と
なるのを避けるために反応性スパツタイオンエツ
チングにより除去する。しかし、このエツチング
時に残存した帯状のオキシナイトライド膜がエツ
チングマスクとして作用し、厚い酸化膜に沿つて
材料層が残る。こうした状態で残つた被酸化性材
料層を熱酸化して酸化膜に変換すると、素子間分
離膜の面積が広くなる。つまり寸法変換差が大き
くなり、素子の微細化の妨げとなる。したがつ
て、選択酸化時に、耐酸化性材料層下の被酸化性
材料層表面の一部にオキシナイトライド膜が生じ
ないことは、素子の微細化の点から極めて有益で
ある。 The present invention is characterized in that an oxidation-resistant material layer made of silicon nitride that constitutes a part of the pattern is formed directly on the oxidizable material layer, and by performing selective oxidation in such a state, the oxidation-resistant material layer is formed directly on the oxidizable material layer. The oxide film digs under the mask, so-called bird's beak can be significantly suppressed, and the formation of an oxynitride film on a part of the surface of the material layer under the mask can be prevented. The effects of not producing an oxynitride film are as follows. That is, after forming a thick oxide film near the exposed part of the material layer by selective oxidation and removing the mask,
The remaining material layer is removed by reactive sputter ion etching to avoid forming an overhang structure in the element isolation film to be formed. However, the band-shaped oxynitride film remaining during this etching acts as an etching mask, and a material layer remains along the thick oxide film. When the oxidizable material layer remaining in this state is thermally oxidized and converted into an oxide film, the area of the element isolation film becomes larger. In other words, the difference in dimensional conversion becomes large, which hinders the miniaturization of elements. Therefore, during selective oxidation, it is extremely beneficial from the viewpoint of device miniaturization that an oxynitride film is not formed on a part of the surface of the oxidizable material layer under the oxidation-resistant material layer.
また、窒化シリコンからなる耐酸化性材料層上
にCVD SiO2からなる不純物ドーピングマスク材
料層を積層して二層構造のパターンを被酸化性材
料層に形成することによりチヤネルストツパ形成
用イオン注入時にマスクの下に半導体表面に誤つ
てチヤネルストツパが形成されることを防止でき
る。特に相補型MOS ICにおけるようにｐ―ウエ
ル領域上のチヤネルストツパ形成とｎ型基板上の
チヤネルストツパ形成を別々に行う必要のある構
造のものでは上述の耐酸化性材料のパターンのみ
を形成するための例えばゴム系レジストをそのま
ま使えずそのパターン形成後一たん除去し、改め
てチヤネルストツパ形成用のレジストマスクパタ
ーンを形成せねばならない。しかし、こうした方
法では１回目と２回目のパターン形成の合わせず
れにより耐酸化性材料のパターンに対してチヤネ
ルストツパを自己整合的に形成することは困難と
なる。これに対し、本発明のようにイオン注入マ
スクとして不純物ドープマスク材料層を耐酸化性
材料層上に被覆してパターンを形成することによ
り、チヤネルストツパを耐酸化性材料層のパター
ンに対して自己整合的に形成でき、その結果相補
型MOS ICの製造方法にまで用途を広げることが
できる。なお、チヤネルストツパ形成のイオン注
入を行つた後、選択酸化する前にCVD SiO2から
なる不純物ドープマスク材料層を除去しなければ
ならない。その理由は選択酸化後、耐酸化材料層
のパターンで覆われない領域ポリシリコン等の被
酸化性材料は二酸化シリコンに変化するので
CVD SiO2のみを選択的に除去することは不可能
なためである。 In addition, by stacking an impurity doping mask material layer made of CVD SiO 2 on an oxidation-resistant material layer made of silicon nitride to form a two-layer structure pattern on the oxidizable material layer, a mask can be used during ion implantation for channel stopper formation. It is possible to prevent a channel stopper from being erroneously formed on the semiconductor surface under the semiconductor surface. Particularly in complementary MOS ICs, where the channel stopper formation on the p-well region and the channel stopper formation on the n-type substrate need to be performed separately, for example, for forming only the pattern of the above-mentioned oxidation-resistant material. The rubber resist cannot be used as is, and after the pattern is formed, it must be removed and a resist mask pattern for forming the channel stopper must be formed again. However, in such a method, it is difficult to form a channel stopper in a self-aligned manner with respect to the pattern of the oxidation-resistant material due to misalignment between the first and second pattern formations. In contrast, as in the present invention, by coating an impurity-doped mask material layer as an ion implantation mask on an oxidation-resistant material layer to form a pattern, the channel stopper is self-aligned with the pattern of the oxidation-resistant material layer. As a result, the application can be expanded to include methods for manufacturing complementary MOS ICs. Note that after performing ion implantation to form a channel stopper, the impurity-doped mask material layer made of CVD SiO 2 must be removed before selective oxidation. The reason is that after selective oxidation, oxidizable materials such as polysilicon in areas not covered by the pattern of the oxidation-resistant material layer turn into silicon dioxide.
This is because it is impossible to selectively remove only CVD SiO 2 .
本発明における残存被酸化性材料層の除去手段
としては、酸化膜端部下がオーバーハング構造と
なるのを避けるために、基板に対して略垂直に残
存材料層をエツチングし得る反応性スパツタイオ
ンエツチング法、イオンビームエツチング法など
の異方法エツチング法を採用することが望まし
い。 As a means for removing the remaining oxidizable material layer in the present invention, in order to avoid an overhang structure under the edge of the oxide film, reactive sputtering ion is used which can etch the remaining material layer approximately perpendicularly to the substrate. It is desirable to employ a different etching method such as an etching method or an ion beam etching method.
実施例
〔〕 まず、ｎ型の単結晶シリコン基板１にボ
ロンをドーズ量8.5×1012／cm2の条件でイオン
注入し、1190℃で30時間活性化（ドライブイ
ン）して深さ約10μm、表面濃度約８×1015／
cm2のｐ―ウエル２を選択的に形成した。つづい
て、熱酸化処理を施して基板１及びｐ―ウエル
２上に厚さ1000Åの熱酸化膜３を成長させた
後、熱酸化膜３上に多結晶シリコンを気相成長
させ被酸化材料層としての厚さ4000Åの多結晶
シリコン層４を堆積した（第１図図示）。
Example [First, boron ions are implanted into an n-type single crystal silicon substrate 1 at a dose of 8.5×10 12 /cm 2 , and activated (drive-in) at 1190° C. for 30 hours to a depth of approximately 10 μm. , surface concentration approximately 8×10 15 /
A cm 2 p-well 2 was selectively formed. Next, a thermal oxide film 3 with a thickness of 1000 Å is grown on the substrate 1 and the p-well 2 by thermal oxidation treatment, and then polycrystalline silicon is grown in a vapor phase on the thermal oxide film 3 to form a layer of material to be oxidized. A polycrystalline silicon layer 4 with a thickness of 4000 Å was deposited (as shown in FIG. 1).
〔〕 次いで、多結晶シリコン層４上に直接厚
さ2000Åの窒化シリコン層及び厚さ5000Åの
SiO2層を気相成長法により順次堆積した後、
反応性スパツタイオンエツチングを用いたフオ
トエツチングプロセスによりパターニングして
基板１の素子領域予定部（ｐチヤネルMOSト
ランジスタ領域予定部）及びｐ―ウエル２の素
子領域予定部（ｎチヤネルMOSトランジスタ
領域予定部）に対応する多結晶シリコン層４上
部分に窒化シリコン層５1，５2，SiO2層６1，
６2からなる積層パターン７1，７2を夫々形成
した。つづいてｐチヤネルMOSトランジスタ
領域予定部上にレジストパターン８を形成した
後これら積層パターン７1，７2及びレジストパ
ターン８をマスクとしてボロンを加速電圧
180keV、ドーズ量４×1018／cm2の条件でイオ
ン注入し、活性化してp+型のチヤネルストツ
パ９…を形成した（第２図図示）。[] Next, a silicon nitride layer with a thickness of 2000 Å and a silicon nitride layer with a thickness of 5000 Å are directly deposited on the polycrystalline silicon layer 4.
After sequentially depositing two SiO layers by vapor phase epitaxy,
It is patterned by a photo-etching process using reactive sputter ion etching to form a planned device region of the substrate 1 (planned p-channel MOS transistor region) and a planned device region of the p-well 2 (planned n-channel MOS transistor region). ), silicon nitride layers 5 1 , 5 2 , SiO 2 layers 6 1 ,
Laminated patterns 7 1 and 7 2 consisting of 6 2 layers were respectively formed. Subsequently, after forming a resist pattern 8 on the planned p-channel MOS transistor region, using these laminated patterns 7 1 , 7 2 and the resist pattern 8 as masks, boron is applied to
Ions were implanted under the conditions of 180 keV and a dose of 4×10 18 /cm 2 and activated to form p + type channel stoppers 9 (as shown in FIG. 2).
〔〕 次いでフツ化アンモニウム液でSiO2層
６1，６2を除去し、残つたパターン化された窒
化シリコン層５1，５2を耐酸化性マスクとして
多結晶シリコン層４を選択酸化した。この時、
多結晶シリコン層４の露出部付近が酸化されて
寸法度換差が0.15μmの素子間分離用の厚さ
8000Åの厚い酸化膜１０…が形成された（第３
図図示）。また窒化シリコン層５1，５2下の酸
化されずに残つた多結晶シリコン層４1′，４
2′の前記酸化膜１０…に沿う表面部分にはオキ
シナイトライド膜が全く生じなかつた。[] Next, the SiO 2 layers 6 1 and 6 2 were removed using an ammonium fluoride solution, and the polycrystalline silicon layer 4 was selectively oxidized using the remaining patterned silicon nitride layers 5 1 and 5 2 as oxidation-resistant masks. At this time,
The exposed portion of the polycrystalline silicon layer 4 is oxidized to a thickness for isolation between elements with a dimensional difference of 0.15 μm.
A thick oxide film 10 of 8000 Å was formed (third
(Illustrated) Moreover, the polycrystalline silicon layers 4 1 ' , 4 remaining unoxidized under the silicon nitride layers 5 1 , 5 2
No oxynitride film was formed on the surface portion along the oxide film 10 2 '.
〔〕 次いで、窒化シリコン層５1，５2をCF4
系のドライエツチングにより除去した後、残存
多結晶シリコン層４1′，４2′をCCl4系の反応性
スパツタイオンエツチングで除去した。この
時、残存多結晶シリコン層４1′，４2′表面には
オキシナイトライド膜が存在しないため、厚い
酸化膜１０…に対してセルフアラインで該多結
晶シリコン層４1′，４2′が略垂直にエツチング
され、第４図に示す如く厚い酸化膜１０…の素
子領域予定部側の側面のオーバーハング部に多
結晶シリコン層４″が残つた。ひきつづき、露
出した熱酸化膜３をフツ化アンモニウム液で除
去して基板１及びｐ―ウエル２の素子領域を露
出させた（同第４図図示）。[] Next, the silicon nitride layers 5 1 and 5 2 are coated with CF 4
After removal by dry etching, the remaining polycrystalline silicon layers 4 1 ′ and 4 2 ′ were removed by reactive sputter ion etching using CCl 4 . At this time, since there is no oxynitride film on the surfaces of the remaining polycrystalline silicon layers 4 1 ′, 4 2 ′, the polycrystalline silicon layers 4 1 ′, 4 2 ′ are self-aligned with respect to the thick oxide film 10 . was etched almost vertically, and a polycrystalline silicon layer 4'' remained on the side surface of the thick oxide film 10 on the side where the device area was to be planned, as shown in FIG. 4. Subsequently, the exposed thermal oxide film 3 was etched. The element regions of the substrate 1 and the p-well 2 were exposed by removing with an ammonium fluoride solution (as shown in FIG. 4).
〔〕 次いで、熱酸化処理を施した。この時ｎ
型単結晶シリコン基板１及びｐ―ウエル２の露
出した素子領域にゲート酸化膜となる厚さ400
Åの酸化膜１１1，１１2が成長されると同時
に、オーバーハング部に残つた多結晶シリコン
層４″が酸化膜となり前記厚い酸化膜と共にオ
ーバーハング部のない素子間分離膜１２…が形
成された（第５図図示）。[] Next, thermal oxidation treatment was performed. At this time n
A gate oxide film with a thickness of 400 mm is deposited on the exposed device region of the single-crystal silicon substrate 1 and the p-well 2.
At the same time as the oxide films 11 1 and 11 2 of Å are grown, the polycrystalline silicon layer 4'' remaining in the overhang portion becomes an oxide film, and together with the thick oxide film, an inter-element isolation film 12 without an overhang portion is formed. (as shown in Figure 5).
〔〕 次いで、常法に従つて素子間分離膜１２
…で分離された基板１及びｐ―ウエル２の素子
領域上の酸化膜１１1，１１2に夫々多結晶シリ
コンのゲート電極１３1，１３2を形成し、同ゲ
ート電極１３1，１３2をマスクとして酸化膜１
１1，１１2をエツチングしてゲート酸化膜１４
１，１４2を形成し、更にｎ型の単結晶シリコン
基板１にボロンを選択的にイオン注入し、活性
化してp+型のソース、ドレイン領域１５1，１
６1を形成してｐチヤネルMOSトランジスタを
作製し、一方ｐ―ウエル２に砒素を選択的にイ
オン注入し、活性化してn+型のソース、ドレ
イン領域１５2，１６2を形成してｎチヤネル
MOSトランジスタを作製し、CMOSを造つた
（第６図図示）。[] Next, the inter-element isolation film 12 is formed according to a conventional method.
Gate electrodes 13 1 and 13 2 of polycrystalline silicon are formed on the oxide films 11 1 and 11 2 on the element regions of the substrate 1 and the p-well 2, which are separated by ... , respectively. Oxide film 1 as a mask
1 1 and 11 2 to form a gate oxide film 14.
1 , 14 2 , and then selectively implant boron ions into the n-type single crystal silicon substrate 1 and activate it to form p + -type source and drain regions 15 1 , 1
6 1 to fabricate a p-channel MOS transistor, while selectively implanting arsenic ions into the p-well 2 and activating it to form n + type source and drain regions 15 2 and 16 2 . channel
A MOS transistor was fabricated and a CMOS was fabricated (as shown in Figure 6).
しかして、本発明はｎ型単結晶シリコン基板１
及びこれに選択的に形成されたｐ―ウエル２上に
多結晶シリコン層４を形成し、これを選択酸化す
ることにより素子間分離膜１２…を形成するた
め、従来の選択酸化法に比べて酸化時間を著しく
短かくでき、ひいては基板１及びｐ―ウエル２へ
の熱影響を抑制できｐ―ウエルドライブイン中に
導入された欠陥の核による多数の欠陥発生を少な
くできると共に、予め形成されたｐ―ウエル２の
不純物の再拡散を著しく少なくできる。また、従
来の選択酸化法の如く基板及びｐ―ウエルの一部
を直接酸化して素子間分離膜を造るのではなく、
基板１及びｐ―ウエル２上の、多結晶シリコン層
４の選択酸化により素子間分離膜１２…を形成す
るため、基板１及びｐ―ウエル２への多大なスト
レス発生を防止できる。更に、多結晶シリコン層
４上に直接パターン化した窒化シリコン層５1，
５2を形成した選択酸化においては、オキシナイ
トライド膜が多結晶シリコン層４表面上の一部に
形成されないことは勿論、基板１及びウエル２上
にも全く形成されない。したがつて、選択酸化後
においてもｎ型単結晶シリコン基板１及びｐ―ウ
エル２に欠陥発生が極めて少ないため、リーク電
流の発生を抑生した電気特性の良好なCMOSの
高歩留りで製造できる。 Therefore, the present invention provides an n-type single crystal silicon substrate 1.
A polycrystalline silicon layer 4 is formed on the p-well 2 selectively formed thereon, and the inter-element isolation film 12 is formed by selectively oxidizing this, which is faster than the conventional selective oxidation method. It is possible to significantly shorten the oxidation time, thereby suppressing the thermal influence on the substrate 1 and the p-well 2, and reducing the occurrence of many defects due to defect nuclei introduced during the p-well drive-in. Rediffusion of impurities in the p-well 2 can be significantly reduced. In addition, unlike the conventional selective oxidation method, the substrate and part of the p-well are not directly oxidized to create an isolation film between elements.
Since the inter-element isolation films 12 are formed by selective oxidation of the polycrystalline silicon layer 4 on the substrate 1 and the p-well 2, it is possible to prevent generation of great stress on the substrate 1 and the p-well 2. Furthermore, a silicon nitride layer 5 1 patterned directly on the polycrystalline silicon layer 4 ,
In the selective oxidation that formed 5 2 , the oxynitride film is not formed on a part of the surface of the polycrystalline silicon layer 4 , and is not formed on the substrate 1 and the well 2 at all. Therefore, even after selective oxidation, there are very few defects in the n-type single-crystal silicon substrate 1 and the p-well 2, so that CMOS with good electrical characteristics and suppressed leakage current can be manufactured at a high yield.
また、基板１へのボロンのイオン注入に際し、
窒化シリコン層５1，５2とSiO2層６1，６2とから
なる積層パターン７1，７2をマスクとしてイオン
注入するため、基板１への応力発生要因となる窒
化シリコン層５1，５2を厚くしなくとも、該積層
パターン７1，７2（素子形成予定部）下の基板１
及びｐ―ウエル２へのボロンの注入を阻止でき、
素子形成領域の表面濃度の変化、つまり閾値電圧
の変動を防止できる。しかも、積層パターン７1，
７2の上層となるSiO2層６1，６2は窒化シリコン
層５1，５2と同一とレジストパターンをマスクと
して形成され、別のレジストパターンを窒化シリ
コン層上に形成することによる該窒化シリコン層
とレジストパターンのマスク合わせずれは生じな
い。このため、チヤネルストツパ９を窒化シリコ
ン層５1，５2に対してセルフアラインで形成でき
る。 Furthermore, when implanting boron ions into the substrate 1,
Since ions are implanted using the laminated pattern 7 1 , 7 2 consisting of the silicon nitride layers 5 1 , 5 2 and the SiO 2 layers 6 1 , 6 2 as a mask, the silicon nitride layers 5 1 , 7 2 are a cause of stress generation in the substrate 1 . The substrate 1 under the laminated patterns 7 1 , 7 2 (area where elements are to be formed) does not need to be thickened.
and can prevent boron injection into p-well 2,
Changes in the surface concentration of the element formation region, that is, changes in the threshold voltage can be prevented. Moreover, the laminated pattern 7 1 ,
The SiO 2 layers 6 1 and 6 2 which are the upper layers of 7 2 are formed using the same resist pattern as the silicon nitride layers 5 1 and 5 2 as a mask, and the nitridation is performed by forming another resist pattern on the silicon nitride layer. Misalignment of the mask alignment between the silicon layer and the resist pattern does not occur. Therefore, the channel stopper 9 can be formed in self-alignment with respect to the silicon nitride layers 5 1 and 5 2 .
更に多結晶シリコン層４上に直接窒化シリコン
パターン５1，５2を形成して選択酸化すれば、窒
化シリコンパターン５1，５2下の多結晶シリコン
層４部分への酸化膜の喰い込み、つまりバーズビ
ークは0.15μmに抑えられること並びに残存多結
晶シリコン層４1′，４2′表面の一部にオキシナイ
トライド膜が生成せず、厚い酸化膜６…に対して
セルフアラインで残存多結晶シリコン層４1′，４
2′を略垂直にエツチングできることにより、寸法
変換差が少なく微細な素子分離膜８…を形成で
き、その結果ｐチヤネル、ｎチヤネルMOSトラ
ンジスタ微細化が達成されたCMOSを得ること
ができる。 Furthermore, if silicon nitride patterns 5 1 , 5 2 are directly formed on the polycrystalline silicon layer 4 and selective oxidation is performed, the oxide film digs into the portion of the polycrystalline silicon layer 4 below the silicon nitride patterns 5 1 , 5 2 . In other words, the bird's beak can be suppressed to 0.15 μm, and an oxynitride film is not formed on a part of the surface of the remaining polycrystalline silicon layers 4 1 ′, 4 2 ′, and the remaining polycrystals are self-aligned with respect to the thick oxide film 6 . Silicon layer 4 1 ', 4
2 ' can be etched substantially vertically, it is possible to form fine element isolation films 8 with little difference in dimensional conversion, and as a result, it is possible to obtain a CMOS in which miniaturization of p-channel and n-channel MOS transistors has been achieved.
以上詳述した如く、本発明によれば選択酸化時
において半導体基板及びこれに選択的に形成され
た基板と逆導電型ウエルへ多大な熱影響、ストレ
ス生を招くことなく十分耐圧の高素子間分離膜の
形成並びチヤネルストツパを素子間分離膜に対し
てセルフアラインで形成することを可能とするこ
とにより、基板及びウエル欠陥が極めて少なくリ
ーク電流の発生が抑制された電気特性の良好な
CMOSを高歩留りで製造できる等顕著な効果を
有する。 As described in detail above, according to the present invention, during selective oxidation, the semiconductor substrate and the substrate selectively formed thereon and the reverse conductivity type wells are not affected by heat or stress, and the high-withstand voltage is sufficiently high. By making it possible to form isolation films and channel stoppers in self-alignment with respect to the isolation film, it is possible to achieve good electrical characteristics with extremely few substrate and well defects and suppressed leakage current.
It has remarkable effects such as being able to manufacture CMOS with high yield.
第１図〜第６図は本発明の実施例における
CMOSの製造工程を示す断面図である。
１…ｎ型単結晶シリコン基板、２…ｐ―ウエ
ル、３…熱酸化膜、４…多結晶シリコン層、４
1′，４2′…残存多結晶シリコン層、５1，５2…窒
化シリコン層、６1，６2…SiO2層、７1，７2…積
層パターン、１０…厚い酸化膜、１２…素子間分
離膜、１３1，１３2…ゲート電極、１４1，１４2
…ゲート酸化膜、１５1，１５2…ソース領域、１
６1，１６2…ドレイン領域。
FIGS. 1 to 6 show examples of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of CMOS. 1... N-type single crystal silicon substrate, 2... P-well, 3... Thermal oxide film, 4... Polycrystalline silicon layer, 4
1 ', 4 2 '...Remaining polycrystalline silicon layer, 5 1 , 5 2 ... Silicon nitride layer, 6 1 , 6 2 ... SiO 2 layer, 7 1 , 7 2 ... Laminated pattern, 10... Thick oxide film, 12... Interelement isolation film, 13 1 , 13 2 ...gate electrode, 14 1 , 14 2
...gate oxide film, 15 1 , 15 2 ...source region, 1
6 1 , 16 2 ... drain region.
Claims (1)
程と、この材料層上に耐酸化性材料層と不純物ド
ーピングマスク材料層からなる二層構造のパター
ンを選択的に形成する工程と、このパターンをマ
スクとして半導体基板に不純物をイオン注入する
工程と、前記不純物ドーピングマスク材料層を除
去した後、耐酸化性材料層のパターンをマスクと
して前記被酸化性材料層を少なくとも一部酸化し
て酸化膜を形成する工程と、前記半導体基板の一
部が露出するように前記耐酸化性材料層のパター
ンとその下の残存被酸化性材料層を少なくとも一
部除去する工程とを具備したことを特徴とする半
導体装置の製造方法。 ２ 半導体基板と被酸化性材料層との間に酸化膜
を介在させることを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。 ３ 耐酸化性材料として窒化シリコンを、不純物
ドーピングマスク材料として気相成長酸化シリコ
ンを、用いることを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。 ４ 被酸化性材料として高不純物濃度多結晶シリ
コンあるいはモリブデンシリサイドあるいはタン
グステンシリサイドを用いることを特徴とする前
記特許請求の範囲第１項記載の半導体装置の製造
方法。 ５ 露出した残存被酸化材料層の少なくとも一部
を除去するに際し、異方性エツチングを用いて行
なうことを特徴とする特許請求の範囲第１項ない
し第４項いずれか記載の半導体装置の製造方法。 ６ 選択酸化により形成された酸化膜が素子間分
離膜であることを特徴とする特許請求の範囲第１
項ないし第５項いずれか記載の半導体装置の製造
方法。[Claims] 1. A step of forming an oxidizable material layer on a semiconductor substrate, and selectively forming a two-layer pattern consisting of an oxidation-resistant material layer and an impurity doping mask material layer on this material layer. a step of ion-implanting an impurity into the semiconductor substrate using this pattern as a mask; and after removing the impurity doping mask material layer, using the pattern of the oxidation-resistant material layer as a mask, at least one of the oxidizable material layers is ion-implanted into the semiconductor substrate; a step of partially oxidizing the semiconductor substrate to form an oxide film; and a step of removing at least a portion of the pattern of the oxidation-resistant material layer and the remaining oxidizable material layer thereunder so that a portion of the semiconductor substrate is exposed. A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, characterized in that an oxide film is interposed between the semiconductor substrate and the oxidizable material layer. 3. The method of manufacturing a semiconductor device according to claim 1, characterized in that silicon nitride is used as the oxidation-resistant material and vapor-phase grown silicon oxide is used as the impurity doping mask material. 4. The method of manufacturing a semiconductor device according to claim 1, characterized in that polycrystalline silicon with high impurity concentration, molybdenum silicide, or tungsten silicide is used as the oxidizable material. 5. A method for manufacturing a semiconductor device according to any one of claims 1 to 4, characterized in that anisotropic etching is used to remove at least a portion of the exposed remaining oxidizable material layer. . 6 Claim 1, characterized in that the oxide film formed by selective oxidation is an isolation film between elements.
5. A method for manufacturing a semiconductor device according to any one of items 5 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57012832A JPS58131761A (en) | 1982-01-29 | 1982-01-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57012832A JPS58131761A (en) | 1982-01-29 | 1982-01-29 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58131761A JPS58131761A (en) | 1983-08-05 |
| JPH023306B2 true JPH023306B2 (en) | 1990-01-23 |
Family
ID=11816345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57012832A Granted JPS58131761A (en) | 1982-01-29 | 1982-01-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58131761A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2770576B2 (en) * | 1991-01-25 | 1998-07-02 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH0518435U (en) * | 1991-08-13 | 1993-03-09 | 象印マホービン株式会社 | Vacuum double container |
| JP3298780B2 (en) * | 1995-08-30 | 2002-07-08 | アルプス電気株式会社 | Thermal head and method of manufacturing thermal head |
-
1982
- 1982-01-29 JP JP57012832A patent/JPS58131761A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58131761A (en) | 1983-08-05 |
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