JPH02303134A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02303134A JPH02303134A JP12473689A JP12473689A JPH02303134A JP H02303134 A JPH02303134 A JP H02303134A JP 12473689 A JP12473689 A JP 12473689A JP 12473689 A JP12473689 A JP 12473689A JP H02303134 A JPH02303134 A JP H02303134A
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- substrate
- gas
- film
- heated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 26
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 claims description 32
- 239000010409 thin film Substances 0.000 claims description 14
- 238000010030 laminating Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 abstract description 16
- 239000011521 glass Substances 0.000 abstract description 13
- 230000003647 oxidation Effects 0.000 abstract description 10
- 238000007254 oxidation reaction Methods 0.000 abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 230000008018 melting Effects 0.000 abstract description 6
- 238000002844 melting Methods 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 230000003685 thermal hair damage Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 241000511976 Hoya Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910001634 calcium fluoride Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005025 nuclear technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明はガラス基板のような非晶質絶縁基板上に成膜し
た半導体薄膜表面に高品質の絶縁膜を形成する方法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a high quality insulating film on the surface of a semiconductor thin film formed on an amorphous insulating substrate such as a glass substrate.
［従来の技術］
近年、大型で高解像度の液晶表示パネル、高速で高解像
度の密着型イメージセンサ、三次元工Ｃ等への実現に向
けて、ガラス、石英等の絶縁性非晶質基板や、５ｉ０２
等の絶縁性非晶質層上に、高性能な半導体素子を形成す
る試みが成されている。特に大型の液晶表示パネル等に
於いては、低コストの要求を満たすため、安価な低融点
ガラス上に薄膜トランジスタ（ＴＰＴ）を形成すること
が必須の要求になりつつある。従来は、低融点ガラス基
板上に形成するＴＦＴのゲート絶縁膜に、Ｊｏｕｒｎａ
ｌ ｏｆ Ｖａｃｕｕｍ ５ｃｉｅｎｃｅ Ｔｅｃｈｎ
ｏｌｏｇｙ Ｖｏｌ、Ｂ６（２） ｐ、５１７ （１９
８８）等に見られるようにプラズマ気相成長法（ＰＣＶ
Ｄ）を用いたもの、 ＡｐｐｌｉｅｄＰｈｙｓｉｃｓ
Ｌｅｔｔｅｒｓ Ｖｏｌ、５０（１７） ｐ、１１６
７ （１９８７）等にみられるように減圧化学気相成長
法（ＬＰＧＶＤ）を用いたもの、Ｅｌｅｃｔｒｏｎｉｃ
ｓ Ｌｅｔｔｅｒｓ Ｖｏｌ、２４（３）ｐ、１７２
（１９８８）、 Ｊａｐａｎｅｓｅ Ｊｏｕｒｎａｌ
ｏｆ ＡｐｐｌｉｅｄＰｈｙｓｉｃｓ Ｖｏｌ、２６（
６） ｐ、８０５，８３５．Ｌ９０Ｂ （１９８８）等
にみられるように光化学気相成長法を用いたもの、Ｊａ
ｐａｎｅｓｅ Ｊｏｕｒｎａｌ ｏｆ Ａｐｐｌｉｅｄ
Ｐｈｙｓｉｃｓ Ｖｏｌ、２２（４） ｐ、Ｌ２１０
（１９８３）等にみられるようにＥＣＲプラズマ気相
成長法を用いたもの等があり、いずれも低温成膜法で作
製したＳｉＯ２薄膜を用いてきた。[Conventional technology] In recent years, insulating amorphous substrates such as glass and quartz have been developed to realize large, high-resolution liquid crystal display panels, high-speed, high-resolution contact image sensors, and three-dimensional engineering. ,5i02
Attempts have been made to form high-performance semiconductor elements on insulating amorphous layers such as . Particularly in large liquid crystal display panels and the like, in order to meet the demand for low cost, it is becoming essential to form thin film transistors (TPT) on inexpensive low melting point glass. Conventionally, the gate insulating film of a TFT formed on a low melting point glass substrate was
l of Vacuum 5science Techn
ology Vol, B6(2) p, 517 (19
88), the plasma vapor deposition method (PCV)
D), Applied Physics
Letters Vol, 50(17) p, 116
7 (1987), etc., using low pressure chemical vapor deposition (LPGVD), Electronic
s Letters Vol, 24(3)p, 172
(1988), Japanese Journal
of Applied Physics Vol. 26 (
6) p, 805,835. Those using photochemical vapor deposition as seen in L90B (1988) etc., Ja
panese Journal of Applied
Physics Vol, 22(4) p, L210
(1983), etc., using the ECR plasma vapor phase growth method, and all of them have used SiO2 thin films produced by low-temperature film formation methods.
［発明が解決しようとする課題］
しかし、ＴＰＴのゲート酸化膜の形成を低温（＜６００
’Ｃ）で行なう場合、高温酸化法で形成したゲート絶縁
膜と比較すると膜質が劣り、高性能のＴＰＴが実現でき
ないという問題点があった。[Problem to be solved by the invention] However, the formation of the gate oxide film of TPT is performed at a low temperature (<600℃).
In the case of 'C), there was a problem that the film quality was inferior to that of a gate insulating film formed by high-temperature oxidation, and a high-performance TPT could not be realized.
一方、集積回路の微細化、高集積化にともない、ＩＥＥ
Ｅ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｌｅｔｔｅｒｓ
、 Ｖｏｌ、 ＥＤＬ−６，Ｎｏ。On the other hand, as integrated circuits become smaller and more highly integrated, IEE
E Electron Device Letters
, Vol. EDL-6, No.
５ 、２０５ 、 （１９８５）等にみられるように、
ＭＯＳトランジスタのゲート酸化膜工程で発生する熱的
ダメージを低減する目的で急速熱酸化法（ＲＴＯ）と呼
ばれる方法で、通常の熱酸化膜に匹敵する膜質の酸化膜
を得られるため注目を集めるようになってきた。しかし
、従来のＲＴＯ法は専ら結晶シリコン半導体の製造に用
いられたものであり、低融点ガラス基板上のＴＰＴの製
造に用いる方法ではなかった。5, 205, (1985), etc.
A method called rapid thermal oxidation (RTO) is used to reduce the thermal damage that occurs in the gate oxide film process of MOS transistors, and it is attracting attention because it can produce an oxide film with a quality comparable to that of ordinary thermal oxide films. It has become. However, the conventional RTO method was used exclusively for manufacturing crystalline silicon semiconductors, and was not a method used for manufacturing TPT on a low melting point glass substrate.
本発明は以上の問題点を解決するもので、その目的は低
融点のガラス基板上に成膜した半導体薄膜表面に高品質
のゲート絶縁膜を形成する方法を提供することにある。The present invention solves the above problems, and its purpose is to provide a method for forming a high quality gate insulating film on the surface of a semiconductor thin film formed on a low melting point glass substrate.
［課題を解決するための手段］
本発明の半導体装置の製造方法は、
（１）非晶質絶縁基板上に成膜した半導体３膜の表面を
熱酸化する方法において、前記非晶質絶縁基板の軟化点
よりも高温に基板表面温度を急速に上昇させる工程と、
前記非晶質絶縁基板の温度が軟化点に到達するのに要す
る時間よりも短い時間だけ前記温度を保持しつつ前記半
導体薄膜を熱酸化する工程と、前記基板温度を急速に低
下させる工程とを少なくとも含むことを特徴とする。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes: (1) a method of thermally oxidizing the surface of three semiconductor films formed on an amorphous insulating substrate; a step of rapidly increasing the substrate surface temperature to a temperature higher than the softening point of the substrate;
thermally oxidizing the semiconductor thin film while maintaining the temperature for a time shorter than the time required for the temperature of the amorphous insulating substrate to reach its softening point; and rapidly lowering the substrate temperature. It is characterized by comprising at least:
（２）前記熱酸化膜上に低温で形成する絶縁膜を積層す
る工程を有することを特徴とする。(2) The method is characterized by comprising a step of laminating an insulating film formed at a low temperature on the thermal oxide film.
［実施例コ
第１図にＴＰＴの製造工程図を示す。本実施例ではｎチ
ャネルＴＰＴの製造工程について説明するが、ｐチャネ
ルの場合についても同様なのはもちろんである。ガラス
基板１００ （ＨＯＹＡ製ＮＡ−４０； 軟化点８００
℃、基板厚３ｍｍ）上に５ｉＯ２１０１をＬＰＧＶＤ法
を用い、基板温度４５０°Ｃで約２００ＯＡ成膜し、こ
の上に非晶質シリコン（ａ−３ｉ）をＰＣＶＤ法で１５
００人成膜する。ここでａ−３ｉをＴＰＴのチャネル部
のパタンにパタニングする。ここでａ−３ｉを６００℃
で１７時間以上Ｎ２アニールしてＳｉ薄膜１０２の面相
成長を行い、Ｓｉの結晶粒径を１μｍ程度まで成長させ
る（第１図（ａ））、 固相成長させずに急速熱酸化
（ＲＴＯ）を行うと、ａ−３ｉが爆発的に多結晶化し、
結晶粒径の小さいｐ。[Example 1] Fig. 1 shows a manufacturing process diagram of TPT. In this embodiment, the manufacturing process of an n-channel TPT will be explained, but it goes without saying that the same applies to the case of a p-channel. Glass substrate 100 (NA-40 made by HOYA; softening point 800
A film of about 200 OA of 5iO2101 was formed using the LPGVD method at a substrate temperature of 450°C (3 mm substrate thickness), and amorphous silicon (a-3i) was deposited on this film using the PCVD method for 150 OA.
00 people will deposit. Here, a-3i is patterned into the pattern of the channel portion of TPT. Here, a-3i is heated to 600℃
The Si thin film 102 is grown in planar phase by N2 annealing for 17 hours or more to grow the Si crystal grain size to approximately 1 μm (Fig. 1(a)). Rapid thermal oxidation (RTO) is performed without solid phase growth. When this is done, a-3i becomes polycrystalline explosively,
p with small grain size.
１ｙ−３ｉ薄膜しか得られず、ＴＰＴの性能が上がらな
いためである。またここで、ＰＣＶＤで成膜したａ−３
ｉを用いるのは、ＬＰＧＶＤ等で成膜したｐｏｌｙ−３
ｉを固相成長させるよりも大粒径のＳｉ薄膜が得られる
からである。This is because only a 1y-3i thin film can be obtained and the performance of TPT cannot be improved. Also, here, a-3 film formed by PCVD
i is used for poly-3 film formed by LPGVD etc.
This is because a Si thin film with a larger grain size can be obtained than by solid phase growth of i.
この段階でゲート酸化膜形成用の急速熱酸化を行う。以
下、第２図に示すような温度変化をガスに与える。即ち
、基板を酸化炉にいれ、加熱したＮ２ガスを流して基板
温度を約３０ ｍ ｉ ｎ、 かけて室温から７００
°Ｃまで上昇させ、５〜１０ｍ１ｎ。At this stage, rapid thermal oxidation is performed to form a gate oxide film. Thereafter, a temperature change as shown in FIG. 2 is applied to the gas. That is, the substrate was placed in an oxidation furnace, and heated N2 gas was flowed to raise the substrate temperature from room temperature to 700 min by approximately 30 min.
Raise to °C, 5-10 m1n.
かけて温度を安定させる。ここで０２ガスに切り換え、
０２ガスの温度を７００°Ｃから１１５０°Ｃまで１秒
で上昇させ、ついでこの状態を２秒保ったあと再び７０
０℃まで０２ガスの温度を１秒で下降させる。０２ガス
の温度変化方法は、７００℃と１１５０°Ｃに予め加熱
されている２種類の０２ガスを切り換える方法をとる。to stabilize the temperature. Now switch to 02 gas,
Raise the temperature of 02 gas from 700°C to 1150°C in 1 second, then maintain this state for 2 seconds and then raise it again to 700°C.
Lower the temperature of 02 gas to 0°C in 1 second. The method for changing the temperature of the 02 gas is to switch between two types of 02 gas that have been preheated to 700°C and 1150°C.
Ｎ２ガスに再び切り換えて、基板温度を室温まで約３０
ｍ ｉ ｎ、 かけて戻す。Switch back to N2 gas and bring the substrate temperature to room temperature for about 30 minutes.
Min, call it back.
この段階で約１０人のゲート酸化膜が形成されている。At this stage, about 10 gate oxide films have been formed.
このＲＴ○工程においては、ガラス基板は水平に保持し
、酸化工程中で余計なストレスが基板にかからないよう
に工夫する必要がある。基板を水平にする保持台は、耐
熱性、耐酸化性が高く、かつ基板に対する熱ダメージを
最小限に押えるため、熱伝導性のよいＢＮ等を用いるの
が望ましい。In this RT◯ step, it is necessary to hold the glass substrate horizontally so that no unnecessary stress is applied to the substrate during the oxidation step. The holding table for horizontally holding the substrate is preferably made of BN or the like with good thermal conductivity, in order to have high heat resistance and oxidation resistance, and to minimize thermal damage to the substrate.
ＲＴ○工程後、５ｉＨａ、０２、Ｎ２ガスの混合ガスに
よる常圧化学気相成長法で更にＳｉＯ２膜を約１０００
人成膜させる（第１図（ｂ））。この時の基板温度は４
８０℃である。この様にして作製したゲート絶縁膜１０
３は、通常のゲート絶縁膜と殆ど変わらない絶縁耐圧を
示し、高品質な酸化膜になっていることがわかる。また
、絶縁基板は石英基板やガラス基板だけではなく、サフ
ァイア基板（Ａ１２０３）あるいはＭｇＯ・Ａ Ｉ ２
０３． Ｂ Ｐ。After the RT○ process, a SiO2 film with a thickness of about 1000 ml is further grown by atmospheric pressure chemical vapor deposition using a mixed gas of 5iHa, 02, and N2 gas.
The film is deposited manually (Fig. 1(b)). The substrate temperature at this time is 4
The temperature is 80°C. Gate insulating film 10 produced in this way
No. 3 shows a dielectric strength voltage that is almost the same as that of a normal gate insulating film, indicating that it is a high-quality oxide film. In addition, the insulating substrate is not only a quartz substrate or a glass substrate, but also a sapphire substrate (A1203) or MgO・AI 2
03. B P.
ＣａＦ２等の結晶性絶縁基板も用いることができる。A crystalline insulating substrate such as CaF2 can also be used.
次にゲート電極１０４となるｐｏｌｙ−３ｉをＬＰＣＶ
Ｄで約３０００人成膜する。ゲート電極パタニング後、
Ｐ゛イオン７０ＫｅＶのエネルギーで５ ｘ １０”ｃ
ｍ−２の温度に打ち込みソース領域１０５、ドレイン領
域１０６を形成する（第１図（Ｃ））。層間絶縁膜１０
７をＬＰＣＶＩ）Ｃ−約８０００Ａ成膜後、イオンを活
性化させるため、６００℃で２０時間アニールを行う。Next, poly-3i which will become the gate electrode 104 is LPCVed.
Approximately 3,000 people will form a film in D. After gate electrode patterning,
P゛ion 5 x 10”c at 70KeV energy
A source region 105 and a drain region 106 are formed by implantation at a temperature of m-2 (FIG. 1(C)). Interlayer insulation film 10
After forming a film of about 8000 A, annealing is performed at 600° C. for 20 hours to activate the ions.
電極取り出し用のコンタクトホールを開け、配線電極１
０８のＡｌ５ｉＣｕを約８００ＯＡスパツタし、配線を
形成する。この後プラズマ反応炉内で水素プラズマを基
板温度２５０℃で１２０ ｍ ｉ ｎ、 かけてＴＰ
Ｔの完成となる（第１図（ｄ））、 この様にして、
低融点で安価なガラス基板を用いても高性能のＴＰＴを
作製することができる。Open a contact hole for taking out the electrode, and connect wiring electrode 1.
Approximately 800 OA of Al5iCu of No. 08 is sputtered to form wiring. After this, hydrogen plasma was applied in a plasma reactor for 120 min at a substrate temperature of 250°C to perform TP.
In this way, T is completed (Figure 1 (d)).
A high-performance TPT can be manufactured even using a glass substrate that is low in melting point and inexpensive.
［発明の効果コ
本発明によって得られた薄膜トランジスタは、従来の低
温成膜法によって製作したＴＰＴに比べてＯＮ電流は増
大しＯＦＦ電流は小さくなる。またスレッシュホルド電
圧も小さくなりトランジスタ特性が大きく改善される。[Effects of the Invention] The thin film transistor obtained by the present invention has an increased ON current and a decreased OFF current compared to a TPT manufactured by a conventional low-temperature film formation method. In addition, the threshold voltage is also reduced, and transistor characteristics are greatly improved.
非晶質絶縁基板上に優れた特性の薄膜トランジスタを作
製することが可能となるので、ドライバー回路を同一基
板上に集積した液晶ディスプレイ等のアクティブマトリ
クス基板に応用した場合にも十分な高速動作が実現され
る。さらに、電源電圧の低減、消費電流の低減、信頼性
の向上に対して大きな効果がある。また、７００″Ｃ以
下の低温プロセスによる作製も可能なので、アクティブ
マトリクス基板の低価格化及び大面積化に対してもその
効果は大きい。Since it is possible to fabricate thin film transistors with excellent characteristics on an amorphous insulating substrate, sufficient high-speed operation can be achieved even when applied to active matrix substrates such as liquid crystal displays where driver circuits are integrated on the same substrate. be done. Furthermore, it has great effects on reducing power supply voltage, reducing current consumption, and improving reliability. In addition, since it is possible to manufacture by a low-temperature process at 700''C or less, this is highly effective in reducing the cost and increasing the area of active matrix substrates.
本発明を、光電変換素子とその走査回路を同一チップ内
に集積した密着型イメージセンサ−に応用した場合には
、読み取り速度の高速化、高解像度化、さらに階調をと
る場合に大きな効果をうみだす。高解像度化が達成され
るとカラー読み取り用密着型イメージセンサ−への応用
も容易となる。When the present invention is applied to a contact image sensor in which a photoelectric conversion element and its scanning circuit are integrated on the same chip, it will have great effects in increasing the reading speed, increasing the resolution, and further increasing the gradation. It starts to emerge. Once high resolution is achieved, it will be easier to apply it to a contact type image sensor for color reading.
もちろん電源電圧の低減、消費電流の低減、信頼性の向
上に対してもその効果は大きい。また低温プロセスによ
って作製することができるので、低コストの低融点ガラ
ス基板を使用でき、密着型イメージセンサ−チップの長
尺化が可能となり、一本のチップでＡ４サイズあるいは
Ａ３サイズの様な大型ファクシミリ用の読み取り装置を
実現できる。従って、センサーチップの二本継ぎのよう
な手数がかかり信頼性の悪い技術を回避することができ
、実装歩留りも向上され、かつ素子の但コスト化に著し
い効果をあげる。Of course, this has great effects in reducing power supply voltage, reducing current consumption, and improving reliability. In addition, since it can be manufactured using a low-temperature process, it is possible to use a low-cost, low-melting-point glass substrate, and it is possible to increase the length of the contact image sensor chip. A reading device for facsimile can be realized. Therefore, it is possible to avoid a complicated and unreliable technique such as splicing two sensor chips together, improve the mounting yield, and have a significant effect on reducing the cost of the device.
以上絶縁基板上の薄膜トランジスタを例として説明した
が、単結晶Ｓｉ基板上の集積回路の素子分離技術に対し
ても、本発明を応用することができる。また、三次元デ
バイスのようなＳ○工核技術利用した素子に対しても、
本発明を応用することができる。Although the explanation has been given above using a thin film transistor on an insulating substrate as an example, the present invention can also be applied to element isolation technology for an integrated circuit on a single crystal Si substrate. Also, for elements using S○ engineering nuclear technology such as three-dimensional devices,
The present invention can be applied.
第１図は本発明の半導体装置の製造方法を示す図。
第２図は急速熱酸化工程におけるガス温度の変化図。
１００・・・・・・・・・非晶質絶縁基板１０１・・・
・・・・・・５ｉＯ２
１０２・・・・・・・・・Ｓｉ薄膜
１０３・・・・・・・・・ゲート絶縁膜１０４・・・・
・・・・・ゲート電極
１０５・・・・・・・・・ソース領域
１０６・・・・・・・・・ドレイン領域１０７・・・・
・・・・・層間絶縁膜
１０８・・・・・・・・・配線電極
以上FIG. 1 is a diagram showing a method for manufacturing a semiconductor device according to the present invention. Figure 2 is a diagram of changes in gas temperature during the rapid thermal oxidation process. 100...Amorphous insulating substrate 101...
......5iO2 102...Si thin film 103...Gate insulating film 104...
...Gate electrode 105...Source region 106...Drain region 107...
・・・・・・Interlayer insulating film 108・・・・・・More than wiring electrode
Claims (2)
熱酸化する方法において、前記非晶質絶縁基板の軟化点
よりも高温に基板表面温度を急速に上昇させる工程と、
前記非晶質絶縁基板の温度が軟化点に到達するのに要す
る時間よりも短い時間だけ前記温度を保持しつつ前記半
導体薄膜を熱酸化する工程と、前記基板温度を急速に低
下させる工程とを少なくとも含むことを特徴とする半導
体装置の製造方法。(1) In a method of thermally oxidizing the surface of a semiconductor thin film formed on an amorphous insulating substrate, the step of rapidly increasing the substrate surface temperature to a temperature higher than the softening point of the amorphous insulating substrate;
thermally oxidizing the semiconductor thin film while maintaining the temperature for a time shorter than the time required for the temperature of the amorphous insulating substrate to reach its softening point; and rapidly lowering the substrate temperature. A method for manufacturing a semiconductor device, the method comprising:
る工程を有することを特徴とする請求項１記載の半導体
装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: (2) laminating an insulating film formed at a low temperature on the thermal oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12473689A JP2805830B2 (en) | 1989-05-18 | 1989-05-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12473689A JP2805830B2 (en) | 1989-05-18 | 1989-05-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02303134A true JPH02303134A (en) | 1990-12-17 |
| JP2805830B2 JP2805830B2 (en) | 1998-09-30 |
Family
ID=14892842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12473689A Expired - Fee Related JP2805830B2 (en) | 1989-05-18 | 1989-05-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2805830B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291365B1 (en) | 1999-02-10 | 2001-09-18 | Nec Corporation | Method for manufacturing thin gate silicon oxide layer |
-
1989
- 1989-05-18 JP JP12473689A patent/JP2805830B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291365B1 (en) | 1999-02-10 | 2001-09-18 | Nec Corporation | Method for manufacturing thin gate silicon oxide layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2805830B2 (en) | 1998-09-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7037765B2 (en) | Semiconductor device and method of manufacturing the same | |
| US5904508A (en) | Semiconductor device and a method of manufacturing the same | |
| US5834827A (en) | Thin film semiconductor device, fabrication method thereof, electronic device and its fabrication method | |
| US8603870B2 (en) | Semiconductor device and method of manufacturing the same | |
| JP3163822B2 (en) | Transistor and manufacturing method thereof | |
| JPH0422120A (en) | Thin film semiconductor device | |
| JPH098313A (en) | Fabrication of semiconductor device and liquid crystal display | |
| JP2917388B2 (en) | Method for manufacturing semiconductor device | |
| JPH03104209A (en) | Manufacture of semiconductor device | |
| JPH02303134A (en) | Manufacture of semiconductor device | |
| JP2717233B2 (en) | Insulated gate field effect semiconductor device and method of manufacturing the same | |
| JP2004288864A (en) | Thin film semiconductor, manufacturing method thereof, electro-optical device and electronic equipment | |
| JP2000183351A (en) | Manufacture of thin-film semiconductor device | |
| JPH034564A (en) | Manufacture of semiconductor device | |
| JPS6336574A (en) | Thin film transistor | |
| JPH0393273A (en) | Manufacture of thin film semiconductor device | |
| JP3109650B2 (en) | Method for manufacturing thin film transistor | |
| JP2751420B2 (en) | Method for manufacturing semiconductor device | |
| JPH05235353A (en) | Active matrix substrate and manufacture thereof | |
| JP2794833B2 (en) | Method for manufacturing thin film transistor | |
| JPS63119268A (en) | Manufacture of semiconductor device | |
| KR0178489B1 (en) | Method for dopant activation in the fabrication of semiconductor devices | |
| JPH03108319A (en) | Manufacture of semiconductor device | |
| JP2995833B2 (en) | Method for manufacturing thin film semiconductor device | |
| JP3185790B2 (en) | Method for manufacturing thin film semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |