JPH02296372A - Transmissive base transistor - Google Patents
Transmissive base transistorInfo
- Publication number
- JPH02296372A JPH02296372A JP1117694A JP11769489A JPH02296372A JP H02296372 A JPH02296372 A JP H02296372A JP 1117694 A JP1117694 A JP 1117694A JP 11769489 A JP11769489 A JP 11769489A JP H02296372 A JPH02296372 A JP H02296372A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drain
- gate
- gate electrodes
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 230000006866 deterioration Effects 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000002265 prevention Effects 0.000 abstract 2
- 230000002950 deficient Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 229920001707 polybutylene terephthalate Polymers 0.000 description 24
- 239000002184 metal Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000605 extraction Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 241000238557 Decapoda Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66454—Static induction transistors [SIT], e.g. permeable base transistors [PBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は透過ベーストランジスタ（ＰＢＴ（Ｐｅｒｍ
ｅａｂｌｅ ’１３ａｓｅ Ｔｒａｈｓｉｓｔｏｒ）
）に関し、特にそのチャネル電流が基板厚さ方向に対し
て垂直方向に流れるようにした構造に関するものである
。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a transparent base transistor (PBT).
easy '13ase Trahsister)
), and particularly relates to a structure in which the channel current flows in a direction perpendicular to the substrate thickness direction.
第２図（ａ）〜（Ｃ）はそれぞれその構造が異なる従来
の透過ベーストランジスタ（ＰＢＴ）を説明するための
断面図であり、第２図（ａ）は埋込形ＰＢＴを示してい
る。図において、３はソース（エミッタ）用ｎ゛形形厚
導体層、ｎ゛形基板あるいはエピタキシャル成長層を用
いている。１は該ソース層３上にエピタキシャル成長し
たチャネル層、４は該チャネル層１」二に形成したドレ
イン（コレクタ）用ｎ゛゛導体層で、上記チャネル層ｌ
中央部にはグレーティング状の薄いショットキー金属か
らなるゲート（ベース）２が配設されており、該ゲ−１
−２近傍にはゲート空乏層が広がっている。FIGS. 2(a) to 2(C) are cross-sectional views for explaining conventional transparent base transistors (PBT) having different structures, and FIG. 2(a) shows a buried PBT. In the figure, reference numeral 3 uses an n-type thick conductor layer for the source (emitter), an n-type substrate, or an epitaxially grown layer. 1 is a channel layer epitaxially grown on the source layer 3; 4 is a drain (collector) conductor layer formed on the channel layer 1;
A gate (base) 2 made of a thin grating-like Schottky metal is arranged in the center, and the gate 1
A gate depletion layer spreads near -2.
また第２図（ｂ）、 （Ｃ）はそれぞれ掘込側壁形Ｐ
Ｂ Ｔ、及び掘込エッヂ形ＰＢＴを示しており、掘込側
壁形ＰＢＴではドレイン層４表面からチャネル層１中央
部に達する溝を形成し、該溝内にゲート２を配置してい
る点、また掘込エッヂ形ＰＢＴでば該溝内に配置したゲ
ート２をさらに断面台形形状にエッチ加工している点が
上記埋込形Ｐ Ｂ Ｔと構造１異なっている。In addition, Fig. 2 (b) and (C) respectively show the dug side wall shape P.
BT and a dug edge type PBT are shown; in the dug sidewall type PBT, a trench is formed from the surface of the drain layer 4 to the center of the channel layer 1, and the gate 2 is disposed within the trench; Further, the recessed edge type PBT differs from the buried type PBT in structure 1 in that the gate 2 disposed in the groove is further etched to have a trapezoidal cross section.
上述の３種のＰＢＴの断面構造は互いに異なっているも
のの、いずれもベース領域がグレーティング状の薄いシ
ョットキー金属ゲートと電流透過のチャネル部分とで構
成され、動作電流（チャネル電流）が縦方向、つまり基
板厚さ方向に流れる縦型構造となっている。Although the cross-sectional structures of the above-mentioned three types of PBTs are different from each other, all of them have a base region consisting of a thin Schottky metal gate in the form of a grating and a current-transmitting channel portion, and the operating current (channel current) is vertical. In other words, it has a vertical structure that flows in the thickness direction of the substrate.
すなわち、その主なる動作は、ベースであるショットキ
ー金属ゲートに入力制御信号が印加されると、上記ゲー
ト空乏層が変調されてチャネル部ゲート透過電流が変調
されるというものである。That is, its main operation is that when an input control signal is applied to the Schottky metal gate that is the base, the gate depletion layer is modulated and the channel portion gate transmission current is modulated.
そしてこのＰＢＴの動作に伴う主な特徴として以下の利
点を挙げることができる。The main features associated with the operation of this PBT include the following advantages.
■ ベース領域が縦型構造、つまりチャネル電流が基板
厚さ方向に流れる構造であるため、ゲート金属の厚さが
ゲート長に相当し、０．１μｍ程度の極短いゲート長を
容易に実現することができ、これにより超高周波動作を
期待することができる。■ Since the base region has a vertical structure, that is, a structure in which the channel current flows in the direction of the substrate thickness, the thickness of the gate metal corresponds to the gate length, and an extremely short gate length of about 0.1 μm can be easily achieved. As a result, ultra-high frequency operation can be expected.
■ またドレイン、ソース層間の能動層はエピタキシャ
ル成長により形成されるため、０．２〜０゜５１１ｍ程
度まで薄くすることも可能であり、ＧａＡｓ等の有効質
量の小さい化合物半導体ではバリステインク（弾道形）
電子伝導が起こり、走行時間遅れをさらに小さくでき、
超高速動作を行うことができる。■ Also, since the active layer between the drain and source layers is formed by epitaxial growth, it can be made as thin as 0.2 to 0.511 m.
Electron conduction occurs, further reducing the travel time delay.
Capable of ultra-high speed operation.
■ さらに入力制御信号がゲート金属を通じてゲート空
乏層容量に加わるため、ベース半導体層を通じて制御す
るバイポーラ１〜ランジスタなどに比べ寄生抵抗による
損失が小さい。(2) Furthermore, since the input control signal is applied to the gate depletion layer capacitance through the gate metal, the loss due to parasitic resistance is smaller than that of bipolar transistors, etc., which are controlled through the base semiconductor layer.
■ さらにまたｎ＋基板をソース用ｎ′層に用いた構造
ではインダクタンスの極めて小さい接地を実現すること
ができ、高周波窩電力トランジスタとして適している。(2) Furthermore, a structure in which an n+ substrate is used as the n' layer for the source can realize grounding with extremely small inductance, and is suitable as a high frequency socket power transistor.
ところが、従来のＰＢＴは縦方向デバイスであり、つま
り第２図（ａ）のＰＢＴ構造ではエピタキシャル成長層
であるチャネル層の中央部にゲー１−（ベース）電極が
位置しているため、該チャネル層上半部分では、結晶の
質が悪くなり、このため高耐圧化ができない等の問題点
が、また、第２図（ｂ）（Ｃ）のＰＢＴ構造ではゲート
（ベース）電極」二に半導体層が存在しないため結晶性
の劣下はあまり問題とはならないものの、ゲート（ベー
ス）とドレイン層との分離が構造的に難しい等の問題点
があった。However, the conventional PBT is a vertical device, and in other words, in the PBT structure shown in FIG. In the upper half, the quality of the crystal deteriorates, which causes problems such as the inability to achieve high breakdown voltage.In addition, in the PBT structure shown in Figure 2(b) and (C), the gate (base) electrode is Although deterioration of crystallinity is not so much of a problem because of the absence of , there are problems such as structural difficulty in separating the gate (base) and drain layers.
この発明は上記のような問題点を解消するためになされ
たもので、ゲート（ベース）電極近傍での半導体結晶の
質の劣化を防止でき、またトランジスタ構造を制御性、
再現性よく形成するのに適した透過型ベーストランジス
タを得ることを目的とする。This invention was made to solve the above-mentioned problems, and can prevent deterioration of the quality of semiconductor crystal near the gate (base) electrode, and improve controllability and control of the transistor structure.
The purpose of this invention is to obtain a transparent base transistor suitable for formation with good reproducibility.
この発明に係る透過ベーストランジスタは、半絶縁性半
導体層内部にその厚さ方向と垂直にソース、ドレイン用
ｎ−層を配列して配置するとともに、該両ｎ゛層間にグ
レーティング状のゲート電極を配置して、動作電流が水
平方向に、つまり基板厚さ方向と垂直な方向に流れるよ
うにしたものである。The transparent base transistor according to the present invention has n-layers for source and drain arranged vertically to the thickness direction inside a semi-insulating semiconductor layer, and a gate electrode in the form of a grating between the n-layers. They are arranged so that the operating current flows horizontally, that is, in a direction perpendicular to the substrate thickness direction.
この発明においては、動作電流（チャネル電流）が基板
厚さ方向と垂直な方向に流れるよう、ソース、ドレイン
層及びゲート電極を配設したから、縦型ＰＢＴ構造のよ
うにゲート電極上にエピタキシャル成長層を設けること
なく、チャネル層を形成することができ、このためゲー
ト電極近傍のエピタキシャル成長チャネル層の結晶性の
劣化を防止することができる。In this invention, since the source, drain layer, and gate electrode are arranged so that the operating current (channel current) flows in a direction perpendicular to the substrate thickness direction, an epitaxial growth layer is formed on the gate electrode as in the vertical PBT structure. The channel layer can be formed without providing a gate electrode, and therefore, deterioration of the crystallinity of the epitaxially grown channel layer in the vicinity of the gate electrode can be prevented.
またドレイン層とゲート電極とは所定距離を離して水平
方向に配列されているため、縦型ＰＢＴのようにゲート
電極とドレイン電極を縦方ｌに分離する必要がなく、ゲ
ート電極とドレイン電極との分離不良をなくすことがで
き、この結果トランジスタの性能を向上し、またその不
良発生率を低減することができる。In addition, since the drain layer and gate electrode are arranged horizontally with a predetermined distance apart, there is no need to separate the gate electrode and drain electrode vertically as in vertical PBT, and the gate electrode and drain electrode As a result, the performance of the transistor can be improved and the failure rate can be reduced.
［実施例］ 以下、この発明の実施例を図について説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施例による透過ベーストランジ
スタを説明するための図であり、第１図（ａ）は該透過
ベーストランジスタの平面パターン構造図、第１図（ｂ
）はチャネル方向と平行なｉｂ−Ｔｂ線断面の構造を示
す図、第１図（Ｃ）はチャネル方向と垂直なＩｃ−ｒｃ
線断面の構造を示す図である。図において、１００は不
純物濃度が１０′４〜１０”ｃｍ−″以下の半絶縁性Ｇ
ａＡｓ基板、３．４はそれぞれ該基板１００内部に対向
して配設されたソースｎ４形領域及びドレインｎ゛形領
域、２は該両ｎ゛形領域３，４間に埋め込まれ、金属あ
るいは低抵抗の半導体層−からなるフィンガー状ゲート
（ベース）埋め込み電極である。また５、６は上記ソー
ス、ドレイン領域３，４上に形成されたソース、ドレイ
ン電極、７は基板１上に形成され、上記ゲート埋め込み
電極２と接続されたゲート引き出し電極で、その隣接す
る埋め込み電極２相互間部分にば該電極４と基板１とが
接触しないよう空隙８が形成されているが、この空隙８
は必ずしも必要ではない。FIG. 1 is a diagram for explaining a transparent base transistor according to an embodiment of the present invention, FIG. 1(a) is a planar pattern structure diagram of the transparent base transistor, and FIG.
) is a diagram showing the structure of the ib-Tb line cross section parallel to the channel direction, and Figure 1 (C) is a diagram showing the structure of the Ic-rc line perpendicular to the channel direction.
It is a figure showing the structure of a line cross section. In the figure, 100 is a semi-insulating G with an impurity concentration of 10'4 to 10"cm-" or less.
an aAs substrate, 3.4 is a source n4 type region and a drain n' type region which are respectively disposed facing each other inside the substrate 100; 2 is buried between both n' type regions 3 and 4; This is a finger-shaped gate (base) embedded electrode made of a resistive semiconductor layer. Further, 5 and 6 are source and drain electrodes formed on the source and drain regions 3 and 4, and 7 is a gate extraction electrode formed on the substrate 1 and connected to the gate buried electrode 2, and the adjacent buried A gap 8 is formed between the electrodes 2 so that the electrode 4 and the substrate 1 do not come into contact with each other.
is not necessarily necessary.
ここでゲート埋め込み電極２はソース・ドレイン領域の
長手方向に沿って０．１〜１０μｍ程度の間隔をおいて
、数百μｍ以上の長さに渡って配列されており、そのゲ
ート長（りは０．１μｍ（１０００人）より小さくなっ
ている。またソース ドレイン電極層３，４の深さは、
その駆動電流が通常の縦方向構造のＰＢＴのものに匹敵
するよう数μｍ以上としている。Here, the gate buried electrodes 2 are arranged along the longitudinal direction of the source/drain region at intervals of approximately 0.1 to 10 μm and have a length of several hundred μm or more. The depth of the source and drain electrode layers 3 and 4 is smaller than 0.1 μm (1000 people).
The driving current is several μm or more so that it is comparable to that of a normal vertically structured PBT.
本実施例のＰ Ｂ Ｔ構造においても主な動作は従来の
Ｐ １３ Ｔと同様であるが、チャネル電流がソースｎ
゛層３−ドレインｎ”層４間を基板厚さ方向と垂直な方
向に流れる点が異なる。The main operation of the P B T structure of this example is the same as that of the conventional P 13 T, but the channel current is
The difference is that the current flows between the layer 3 and the drain n'' layer 4 in a direction perpendicular to the thickness direction of the substrate.
次に本実施例の透過ベーストランジスタの製造方法につ
いて第３図を用いて説明する。Next, a method for manufacturing the transparent base transistor of this example will be explained using FIG.
まず、半絶縁性Ｇ ａ Ａ、 ｓ基板１００全面に第１
の絶縁層を形成し、第１のレジスト膜９によりパターン
ニングしてソース、ドレインｎ゛層形成用の絶縁膜パタ
ーン１０を形成する。ここでの該パターン１０の幅はソ
ース・ドレインｎ゛形層３４の間隔が０．１μｍ以下程
度となるよう設定する（第３図（ａ））。First, a first layer is applied to the entire surface of the semi-insulating GaA,s substrate 100.
An insulating layer is formed and patterned using a first resist film 9 to form an insulating film pattern 10 for forming the source and drain n' layers. The width of the pattern 10 is set so that the interval between the source/drain n-type layers 34 is approximately 0.1 μm or less (FIG. 3(a)).
次に前記絶縁膜パターン１０をマスクにＧａ△Ｓ基板１
００を選択的に数μｍ以上エツチングする（第３図〔ｂ
））。その後エツチング掘り込み部分Ｉａ内にソース・
ドレインｎ“層３，４をエピタキシャル成長しく第３図
（Ｃ））、続いて上記絶縁膜パターン１０とは異種の第
２の絶縁膜１２を全面に形成しく第３図（ｄ））、パタ
ーン１０を除去して該絶縁膜１２を該ｎ゛エピタキシャ
ル層３．４上に選択的にかつセルファライン的に残す。Next, using the insulating film pattern 10 as a mask, the GaΔS substrate 1 is
00 is selectively etched several μm or more (Fig. 3 [b
)). Afterwards, place the source inside the etched portion Ia.
The drain n'' layers 3 and 4 are epitaxially grown (FIG. 3(C)), and then a second insulating film 12 of a different type from the insulating film pattern 10 is formed on the entire surface (FIG. 3(d)), pattern 10. is removed to leave the insulating film 12 selectively and in a self-aligned manner on the n' epitaxial layer 3.4.
このように−旦絶縁膜パターン１０を除去した後、上記
第２の絶縁膜１２上にもう一度絶縁膜パターン１０と同
種の第３の絶縁膜２０を形成しく第３図（ｅ））、該絶
縁膜２０をエッチパックしてｎ゛エピタキシヤル層３４
上の絶縁膜１２側壁にサイドウオール１０ａを残し、該
サイドウオール１０ａ間に幅０．１μｍ以下のＧａＡｓ
表面露出部１ｂをセルファライン的に形成する。その後
、第２のレジスト膜１３の形成１パターンニングを行っ
て、この露出部１ｂにこれより大きい開口１３ａを形成
する（第３図（ｆ））。このレジスト膜１３のパターン
は第３図（ｉ）に示すように空隙８を形成するための空
隙用パターン部１３ｂが形成されている。In this way, after removing the insulating film pattern 10, a third insulating film 20 of the same type as the insulating film pattern 10 is again formed on the second insulating film 12 (FIG. 3(e)). Etch-pack the film 20 to form an epitaxial layer 34.
A side wall 10a is left on the side wall of the upper insulating film 12, and a GaAs layer with a width of 0.1 μm or less is left between the side walls 10a.
The surface exposed portion 1b is formed in a self-aligned manner. Thereafter, the second resist film 13 is patterned to form a larger opening 13a in the exposed portion 1b (FIG. 3(f)). The pattern of this resist film 13 has a gap pattern portion 13b for forming the gap 8, as shown in FIG. 3(i).
ざらにゲーＩ〜埋め込み用の領域であるＧａＡｓ露出部
分１ｂをエツチングして深さ数μｍ以上のエツチング掘
込み部ＩＣを形成し、該堀込み部ＩＣにエビクキシャル
成長５スパッタあるいは茎着等によりゲー１− （ベー
ス）金属１５を選択的に埋め込む。その後、続けてゲー
ト引出し電極用金属７をレジスト膜１３をマスクとして
スバンタあるいは蒸着により形成しく第３図（ｇ））、
最後に第２の絶縁膜１２及びサイドウオール２０ａを除
去した後、ソース・ドレイン電極５，６を蒸着により形
成する（第３図０１））。The GaAs exposed portion 1b, which is the region for embedding the gate I, is roughly etched to form an etched trench IC with a depth of several μm or more, and a gate is formed on the trench IC by evixaxial growth 5 sputtering or stem adhesion. 1- Selectively embed (base) metal 15. Thereafter, the metal 7 for the gate lead-out electrode is formed by svanta or vapor deposition using the resist film 13 as a mask (FIG. 3(g)).
Finally, after removing the second insulating film 12 and the sidewall 20a, source/drain electrodes 5, 6 are formed by vapor deposition (FIG. 3, 01)).
このように本実施例のＰＢＴでは、従来の縦型ＰＢＴと
比べて、チャネル電流が基板厚さ方向と平行となるよう
ソース、トレイン領域３．４及びゲート埋め込み電極２
を配置した点以外に木質的な差はないが、このような配
置としたことにより、デー１〜埋め込み電極２を基板１
００の堀込み溝内に形成することが可能となり、つまり
チャネル層としてゲート埋め込み電極上のエビタギシャ
ル層ではなく半絶縁性バルク結晶基板を用いることがＯ
でき、ゲート上にエピタキシャル成長を行ってチャネル
層を形成する必要がなくなる。この結果ゲート付近の結
晶性の悪化の問題はなくなり、エピタキシャル成長によ
る特性劣化をなくして、より高性能なＰＢＴ、即ち高耐
圧化、あるいはバリステインク伝導が生じやすい等の性
能の得られるＰＢＴを実現することができる。In this way, in the PBT of this example, compared to the conventional vertical PBT, the source, train region 3.4, and gate buried electrode 2 are arranged so that the channel current is parallel to the substrate thickness direction.
There is no difference in the quality of the wood other than the placement of
In other words, it is possible to use a semi-insulating bulk crystal substrate as the channel layer instead of the epitaxial layer on the gate buried electrode, and the channel layer can be formed by epitaxial growth on the gate. No need to form. As a result, the problem of deterioration of crystallinity near the gate is eliminated, and characteristic deterioration due to epitaxial growth is eliminated, thereby realizing a PBT with higher performance, that is, a PBT with performance such as high breakdown voltage or varistain ink conduction easily occurring. I can do it.
またドレイン層とゲート電極とは所定距離を離して水平
方向に配列されているため、ゲート電極とドレイン電極
の分離不良を回避することができ、ＰＢＴ構造作製の各
種制御性を向上させることができる。In addition, since the drain layer and the gate electrode are arranged horizontally with a predetermined distance apart, it is possible to avoid poor separation between the gate electrode and the drain electrode, and it is possible to improve various controllability of PBT structure fabrication. .
さらに横型構造なので、ＦＥＴプロセスとの整合が可能
で、ｒ Ｃ上でＦＥＴと共存できる可能性が高いという
効果がある。Furthermore, since it has a horizontal structure, it can be matched with the FET process, and there is a high possibility that it can coexist with the FET on the rC.
なお、上記実施例では、ゲーＩ〜埋め込み金属を形成し
た後ゲート引出し電極を形成したが、ゲート引出し電極
はゲート埋め込み金属の形成の際、これと同時にエピタ
キシャル成長により形成してもよい。またトランジスタ
を構成する基板はＧａＡｓに限らず、他の高移動度を有
するＩ［ｌ−Ｖ系化合物（ＩｎＰ、ＩｎＧａＡ、ｓ等）
、あるいはＳｉを用いてもよく、さらにトランジスタを
構成する半導体層として上記基板の代わりに該基板上に
形成した不純物濃度が１０１４ｃｍ−３以下と小さいエ
ビタギシャル層を用いてもよい。In the above embodiment, the gate extraction electrode was formed after forming the gate I to the buried metal, but the gate extraction electrode may be formed by epitaxial growth at the same time as the formation of the gate buried metal. In addition, the substrate constituting the transistor is not limited to GaAs, but may also be made of other high-mobility I[l-V compounds (InP, InGaA, s, etc.).
Alternatively, Si may be used, and furthermore, an epitaxial layer formed on the substrate and having a small impurity concentration of 10<14>cm<-3> or less may be used instead of the above-mentioned substrate as the semiconductor layer constituting the transistor.
さらにまたソース・ドレイン層及びゲートの平面配置パ
ターンは第１図（Ａ）に示すものに限るものではなく、
例えば第４図に示すようにこれらを同軸上に配置しても
よい。第４図において４，３はそれぞれ同軸状に半絶縁
性半導体基板１００内に配置されたドレイン及びソース
ｎ゛形領域、２は該両領域間にこれらの領域に沿って配
列されたゲート埋め込み電極、５，６はそれぞれソース
、ドレイン電極であり、この場合も」−記実施例と同様
な効果がある。Furthermore, the planar arrangement pattern of the source/drain layer and the gate is not limited to that shown in FIG. 1(A).
For example, as shown in FIG. 4, these may be arranged coaxially. In FIG. 4, 4 and 3 are drain and source n-type regions arranged coaxially within the semi-insulating semiconductor substrate 100, respectively, and 2 is a gate buried electrode arranged between these regions along these regions. , 5 and 6 are source and drain electrodes, respectively, and in this case as well, the same effect as in the embodiment described above can be obtained.
以上のように、この発明に係る透過トランジスタによれ
ば、動作電流、つまりチャネル電流が基板厚さ方向に対
して垂直な方向に流れるよう、ソ一ス、ドレイン層及び
ゲート電極を配設したので、ゲート（ベース）埋め込み
電極上へのチャネル層のエピタキシャル成長を不要とで
き、これによりチャネル層の結晶特性の劣化を回避でき
、高耐圧でパリスティック伝導性に優れた、より高性能
なＰＢＴが実現できる効果がある。As described above, according to the transparent transistor according to the present invention, the source, drain layer, and gate electrode are arranged so that the operating current, that is, the channel current, flows in a direction perpendicular to the substrate thickness direction. This eliminates the need for epitaxial growth of the channel layer on the buried gate (base) electrode, thereby avoiding deterioration of the crystalline properties of the channel layer, resulting in a higher performance PBT with high withstand voltage and excellent pallitic conductivity. There is an effect that can be done.
第１図はこの発明の一実施例による横型Ｐ’ＢＴを説明
するだめの図、第２図は従来のＰＢＴ構造を示す図、第
３図は本発明の横型ＰＢＴの製造方法をその工程順に示
す断面図、第４図は本発明の他の実施例による横型ＰＢ
Ｔを示す図である。
１００・・・半絶縁性ＧａＡｓ基板、■・・・チャネル
層、２・・・ゲート（ベース）埋め込み電極、３・・・
ソース用ｎ°層、４・・・ドレイン用ｎ゛層、５・・・
ソース電極、６・・・トレイン電極、７・・・ゲート（
ベース）引き出し電極、８・・・空隙、９．１３・・・
第１．第２のレジスト膜、ＩＯ・・・絶縁膜パターン、
１２．２０・・・第２．第３の絶縁膜、１３・・・レジ
スト、２０ａ・・・サイドウオール。
なお図中同一符号は同−又は相当部分を示す。
■
Ｎ （”：
＼ｊ
○
平成
１年ｔＯ月、ｊＯ口
許
庁
長
官
殿
■。
事件の表示
特願平 １−１１７６９４号
発明の名称
透過・＼−ストランシスタ
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号住所
大阪市淀用区宮原４丁１１１番４５号
５、補正の対象
明細書の発明の詳細な説明の欄、及び図面の簡単な説明
の欄
６、補正の内容
（１）明細書第３頁第２０行〜第４頁第１行の［ＧａＡ
ｓ等の〜化合物半導体では］を１キヤリア（電子）の平
均自由行程長と同程度になってくることにより」に訂正
する。
（２）同第６頁第１１行の「ゲート電極と」を「第１に
ゲート電極と」に訂正する。
（３） 同第６頁第１４行の「ことができる。」の後
に以下の文章を挿入する。
「第２に電極所要面積が小さくできるので、集積化に有
利である。」
（４）同第７頁第１４行の「該電極４」を「該電極３．
４」に訂正する。
（５）同第８頁第１６行の「０．１μｍ」を「１．０μ
ｍ」に訂正する。
（６）同第９頁第１２行のｒｌｏａＪをｒ２０ａＪに訂
正する。
（７）同第１０頁第５行の１金属１５」を「金属２」に
訂正する。
（８）同第１１頁第９行の「ゲート電極」を１従来の縦
方向ＰＢＴ構造において懸念されたエビ層垂直方向に発
生するゲート電極」に訂正する。
（９） 同第１１頁第１０行の「ドレイン電極」を１
ソース、ドレイン電極」に訂正する。
００）同第１２頁第１８行〜第１９行の「透過トランジ
スタ」を「透過ベーストランジスタ」に訂正する。
００ 同第１３頁第１９行の１１３・・・レジスト、」
を削除する。
以 上FIG. 1 is a diagram for explaining a horizontal P'BT according to an embodiment of the present invention, FIG. 2 is a diagram showing a conventional PBT structure, and FIG. 3 is a diagram showing the manufacturing method of a horizontal PBT according to the present invention in the order of steps. The cross-sectional view shown in FIG. 4 is a horizontal PB according to another embodiment of the present invention.
It is a figure showing T. 100... Semi-insulating GaAs substrate, ■... Channel layer, 2... Gate (base) buried electrode, 3...
n° layer for source, 4... n' layer for drain, 5...
Source electrode, 6... Train electrode, 7... Gate (
base) extraction electrode, 8... void, 9.13...
1st. second resist film, IO...insulating film pattern,
12.20...Second. Third insulating film, 13...resist, 20a...side wall. Note that the same reference numerals in the figures indicate the same or equivalent parts. ■ N (”: \j ○ Month tO, 1999, Mr. JO Commissioner of the Office of the Complainant ■. Display of the case Patent application No. 1-117694 Transparency of the name of the invention \- Transistor 3, relationship with the amended person case Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Address: 4-111-45-5 Miyahara, Yodoyo-ku, Osaka Explanation column 6, Contents of amendment (1) [GaA
In compound semiconductors such as (2) On page 6, line 11, "with the gate electrode" is corrected to "first with the gate electrode." (3) Insert the following sentence after "It is possible." on page 6, line 14. "Secondly, the required area of the electrode can be reduced, which is advantageous for integration." (4) "The electrode 4" on page 7, line 14 of the same page is replaced with "the electrode 3.
Corrected to 4. (5) “0.1μm” on page 8, line 16 of the same page was changed to “1.0μm”.
Correct it to "m". (6) Correct rloaJ on page 9, line 12 to r20aJ. (7) "1 Metal 15" on page 10, line 5 is corrected to "Metal 2." (8) "Gate electrode" in line 9 of page 11 has been corrected to 1. Gate electrode generated in the vertical direction of the shrimp layer, which was a concern in the conventional vertical PBT structure. (9) “Drain electrode” on page 11, line 10
Corrected to ``source and drain electrodes''. 00) Correct "transparent transistor" in lines 18 to 19 of page 12 to "transparent base transistor". 00 Page 13, line 19, 113...Regist.''
Delete. that's all
Claims (1)
ス領域及びドレイン領域と、該両領域間に配置され、電
流貫通開口を持つゲート電極とを有し、チャネル電流が
上記ゲート電極を貫通して流れる透過ベーストランジス
タにおいて、 上記チャネル電流の方向が基板厚さ方向と垂直となるよ
う、ソース、ドレイン領域及びゲート電極を配列したこ
とを特徴とする透過ベーストランジスタ。(1) It has a source region and a drain region disposed facing each other inside a semi-insulating semiconductor layer, and a gate electrode disposed between the two regions and having a current through opening, and a channel current flows through the gate electrode. A transparent base transistor in which a source, a drain region, and a gate electrode are arranged such that the direction of the channel current is perpendicular to the thickness direction of the substrate.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1117694A JPH02296372A (en) | 1989-05-10 | 1989-05-10 | Transmissive base transistor |
| US07/463,478 US5057883A (en) | 1989-05-10 | 1990-01-11 | Permeable base transistor with gate fingers |
| DE4015067A DE4015067C2 (en) | 1989-05-10 | 1990-05-10 | Transistor with a permeable base |
| FR909005819A FR2646963B1 (en) | 1989-05-10 | 1990-05-10 | STRUCTURE OF A PERMEABLE-BASED TRANSISTOR AND MANUFACTURING METHOD THEREOF |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1117694A JPH02296372A (en) | 1989-05-10 | 1989-05-10 | Transmissive base transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02296372A true JPH02296372A (en) | 1990-12-06 |
Family
ID=14717988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1117694A Pending JPH02296372A (en) | 1989-05-10 | 1989-05-10 | Transmissive base transistor |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5057883A (en) |
| JP (1) | JPH02296372A (en) |
| DE (1) | DE4015067C2 (en) |
| FR (1) | FR2646963B1 (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04223342A (en) * | 1990-12-26 | 1992-08-13 | Mitsubishi Electric Corp | Gate electrode of semiconductor device and manufacture thereof |
| JPH0575139A (en) * | 1991-09-12 | 1993-03-26 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| DE4311388B4 (en) * | 1993-04-07 | 2005-07-28 | Forschungszentrum Jülich GmbH | Layer system with electrically activatable layer |
| JP2713205B2 (en) * | 1995-02-21 | 1998-02-16 | 日本電気株式会社 | Semiconductor device |
| US5828101A (en) * | 1995-03-30 | 1998-10-27 | Kabushiki Kaisha Toshiba | Three-terminal semiconductor device and related semiconductor devices |
| US6919592B2 (en) | 2001-07-25 | 2005-07-19 | Nantero, Inc. | Electromechanical memory array using nanotube ribbons and method for making same |
| US7259410B2 (en) | 2001-07-25 | 2007-08-21 | Nantero, Inc. | Devices having horizontally-disposed nanofabric articles and methods of making the same |
| US6911682B2 (en) | 2001-12-28 | 2005-06-28 | Nantero, Inc. | Electromechanical three-trace junction devices |
| US6924538B2 (en) | 2001-07-25 | 2005-08-02 | Nantero, Inc. | Devices having vertically-disposed nanofabric articles and methods of making the same |
| US6835591B2 (en) | 2001-07-25 | 2004-12-28 | Nantero, Inc. | Methods of nanotube films and articles |
| US6643165B2 (en) | 2001-07-25 | 2003-11-04 | Nantero, Inc. | Electromechanical memory having cell selection circuitry constructed with nanotube technology |
| US7566478B2 (en) | 2001-07-25 | 2009-07-28 | Nantero, Inc. | Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles |
| US6706402B2 (en) | 2001-07-25 | 2004-03-16 | Nantero, Inc. | Nanotube films and articles |
| US6574130B2 (en) | 2001-07-25 | 2003-06-03 | Nantero, Inc. | Hybrid circuit having nanotube electromechanical memory |
| US7176505B2 (en) | 2001-12-28 | 2007-02-13 | Nantero, Inc. | Electromechanical three-trace junction devices |
| US6784028B2 (en) | 2001-12-28 | 2004-08-31 | Nantero, Inc. | Methods of making electromechanical three-trace junction devices |
| US7335395B2 (en) | 2002-04-23 | 2008-02-26 | Nantero, Inc. | Methods of using pre-formed nanotubes to make carbon nanotube films, layers, fabrics, ribbons, elements and articles |
| US6759693B2 (en) | 2002-06-19 | 2004-07-06 | Nantero, Inc. | Nanotube permeable base transistor |
| US6774052B2 (en) * | 2002-06-19 | 2004-08-10 | Nantero, Inc. | Method of making nanotube permeable base transistor |
| US7560136B2 (en) | 2003-01-13 | 2009-07-14 | Nantero, Inc. | Methods of using thin metal layers to make carbon nanotube films, layers, fabrics, ribbons, elements and articles |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4463366A (en) * | 1980-06-20 | 1984-07-31 | Nippon Telegraph & Telephone Public Corp. | Field effect transistor with combination Schottky-junction gate |
| FR2501913A1 (en) * | 1981-03-10 | 1982-09-17 | Thomson Csf | PLANAR TYPE FIELD EFFECT TRANSISTOR COMPRISING METALLIZED WELL ELECTRODES AND METHOD OF MANUFACTURING THE TRANSISTOR |
| US4583107A (en) * | 1983-08-15 | 1986-04-15 | Westinghouse Electric Corp. | Castellated gate field effect transistor |
| JPS622666A (en) * | 1985-06-28 | 1987-01-08 | Matsushita Electric Ind Co Ltd | Field effect transistor |
| US4724223A (en) * | 1986-12-11 | 1988-02-09 | Gte Laboratories Incorporated | Method of making electrical contacts |
-
1989
- 1989-05-10 JP JP1117694A patent/JPH02296372A/en active Pending
-
1990
- 1990-01-11 US US07/463,478 patent/US5057883A/en not_active Expired - Fee Related
- 1990-05-10 DE DE4015067A patent/DE4015067C2/en not_active Expired - Fee Related
- 1990-05-10 FR FR909005819A patent/FR2646963B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE4015067C2 (en) | 1994-06-09 |
| FR2646963B1 (en) | 1992-05-15 |
| DE4015067A1 (en) | 1990-11-22 |
| FR2646963A1 (en) | 1990-11-16 |
| US5057883A (en) | 1991-10-15 |
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