JPH02295133A - Crystal structure and manufacture thereof - Google Patents
Crystal structure and manufacture thereofInfo
- Publication number
- JPH02295133A JPH02295133A JP11492889A JP11492889A JPH02295133A JP H02295133 A JPH02295133 A JP H02295133A JP 11492889 A JP11492889 A JP 11492889A JP 11492889 A JP11492889 A JP 11492889A JP H02295133 A JPH02295133 A JP H02295133A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ingaas
- growth
- doped
- crystal structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000013078 crystal Substances 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 239000000872 buffer Substances 0.000 claims abstract description 31
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 240000002329 Inga feuillei Species 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 241000239290 Araneae Species 0.000 description 1
- 239000006173 Good's buffer Substances 0.000 description 1
- -1 are n Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置における基板と半導体層との間に挟
まれた緩衝層から形成される結晶構造及びその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a crystal structure formed from a buffer layer sandwiched between a substrate and a semiconductor layer in a semiconductor device, and a method for manufacturing the same.
従来から，基板と半導体層の間に緩衝層を導入し、半導
体装置の特性向上を計る方法は広く知られている．特に
、基板と半導体層の格子定数に大きな違いがある場合は
緩衝層の効果により，半導体層の結晶性、電気的特性、
光学的特性が著しく異なるため、種々の緩衝層が検討さ
れてきた．最近では、薄膜形成技術の向上により、歪超
格子が緩衝層として利用され、半導体装置の特性改善に
寄与している。歪超格子緩衝層は、ジャパニーズ、ジャ
ーナル・オブ・アプライド・ブイジツクス，ボリューム
２６， （１９８７年）第エルｌ９５０頁からエルｌ９
５２頁（Ｊｐｎ．Ｊ．Ａｐｐｌ．ｐｈｙｓ．ｖｏ１．２
６（１９８７）ｐｐＬ１９５０−Ｌ１９５２）において
論じられている。Conventionally, it is widely known that a buffer layer is introduced between a substrate and a semiconductor layer to improve the characteristics of a semiconductor device. In particular, when there is a large difference in lattice constant between the substrate and the semiconductor layer, the effect of the buffer layer may affect the crystallinity, electrical properties, etc. of the semiconductor layer.
Various buffer layers have been investigated because their optical properties are significantly different. Recently, with improvements in thin film formation technology, strained superlattices are being used as buffer layers, contributing to improving the characteristics of semiconductor devices. The strained superlattice buffer layer is described in Japanese Journal of Applied Physics, Volume 26, (1987) No. 1950 to 19
52 pages (Jpn.J.Appl.phys.vol.2
6 (1987) ppL1950-L1952).
また，ＧａＡｓ層上にＩｎｘＧａｔ−ｘＡｓ層を成長し
た構造において、Ｉｎ組成Ｘが０．５以上になると両半
導体層の界面付近に発生していた転位が界面付近約３０
０人に閉じ込められ、上の層には伝播しないという報告
がある．これは電子情報通信学会研究技術報告、イーデ
イ−８７ − １２３（１９８’／年）第８５頁から９
０頁（信技報， Ｅ Ｄ８７−１２３ （１９８７）ｐ
ｐ８５−９０）において論じられている．
〔発明が解決しようとする課題〕
上記従来技術で記載されているＩｎ組成０．５以上のＩ
ｎＧａＡｓ層を緩衝層として用いることを試みた．Ｇａ
Ａｓ基板上に． ＩｎＧａＡｓ層を３００人以上形成し
、その上にｎ型ＩｎＡ Ｑ Ａｓ層を電子供給層として
形成した．この場合、ＧａＡｓとＩｎＧａＡｇ界面に発
生した転位は界面近傍３００人以内のＩｎＧａＡｓ層に
閉じ込められるため、その上のＩｎＧａＡｇ層、ｉｎＡ
ｊｌ Ａｓ層は転位における結晶性の劣化は受けない
．しかし、この構造における電子移動度は約５００００
ｌ＃／Ｖ・Ｓであった．この値は予測される移動度の半
分の値である．
本発明の目的は、ＩｎＧａＡｓ緩衡層の形成方法を改善
することにより，高い電子移動度を持つ結晶構造を得る
ことにある．
また，上記従来技術で緩衝層として用いられている歪超
格子は熱や応力に弱いという欠点がある。Furthermore, in a structure in which an InxGat-xAs layer is grown on a GaAs layer, when the In composition
There are reports that it is confined to 0 people and does not spread to upper layers. This is the Institute of Electronics, Information and Communication Engineers Research and Technical Report, E.D.-87-123 (198'/year), pages 85 to 9.
p. 0 (Shin Giho, E D87-123 (1987) p.
Discussed on pages 85-90). [Problem to be solved by the invention] I of the In composition described in the above-mentioned prior art is 0.5 or more.
An attempt was made to use an nGaAs layer as a buffer layer. Ga
on the As substrate. More than 300 InGaAs layers were formed, and an n-type InA Q As layer was formed thereon as an electron supply layer. In this case, dislocations generated at the interface between GaAs and InGaAg are confined in the InGaAs layer within 300 layers near the interface, so the dislocations generated at the interface between GaAs and InGaAg are
jl The crystallinity of the As layer does not suffer from deterioration due to dislocations. However, the electron mobility in this structure is about 50,000
It was l#/V・S. This value is half the predicted mobility. An object of the present invention is to obtain a crystal structure with high electron mobility by improving the method for forming an InGaAs buffer layer. Furthermore, the strained superlattice used as a buffer layer in the above-mentioned prior art has the disadvantage of being susceptible to heat and stress.
本発明の他の目的は、熱、応力に強い半導体結晶構造お
よびその製造方法を提供することにある．〔課題を解決
するための手段〕
上記目的を達成するために、本発明においてはＩｎＧａ
Ａｇ緩衝層を形成する際に、ＩｎＧａＡｓ層内に欠陥が
閉じ込められる膜厚数１００人の１ｎＧａＡｓ層を形成
した後，成長を一時中断し，その後，ＩｎＧａＡｓ層を
再び成長し、緩衡層を形成したものである。Another object of the present invention is to provide a semiconductor crystal structure that is resistant to heat and stress, and a method for manufacturing the same. [Means for solving the problem] In order to achieve the above object, the present invention uses InGa
When forming the Ag buffer layer, after forming a 1nGaAs layer with a thickness of several hundred layers in which defects are confined within the InGaAs layer, the growth is temporarily interrupted, and then the InGaAs layer is grown again to form a buffer layer. This is what I did.
上記他の目的を達成するために，緩衝層として転位の発
生している層を用いたものである。In order to achieve the other objects mentioned above, a layer in which dislocations occur is used as a buffer layer.
欠陥の閉じ込めが完了したと観察される膜厚以上で、緩
衝層の成長を一時中断することにより、中断表面上で緩
衝層を構成している原子、例えば、ＩｎＧａＡｓではＩ
ｎ，Ｇａ，Ａｓがエネルギ的に安定な位置に移動するこ
とができ、欠陥の閉じ込めがより完壁になる．それによ
って、その上に形成した緩衝層への転位伝播の抑制が強
められ，更にその上に形成される半導体層の結晶性の向
上が計られる．
緩衝層として１ｎＧａＡｓ．電子供給層としてｎ型ｌｎ
Ａ Ｑ Ａｓ層を持つ構造の電子移動度はｌ００００ａ
Ｊ ／ Ｖ・Ｓを示し、従来の２倍高い値となる．また
、転位は格子歪みが緩和された後に発生するため、転位
の発住している緩衝層は熱や応力に対しても強い．
さらに，転位発生により緩衝層は高抵抗となるため，基
板とその上に形成された半導体層との電気的遮断効果を
示す．それによって、漏れ電流低減等，この構造を持っ
た半導体装置の特性向上を計ることができる．
〔実施例〕
以下、本発明の一実施例を第１図により説明する．
半絶縁性ＧａＡｓ基板ｌ上にノンドープＧａＡｓ層２ノ
ンドープＩｎＧａＡｓ層３、ノンドープＩｎＡ Ｑ Ａ
ｓスペーサ層４，ｎ型１ｎＡ Ｑ Ａｓ電子供給層５、
ｎ型１ｎＧａＡｓキャップ層６を順次形成する．本実施
例では分子線エビタキシャル成長法（ＭＢＥ法）を用い
て、半導体層を形成する．上記のような構造を形成後，
キャップ層６の一部をエッチングにより除去し、ゲート
電極７を形成する。その後、キャップ層６上にソース・
ドレイン電極８を形成する．本実施例ではＩｎＧａＡｓ
層３が緩衝層の役目を果たしているａｌｎ組成０．５
以上、膜厚を５００人以上とするが、ＩｎＧａＡｓ層を
３００〜５００人形成した後に、成長を一時中断し，５
秒〜３分後に成長を再開し、所定の膜厚のＩｎＧａＡｓ
層３を成長する．ここでは、Ｉｎ組成０．８，膜厚１０
００人とした．スペーサ層４の厚さは０〜１５０人とす
る。By temporarily suspending the growth of the buffer layer above the film thickness at which defect confinement is observed, atoms constituting the buffer layer on the suspended surface, such as I in InGaAs, are
n, Ga, and As can be moved to energetically stable positions, and defects can be more completely confined. This strengthens the suppression of dislocation propagation to the buffer layer formed above it, and further improves the crystallinity of the semiconductor layer formed above it. As a buffer layer, 1nGaAs. n-type ln as electron supply layer
A Q The electron mobility of the structure with As layer is l0000a
J/V・S, which is twice as high as the conventional value. Furthermore, because dislocations occur after lattice strain is relaxed, the buffer layer in which dislocations reside is resistant to heat and stress. Furthermore, the buffer layer has a high resistance due to the generation of dislocations, and thus exhibits an electrically blocking effect between the substrate and the semiconductor layer formed on it. By doing so, it is possible to improve the characteristics of semiconductor devices with this structure, such as reducing leakage current. [Example] An example of the present invention will be described below with reference to FIG. Non-doped GaAs layer 2, non-doped InGaAs layer 3, non-doped InA Q A on semi-insulating GaAs substrate 1
s spacer layer 4, n-type 1nA Q As electron supply layer 5,
An n-type 1nGaAs cap layer 6 is sequentially formed. In this example, a semiconductor layer is formed using molecular beam epitaxial growth (MBE). After forming the above structure,
A portion of the cap layer 6 is removed by etching to form a gate electrode 7. After that, the source layer is placed on the cap layer 6.
Form the drain electrode 8. In this example, InGaAs
Aln composition 0.5 with layer 3 serving as a buffer layer
In the above, the film thickness is set to 500 layers or more, but after 300 to 500 layers of InGaAs are formed, the growth is temporarily interrupted, and
After a few seconds to 3 minutes, the growth is resumed and the InGaAs film is grown to a predetermined thickness.
Grow layer 3. Here, In composition is 0.8, film thickness is 10
00 people. The thickness of the spacer layer 4 is set to 0 to 150 layers.
電子供給層５はドナ不純物ＳｉをＩＸ１０１”（ｃｌｍ
−’）程度含有し，その厚さは１００〜５００人である
。キャップ層６はＳｊを３Ｘ１０”δ（ａｍ−’）程度
含有する。Ｉ ｎ Ｇ ａ Ａ ｓ層：３とスベーサ層
３との界面近傍に電子が蕎積され、電子走行層７として
働く．
格子定数の異なる半導体層を積み重ねた場合，上部の半
導体層はある膜厚（臨界膜厚）以内であると半導体層が
歪むことにより、転位の発生が抑えられる．この臨界膜
厚は格子定数の差の程度に依存し、ｌｎＧａＡｓの場合
、Ｉｎの組成に依存する．第２図に， （ｉａＡｓ上に
ｌｎＧａＡｓを形成した場合のＩｎ組成と臨界膜厚の依
存性を実線で示す．この図から明らかなように、転位無
しに利用できるｌｎＧａＡｓ層の膜厚（斜ｍ）は制限さ
れる．臨界膜厚以上のｌｎＧａＡｓ層内では転位が発生
することになる．第３図は上記の様子を模式的に示した
半導体層の界而付近の断面図である．ここで，半導体層
１１はＧａＡｓ、半導体層１２はＩｎＧａＡｓである．
，１マスが１格子を表わしている．転位は半導体層１１
と１２の格子定数の差が大きいと界面付近に閉じ込めら
れ、上層へ伝播しない．この状況を第４図に模式的に示
す．互いに格子定数の違う半導体層２１，２２．２３を
積み重ねている．格子定数の違いにより、半導体層２２
中に転位が発生する．この際，格子定数の差が大きいと
転位は半導体層２２の厚さが数１００人内に閉じ込めら
れ，更に一時成長中断を行なうと、閉じ込めの効果が顕
著になる．この時、半導体層２２は多量の転位の発生に
より多結晶的になっているが、この上に形成される半導
体Ｍ２３はエビタキシャル成長する．そこで第２図中の
破線Ｌより上の領域のＬ ｎ Ｇａ Ａ ｓ層を成長中
断を含む製造方法により、形成すればＩｎＧａＡｓ層は
良好な緩衝層として働《。The electron supply layer 5 is made of donor impurity Si with IX101'' (clm
-'), and its thickness is 100 to 500 people. The cap layer 6 contains about 3×10”δ (am−′) of Sj. Electrons are accumulated near the interface between the InGaAs layer 3 and the sublayer 3, and it functions as the electron transit layer 7. When semiconductor layers with different constants are stacked, if the thickness of the upper semiconductor layer is within a certain thickness (critical thickness), the semiconductor layer will be distorted and the generation of dislocations will be suppressed.This critical thickness is determined by the difference in lattice constants. In the case of lnGaAs, it depends on the In composition. In Figure 2, the dependence of In composition and critical film thickness when lnGaAs is formed on iaAs is shown by a solid line. As such, the thickness (oblique m) of the lnGaAs layer that can be used without dislocations is limited.Dislocations will occur in the lnGaAs layer with a thickness greater than the critical thickness.Figure 3 schematically shows the above situation. 2 is a cross-sectional view of the semiconductor layer shown in FIG. 1. Here, the semiconductor layer 11 is made of GaAs, and the semiconductor layer 12 is made of InGaAs.
, one square represents one grid. Dislocations occur in the semiconductor layer 11
If the difference between the lattice constants of and 12 is large, it will be confined near the interface and will not propagate to the upper layers. This situation is schematically shown in Figure 4. Semiconductor layers 21, 22, and 23 with mutually different lattice constants are stacked. Due to the difference in lattice constant, the semiconductor layer 22
Dislocations occur inside. At this time, if the difference in lattice constant is large, dislocations will be confined within the thickness of the semiconductor layer 22 of several hundred layers, and if the growth is further temporarily interrupted, the effect of confinement will become noticeable. At this time, the semiconductor layer 22 has become polycrystalline due to the generation of a large amount of dislocations, but the semiconductor M23 formed thereon grows epitaxially. Therefore, if the LnGaAs layer in the region above the broken line L in FIG. 2 is formed by a manufacturing method that includes interruption of growth, the InGaAs layer will function as a good buffer layer.
本発明ではこの半導体層２２を緩衝層として使う．実施
例１ではＩｎＧａＡｓ層２がこの役割を果しでいる．こ
の手法を採用することにより、基板ＧａＡｓと電子走行
層との間に格ｔ定数の差がある場合も、劣化の少ない電
子走行層を形成することかできる，また，緩衝層は高抵
抗であるため、基抜と屯子走行層との電気的遮断の役割
を果す．このため、漏れ電流を低減できる．
次に本発明を用いた別の実施例を第５図により説明する
．半絶縁性ＧａＡｓ基板３１上に、ノンドーブＧａＡｓ
層３２，ノンドープｌｎＧａＡｓ層３３，ｎ型ＩｎＧａ
Ａｓ能動層；３４、ノンドープＩ．ｎＡ Ｑ Ａｓ ７
９４ ３ ５を順次形成する．本実施例ではＭＢＥ法を
用いて、半導体層を形成する．上記のような構造を形成
後，ｌｎＡ Ｑ Ａｓ層；３５を一部を残してエッチン
グにより除去し、ゲート電極３６を形成する．その後、
能動層３ ４−１；にンース・ドレイン電極３７を形成
する．
ここでは、ｌｎＧａＡｓ層３３が緩衝層の役目を果たし
ている．Ｉｎ組成，膜厚，製造方法は実施例１と同様と
した，ここでは、能動層３４のＩｎ組成はＩｎＧａＡｓ
層コ３３と同様とし、その）績さはｉｏｏｏ人以上とし
た．この層は、ドナ不純物ＳｉをＩ×１ ０”〜Ｉ Ｘ
１ ０ｌ８Ｃ！１″″８含有しテイる．実施例』，２
にボした結晶横造は，通常、ＩｎＧａＡｓおよびｆｎＡ
Ｑ Ａｓ層の組成を限定し、ＩｎＰ基板上に格子整合
させ、形成している．本発明を用いれば安価でプロセス
の確立しているＧａＡｓ基板を用いて同構造の半導体装
置を製造できる。In the present invention, this semiconductor layer 22 is used as a buffer layer. In Example 1, the InGaAs layer 2 fulfills this role. By adopting this method, even if there is a difference in the t-constant between the GaAs substrate and the electron transport layer, it is possible to form an electron transport layer with little deterioration, and the buffer layer has a high resistance. Therefore, it plays the role of electrically interrupting the foundation and the tunnel running layer. Therefore, leakage current can be reduced. Next, another embodiment using the present invention will be explained with reference to FIG. On the semi-insulating GaAs substrate 31, non-doped GaAs
Layer 32, non-doped InGaAs layer 33, n-type InGa
As active layer; 34, non-doped I. nA Q As 7
Form 94 3 5 in sequence. In this example, a semiconductor layer is formed using the MBE method. After forming the structure as described above, the lnA Q As layer 35 is removed by etching leaving only a portion, and a gate electrode 36 is formed. after that,
Form a source/drain electrode 37 on active layer 3 4-1; Here, the lnGaAs layer 33 serves as a buffer layer. The In composition, film thickness, and manufacturing method were the same as in Example 1. Here, the In composition of the active layer 34 was InGaAs.
It is the same as layer 33, and its performance is set to be iooo people or higher. This layer contains the donor impurity Si from I×10” to I
1 0l8C! Contains 1″″8. Example”, 2
Bottled crystal horizontal structures are usually used for InGaAs and fnA
The Q As layer is formed by limiting its composition and lattice-matching it on the InP substrate. According to the present invention, a semiconductor device having the same structure can be manufactured using a GaAs substrate which is inexpensive and has an established process.
本発明は、以上説明したように構成されているので以下
に記載されているような効果を奏する。Since the present invention is configured as described above, it produces the effects described below.
１１衝層の導入により、緩衝層内に転位が閉じ込められ
るため，その上層に格子定数が下層と異なる結晶性のよ
いエビタキシャル成長ができる．また、転位の発生によ
り緩衝層は高抵抗となるため、基板と上部の半導体層の
間で優れた電気的遮断効果を示し、漏れ屯流を低減でき
る，11 The introduction of a buffer layer confines dislocations within the buffer layer, allowing epitaxial growth with good crystallinity in the upper layer, where the lattice constant is different from the lower layer. In addition, since the buffer layer has high resistance due to the occurrence of dislocations, it exhibits an excellent electrical isolation effect between the substrate and the upper semiconductor layer, and can reduce leakage current.
第１図は本発明の実施例１の半導体装置の縦断面図，第
２図はＣ； ａ Ａ ｓ基板］一におけるｌｎＧａＡｓ
層のＩｎ組成と臨界腺厚の関係曲線図，第３図は半趨体
層界面での転位発生機構を説明するための結晶格子の模
式断血図，第４図は転位発生層を持つ半導体層の模式的
所而図，第５図は本発明の実施例２の半４体装置の縦断
面図である。
１・・・半絶縁性（；ａＡｓ基扱、２・・・ノンドーブ
ｆｊａＡｓ層、３・・・ノンドープｉｎｆｉａＡｓ層、
４・・・ノントーブｌｎＡ Ｑ Ａｓ層、５ − ｎ型
１ｎＡ Ｑ Ａｓ［、６ − ｎ型ＩｎＧａＡｓ層，７
・・・ゲート電極，８・・・リース・ドレイン電極，１
１．１２・・・半導体層、２１．２３・・・半導体エビ
タキシャル層，２２・・・転位の発生している半導体層
、３１・・・半絶縁性ＧａＡｓ基板，３２・・・ノンド
ープＧａＡｓ層、３ ３ ・・・ノンドープｌｎＧａＡ
ｓ層，３４・・・ｎ型１ｎＧａＡｓ層、３ ５−・・ノ
ンドープＩｎＡ Ｑ Ａｓ層、３ Ｂ ・・・ゲート電
極、３７・・・リース・ドレイン電極．１蜘阻氏FIG. 1 is a vertical cross-sectional view of a semiconductor device according to Example 1 of the present invention, and FIG.
A curve diagram showing the relationship between the In composition of the layer and the critical thickness. Figure 3 is a schematic cross-section diagram of a crystal lattice to explain the mechanism of dislocation generation at the interface between half-layers. Figure 4 is a diagram of a semiconductor with a dislocation generation layer. FIG. 5, which is a schematic diagram of the layers, is a longitudinal sectional view of a half-four body device according to a second embodiment of the present invention. 1... Semi-insulating (; aAs-based treatment, 2... Non-doped fjaAs layer, 3... Non-doped infiaAs layer,
4...Nontobu lnA Q As layer, 5 - n-type 1nA Q As [, 6 - n-type InGaAs layer, 7
... Gate electrode, 8 ... Lease/drain electrode, 1
1.12...Semiconductor layer, 21.23...Semiconductor epitaxial layer, 22...Semiconductor layer in which dislocations have occurred, 31...Semi-insulating GaAs substrate, 32...Non-doped GaAs layer , 3 3 ... non-doped lnGaA
s layer, 34... n-type 1nGaAs layer, 3 5-... non-doped InA Q As layer, 3 B... gate electrode, 37... lease/drain electrode. Mr. 1 Spider
Claims (1)
層、ノンドープＩｎＡｌＡｓスペーサ層、ｎ型ＩｎＡｌ
Ａｓ電子供給層、ｎ型ＩｎＧａＡｓキャップ層を順次形
成した結晶構造において、上記ノンドープのＩｎＧａＡ
ｓ層を緩衝層としてＩｎ組成を０．５以上、膜厚を５０
０Å以上としたことを特徴とする結晶構造。 ２、半絶縁性ＧａＡｓ基板上にノンドープＩｎＧａＡ＿
８層、ｎ型ＩｎＧａＡｓ層、ノンドープＩｎＡｌＡｓ層
を順次形成した結晶構造において、ノンドープのｌｎＧ
ａＡｓ層を緩衝層としてＩｎ組成を０．５以上、膜厚を
５００Å以上としたことを特徴とする結晶構造。 ３、請求項１、２記載の結晶構造において、基板上に第
１のＩｎＧａＡｓ層を３００〜５００Å形成した後に、
成長を一時中断し、５秒〜３分後に成長を再開し、所定
の膜厚のＩｎＧａＡｓ層を成長し、その後、順次ノンド
ープＩｎＡｌＡｓ、ｎ型ＩｎＡｌＡｓ、ｎ型ＩｎＧａＡ
ｓ半導体層を形成することを特徴とする結晶構造の製造
方法。[Claims] 1. Non-doped InGaAs on a semi-insulating GaAs substrate
layer, undoped InAlAs spacer layer, n-type InAl
In the crystal structure in which an As electron supply layer and an n-type InGaAs cap layer are sequentially formed, the above-mentioned non-doped InGaA
The s layer is used as a buffer layer, the In composition is 0.5 or more, and the film thickness is 50
A crystal structure characterized by having a thickness of 0 Å or more. 2. Non-doped InGaA on semi-insulating GaAs substrate
In a crystal structure in which 8 layers, an n-type InGaAs layer, and a non-doped InAlAs layer are sequentially formed, non-doped InG
A crystal structure characterized in that an aAs layer is used as a buffer layer, an In composition is 0.5 or more, and a film thickness is 500 Å or more. 3. In the crystal structure according to claims 1 and 2, after forming the first InGaAs layer with a thickness of 300 to 500 Å on the substrate,
The growth is temporarily interrupted and restarted after 5 seconds to 3 minutes to grow an InGaAs layer of a predetermined thickness, and then sequentially grow non-doped InAlAs, n-type InAlAs, and n-type InGaA.
1. A method for manufacturing a crystal structure, comprising forming a semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11492889A JPH02295133A (en) | 1989-05-10 | 1989-05-10 | Crystal structure and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11492889A JPH02295133A (en) | 1989-05-10 | 1989-05-10 | Crystal structure and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02295133A true JPH02295133A (en) | 1990-12-06 |
Family
ID=14650134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11492889A Pending JPH02295133A (en) | 1989-05-10 | 1989-05-10 | Crystal structure and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02295133A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018511945A (en) * | 2015-03-31 | 2018-04-26 | ソウル バイオシス カンパニー リミテッドＳｅｏｕｌ Ｖｉｏｓｙｓ Ｃｏ．，Ｌｔｄ． | UV light emitting element |
-
1989
- 1989-05-10 JP JP11492889A patent/JPH02295133A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018511945A (en) * | 2015-03-31 | 2018-04-26 | ソウル バイオシス カンパニー リミテッドＳｅｏｕｌ Ｖｉｏｓｙｓ Ｃｏ．，Ｌｔｄ． | UV light emitting element |
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