JPH02294059A - Ic package - Google Patents

Ic package

Info

Publication number
JPH02294059A
JPH02294059A JP11570589A JP11570589A JPH02294059A JP H02294059 A JPH02294059 A JP H02294059A JP 11570589 A JP11570589 A JP 11570589A JP 11570589 A JP11570589 A JP 11570589A JP H02294059 A JPH02294059 A JP H02294059A
Authority
JP
Japan
Prior art keywords
contact
contacts
lead
package
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11570589A
Other languages
Japanese (ja)
Inventor
Shoichi Kawahara
河原　章一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP11570589A priority Critical patent/JPH02294059A/en
Publication of JPH02294059A publication Critical patent/JPH02294059A/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of current leak and crosstalk by providing each lead with a plurality of pads for contact. CONSTITUTION:Each IC lead 2 is provided with a plurality of pads 3, 4 for contact. As a result, when measuring contacts come into contact with contact parts 5 at the time of testing electric characteristics, the intervals between contacts can be made wide. Hence mutual interference between the contacts and difficulty of contact arrangement can be avoided even in the case of narrow intervals between the IC leads 2. Thereby, the generation of current leak and crosstalk can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＩＣパッケージに関し、特にそのリードの構
造に関する． 〔従来の技術〕 従来のＩＣパッケージは、第４図に示すように、各ＩＣ
リード２に１個のタイパー６を有するだけの構造となっ
ていた． 〔発明が解決しようとする課題〕 上述した従来のＩＣパッケージのリードは、第４図に示
すようにタイパー６が１つしかない構造であった．この
ため電気特性試験において，測定用接触子はタイパー６
に対し第５図に示すように一列に配列されるが、ＩＣリ
ード２の間隔が狭くなると、接触子同志が干渉し、接触
子の配列が非常に難しくなったり、電気的にも電流リー
クやクロストーク等の発生もあるという欠点があった。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IC package, and particularly to the structure of its leads. [Prior art] As shown in Fig. 4, in a conventional IC package, each IC
The structure was such that lead 2 had only one typer 6. [Problems to be Solved by the Invention] The conventional IC package lead described above had a structure in which there was only one tieper 6, as shown in FIG. For this reason, in electrical property tests, the measurement contact is typer 6.
However, as the spacing between the IC leads 2 becomes narrower, the contacts interfere with each other, making it very difficult to arrange the contacts, and electrically causing current leakage. There is also a drawback that crosstalk etc. may occur.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、複数のリードを有するＩＣパッケージにおい
て、各リードに複数の電気特性試験コタクト用パッドを
設けたことを特徴とする．〔実施例〕 次に、本発明について図面を参照して説明する．第１図
は本発明の第１の実施例を示す図である．本実施例では
ＩＣパッケージ１より出ている各ＩＣリード２に対しコ
ンタクト用パッド３，４を設けてある． このようなＩＣパッケージにＩＣを組込んだ後の電気特
性試験時には第２図に斜線で示す接触子コンタクト部５
を測定用接触子がコンタクトする。The present invention is characterized in that, in an IC package having a plurality of leads, each lead is provided with a plurality of contact pads for electrical property testing. [Example] Next, the present invention will be explained with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of the present invention. In this embodiment, contact pads 3 and 4 are provided for each IC lead 2 protruding from the IC package 1. When testing electrical characteristics after incorporating an IC into such an IC package, the contact portion 5 shown by diagonal lines in FIG.
The measurement contact makes contact.

第３図は本発明の第２の実施例を示す図である．本実施
例では複数設けられたコンタクトパッド３．４は、隣ど
うし干渉しないようにジグザグにレイアウトされている
。この実施例ではジグザグにレイアウトされるコンタク
トパッド３，４に対し、電気特性試験用接触子間も同様
にジグザグにレイアウトし、接触子間も広くとることが
でき、接触子に付加する抵抗．コンデンサ等の電気部品
が容易に取り付けることができるという利点がある。FIG. 3 is a diagram showing a second embodiment of the present invention. In this embodiment, a plurality of contact pads 3.4 are laid out in a zigzag pattern so as not to interfere with each other. In this embodiment, while the contact pads 3 and 4 are laid out in a zigzag pattern, the contact pads for electrical property testing are also laid out in a zigzag pattern, allowing for a wide gap between the contacts and the resistance added to the contacts. It has the advantage that electrical parts such as capacitors can be easily attached.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＩＣパッケージの各リー
ドにコンタクト用パッドを複数設けることにより、ＩＣ
リード間間隔が狭くかつ縮少化するＩＣリードに対し、
電気特性試験用の接触子同志の間隔を広くとることが可
能となり、電流リーク，クロストークなどの発生を減少
させる効果がある．As explained above, the present invention provides a plurality of contact pads on each lead of an IC package.
For IC leads whose inter-lead spacing is narrow and shrinking,
This allows for wider spacing between contacts for electrical property testing, which has the effect of reducing current leakage, crosstalk, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例を示す平面図、第２図は
第１の実施例のＩＣリードに対し電気特性試験のための
接触子のコンタクト位置を説明するための図、第３図は
本発明の第２の実施例を示す平面図、第４図は従来のＩ
Ｃパッケージを示す平面図、第５図は従来のＩＣパッケ
ージに対し、電気特性試験のための接触子のコンタクト
位置を説明するための図である。 １・・・ＩＣパッケージ、２・・・ＩＣリード、３．４
・・・コンタクトパッド、５・・・電気特性試験用接触
子のコンタクト部、６・・・タイバーFIG. 1 is a plan view showing the first embodiment of the present invention, FIG. 3 is a plan view showing a second embodiment of the present invention, and FIG. 4 is a plan view showing a conventional I
FIG. 5, which is a plan view showing the C package, is a diagram for explaining the contact positions of the contacts for electrical characteristic testing with respect to the conventional IC package. 1...IC package, 2...IC lead, 3.4
...Contact pad, 5...Contact part of electrical property test contact, 6...Tie bar

Claims (1)

【特許請求の範囲】[Claims] 　複数のリードを有するＩＣパッケージにおいて、各リ
ードに複数の電気特性試験コンタクト用パッドを設けた
ことを特徴とするＩＣパッケージ。An IC package having a plurality of leads, characterized in that each lead is provided with a plurality of electrical property test contact pads.
JP11570589A 1989-05-08 1989-05-08 Ic package Pending JPH02294059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11570589A JPH02294059A (en) 1989-05-08 1989-05-08 Ic package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11570589A JPH02294059A (en) 1989-05-08 1989-05-08 Ic package

Publications (1)

Publication Number Publication Date
JPH02294059A true JPH02294059A (en) 1990-12-05

Family

ID=14669177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11570589A Pending JPH02294059A (en) 1989-05-08 1989-05-08 Ic package

Country Status (1)

Country Link
JP (1) JPH02294059A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475259A (en) * 1991-10-17 1995-12-12 Fujitsu Limited Semiconductor device and carrier for carrying semiconductor device
JPH08204112A (en) * 1995-01-30 1996-08-09 Nec Corp Manufacture of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475259A (en) * 1991-10-17 1995-12-12 Fujitsu Limited Semiconductor device and carrier for carrying semiconductor device
US5637923A (en) * 1991-10-17 1997-06-10 Fujitsu Limited Semiconductor device, carrier for carrying semiconductor device
US5666064A (en) * 1991-10-17 1997-09-09 Fujitsu Limited Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device
US5736428A (en) * 1991-10-17 1998-04-07 Fujitsu Limited Process for manufacturing a semiconductor device having a stepped encapsulated package
US5750421A (en) * 1991-10-17 1998-05-12 Fujitsu Limited Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device
JPH08204112A (en) * 1995-01-30 1996-08-09 Nec Corp Manufacture of semiconductor device

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