JPH0229110A - Switched capacitor filter device - Google Patents
Switched capacitor filter deviceInfo
- Publication number
- JPH0229110A JPH0229110A JP17954088A JP17954088A JPH0229110A JP H0229110 A JPH0229110 A JP H0229110A JP 17954088 A JP17954088 A JP 17954088A JP 17954088 A JP17954088 A JP 17954088A JP H0229110 A JPH0229110 A JP H0229110A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frequency divider
- frequency
- scf
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 6
- 239000000203 mixture Substances 0.000 abstract 1
- 238000004965 Hartree-Fock calculation Methods 0.000 description 31
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 1
Landscapes
- Filters That Use Time-Delay Elements (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、モデム、音声合成装置等の信号処理装置に利
用されるスイッチトキャパシタフィルタ（以下、ＳＣＦ
と略す）装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to switched capacitor filters (hereinafter referred to as SCFs) used in signal processing devices such as modems and voice synthesizers.
(abbreviated as ) device.
従来の技術
１つのＳＣＦで多種類の帯域をもつフィルタを作成する
場合、各帯域に応じたＳＣＦ駆動用クロック信号を発生
させる分周器を具備し、これを選択する方式が用いられ
てきた。2. Description of the Related Art When creating a filter having multiple types of bands using one SCF, a method has been used in which a frequency divider is provided to generate a clock signal for driving the SCF according to each band, and a frequency divider is selected.
以下に従来のＳＣＦ装置について説明する。A conventional SCF device will be explained below.
第２図は、従来の分周装置の構成図であり、１９は外部
装置、２０は基本クロック信号線、２１はＳＣＦ駆動用
クロック信号発生器、２２は分周器Ａ、２３は基本クロ
ック信号を分周器Ａで分周された分周信号線、２４は分
周器Ｂ、２５は基本クロック信号を分局器Ｂで分周され
た分周信号線、２６は分周器Ｃ１２７は基本クロック信
号を分周器Ｃで分周された分周信号線、２８は分周信号
のいづれかを選択する選択制御信号線、２９は選択制御
信号により分周信号を選択する分周信号選択装置、３０
はＳＣＦ駆動用クロック信号線、３１はＳＣＦである。FIG. 2 is a configuration diagram of a conventional frequency dividing device, in which 19 is an external device, 20 is a basic clock signal line, 21 is an SCF driving clock signal generator, 22 is a frequency divider A, and 23 is a basic clock signal. 24 is the frequency divider B, 25 is the frequency divided signal line where the basic clock signal is divided by the divider B, 26 is the frequency divider C127 is the basic clock A frequency division signal line whose frequency is divided by the frequency divider C, 28 a selection control signal line for selecting one of the frequency division signals, 29 a frequency division signal selection device for selecting a frequency division signal by the selection control signal, 30
31 is an SCF driving clock signal line, and 31 is an SCF.
つぎに、このＳＣＦ装置の動作をのべる。Next, the operation of this SCF device will be described.
外部装置１９から信号線２０を通じて基本りロック信号
がＳＣＦ駆動用クロック信号発生器２１に入力され、分
周器Ａ２２１分周器Ｂ２４゜分周器Ｃ２６から、各信号
線２３．２５．２７に、各々、分周信号を発生する。こ
れらを分周信号選択装置２９に入力し、外部装置１９か
ら出力された選択制御信号を信号線２８により与えて、
所望の分周信号を選択し、それをＳＣＦ駆動用クロック
信号として信号線３０に出力する。これを５ＣＦ３１に
入力し、必要とする帯域をもつフィルタを形成する。A basic lock signal is input from the external device 19 to the SCF driving clock signal generator 21 through the signal line 20, and from the frequency divider A 221, the frequency divider B 24°, and the frequency divider C26, to each signal line 23, 25, 27, Each generates a frequency-divided signal. These are input to the frequency division signal selection device 29, and the selection control signal output from the external device 19 is given through the signal line 28,
A desired frequency-divided signal is selected and outputted to the signal line 30 as an SCF driving clock signal. This is input to 5CF31 to form a filter with the required band.
発明が解決しようとする課題
しかしながら、上記従来の構成では、全ての分周器を同
時に動作させているため、常に全ての分周信号が分周信
号選択装置２９に入力される。このために、配線や電源
線において分周信号が相互干渉を生じ、高調波による干
渉雑音を発生する。Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, all the frequency dividers are operated at the same time, so all frequency-divided signals are always input to the frequency-divided signal selection device 29. For this reason, the frequency-divided signals cause mutual interference in wiring and power lines, and interference noise due to harmonics is generated.
この干渉雑音の周波数を王１としてお（と（１）式とな
る。Letting the frequency of this interference noise be 1, the equation (1) is obtained.
ｆ＋＝ｆｏ−ｎ （ｎ＝０．１，２．−）・・・・・
・（１）
（ｎ＝ｏ、 １．２． ・・・・・・）となる。f+=fo-n (n=0.1, 2.-)...
・(1) (n=o, 1.2. ...).
この干渉雑音は、ＳＣＦにおいても配線や電源線により
、ＳＣＦ中の信号線と結合し、雑音となり、信号に混入
し、信号対雑音比（以下、ＳＮ比と略する）を低下させ
るという問題点を有していた。This interference noise also combines with the signal line in the SCF through wiring and power lines, becomes noise, mixes into the signal, and reduces the signal-to-noise ratio (hereinafter abbreviated as SN ratio). It had
本発明は上記従来の問題点を解決するもので、分周信号
選択装置で選択されない分局信号を発生させる分周器を
停止することにより、干渉雑音を低減しＳＣＦのＳＮ比
を向上させることのできるＳＣＦ装置を提供するもので
ある。The present invention solves the above-mentioned conventional problems, and reduces interference noise and improves the SNR of SCF by stopping the frequency divider that generates the divided signals that are not selected by the divided signal selection device. The purpose is to provide an SCF device that can.
課題を解決するための手段
この目的を達成するために、本発明のＳＣＦ装置は、Ｓ
ＣＦ駆動用クロック信号発生器内部に外部装置からの制
御信号により、必要とする分周信号を発生する分周器以
外の分周器を停止させる停止制御装置を備えた構成にな
っている。Means for Solving the Problems To achieve this object, the SCF device of the present invention
The CF drive clock signal generator is provided with a stop control device that stops frequency dividers other than the frequency divider that generates the required frequency division signal in response to a control signal from an external device.
作用
この構成により１つのＳＣＦで多種類の帯域を持つフィ
ルタを形成することのできるＳＣＦ装置の干渉雑音を低
減し、ＳＮ比を向上させることができる。Effect: With this configuration, it is possible to reduce interference noise and improve the S/N ratio of an SCF device that can form a filter with multiple types of bands using one SCF.
実施例
以下本発明の一実施例について図面を参照しながら説明
する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例におけるＳＣＦ装置の構成図
を示すものである。FIG. 1 shows a configuration diagram of an SCF device in an embodiment of the present invention.
第１図において、１は分周器を停止させる制御信号を発
生する停止制御装置、２は同停止制御装置を制御するた
めの制御信号線、３．４．５は各分周器Ａ、Ｂ、Ｃを停
止するための信号を送る各信号線である。なお、６は外
部装置、７は基本クロック信号線、８はＳＣＦ駆動用ク
ロック信号発生器、９は分周器Ａ、１ｏは分周器Ａから
の信号線、１１は分周器Ｂ、１２は同分周器Ｂからの信
号線、１３は分周器Ｃ１１４は同分周器Ｃからの信号線
、１５は分周信号選択装置、１６は選択制御信号線、１
７はＳＣＦ駆動用クロック信号線、１８はＳＣＦであり
、これらは従来例の構成と同じである。In FIG. 1, 1 is a stop control device that generates a control signal to stop the frequency divider, 2 is a control signal line for controlling the stop control device, and 3.4.5 is each frequency divider A, B. , C are each signal line that sends a signal to stop. In addition, 6 is an external device, 7 is a basic clock signal line, 8 is a clock signal generator for driving the SCF, 9 is a frequency divider A, 1o is a signal line from the frequency divider A, 11 is a frequency divider B, 12 13 is a signal line from the same frequency divider B, 13 is a frequency divider C114 is a signal line from the same frequency divider C, 15 is a frequency division signal selection device, 16 is a selection control signal line, 1
Reference numeral 7 indicates a clock signal line for driving the SCF, and reference numeral 18 indicates an SCF, which have the same configuration as the conventional example.
まず、外部装置６から信号線７に出力される基本クロッ
ク信号は、ＳＣＦ駆動用クロック信号発生器８の内部の
各分周器９，１１．１２に入力される。この時、外部装
置６から信号線２に出力される制御信号により、ＳＣＦ
駆動用クロック信号発生器９の内部に備えられた停止制
御装置１が、各分周器を停止させるための停止信号を信
号線３．４．５のいずれかに出力し、この停止信号を受
けた分周器は停止する。分周信号選択装置１５は、外部
装置６から出力された選択制御信号線１６の信号により
、必要とする分周信号を選択し、ＳＣＦ駆動用クロック
信号を信号線出力する。このＳＣＦ駆動用クロック信号
１６は５ＣＦ１７に入力し、必要とする帯域を持つフィ
ルタを形成する。First, a basic clock signal outputted from the external device 6 to the signal line 7 is inputted to each frequency divider 9, 11.12 inside the SCF driving clock signal generator 8. At this time, a control signal output from the external device 6 to the signal line 2 causes the SCF to
A stop control device 1 provided inside the driving clock signal generator 9 outputs a stop signal for stopping each frequency divider to one of the signal lines 3.4.5, and receives this stop signal. The frequency divider is stopped. The frequency division signal selection device 15 selects a necessary frequency division signal based on the signal on the selection control signal line 16 output from the external device 6, and outputs the SCF driving clock signal to the signal line. This SCF driving clock signal 16 is input to the 5CF 17 to form a filter having the required band.
以上のように、本実施例によれば、分周信号選択装置１
５に入力される分周信号は必要とする帯域を持つフィル
タを形成するための分周信号だけに限られる。このこと
により、分周信号選択装置１５中で発生する干渉雑音の
中に、他の分周器による信号が混在することはなくなり
、雑音レベルを最低限に押えることができる。たとえば
、前述した例を用い分周信号Ａのみを選択した場合、干
渉雑音は発生せず式（３）に示す分周信号Ａの周波数ｆ
Ａの高調波成分のみとなる。As described above, according to this embodiment, the frequency-divided signal selection device 1
The frequency-divided signals inputted to 5 are limited to those for forming a filter having the required band. This prevents signals from other frequency dividers from being mixed in the interference noise generated in the frequency-divided signal selection device 15, and the noise level can be kept to a minimum. For example, if only the frequency-divided signal A is selected using the example described above, no interference noise will occur and the frequency f of the frequency-divided signal A shown in equation (3)
Only the harmonic components of A are present.
ｆ＋＝２００−ｎ （ＫＨｚ）
（ｎ＝０．１，２．・・・・・・）・・・・・・（３）
これは（２）式で算出した干渉雑音成分と比較しても十
分低減されており、ＳＮ比が向上している。f+=200-n (KHz) (n=0.1, 2.....)...(3)
This is sufficiently reduced compared to the interference noise component calculated using equation (2), and the S/N ratio is improved.
なお、本実施例では分周器を３個用意したが、一般的に
は分周器は２個以上でも良い。また、停止させる分周器
は用意した分周器の個数以内であれば゛良く、より多く
の不必要な分周器を停止させておくほどＳＮ比は向上す
る。In this embodiment, three frequency dividers are provided, but in general, two or more frequency dividers may be used. Further, it is sufficient that the number of frequency dividers to be stopped is within the number of prepared frequency dividers, and the more unnecessary frequency dividers are stopped, the better the SN ratio is.
発明の効果
本発明によれば、ＳＣＦ駆動用クロック信号発生器内に
分周器を停止させる停止制御装置を設けることにより、
分周信号選択装置内で発生する干渉雑音を低下させ、Ｓ
ＣＦ装置をＳＮ比を向上させるという効果を得ることが
できる優れたＳＣＦ装置を実現できるものである。Effects of the Invention According to the present invention, by providing a stop control device in the SCF driving clock signal generator to stop the frequency divider,
Reduces interference noise generated within the frequency-divided signal selection device,
It is possible to realize an excellent SCF device that can obtain the effect of improving the SN ratio of the CF device.
第１図は本発明の一実施例におけるＳＣＦ装置の構成図
、第２図は従来のＳＣＦ装置の構成図である。
１・・・・・・停止制御装置、２・・・・・・制御信号
線、３・・・・・・分周器Ａの停止信号線、４・・・・
・・分周器Ｂの停止信号線、５・・・・・・分周器Ｃの
停止信号線、６・・・・・・外部装置、７・・・・・・
基本クロック信号線、８・・・・・・ＳＣＦ駆動用クロ
ック信号発生器、９・・・・・・分周器Ａ、１０・・・
・・・分周信号線、１１・・・・・・分周器Ｂ、１２・
・・・・・分周信号線、１３・・・・・・分周器Ｃ１１
４・・・・・・分周信号線、１５・・・・・・分周信号
選択装置、１６・・・・・・選択制御信号線、１７・・
・・・・ＳＣＦ駆動用クロック信号線、１８・・・・・
・ＳＣＦ。
代理人の氏名 弁理士 粟野重孝 ほか１名Ｉｌ１図FIG. 1 is a block diagram of an SCF device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional SCF device. 1... Stop control device, 2... Control signal line, 3... Stop signal line of frequency divider A, 4...
...Stop signal line of frequency divider B, 5...Stop signal line of frequency divider C, 6...External device, 7...
Basic clock signal line, 8... SCF driving clock signal generator, 9... Frequency divider A, 10...
...Frequency division signal line, 11... Frequency divider B, 12.
...Frequency division signal line, 13... Frequency divider C11
4... Frequency division signal line, 15... Frequency division signal selection device, 16... Selection control signal line, 17...
...SCF drive clock signal line, 18...
・SCF. Name of agent: Patent attorney Shigetaka Awano and one other person
Claims (1)
数の分周器と前記分周器の分周信号を外部装置からの選
択制御信号により選択する分周信号選択装置と所望する
分周信号を発生する分周器以外の分周器を外部装置から
の停止制御信号により停止する停止制御装置と分周信号
選択装置から出力されるスイッチトキャパシタフィルタ
駆動用クロック信号により動作するスイッチトキャパシ
タフィルタとを備えたことを特徴とするスイッチトキャ
パシタフィルタ装置。A plurality of frequency dividers that frequency divide a basic clock signal input from an external device, a frequency division signal selection device that selects a frequency division signal of the frequency divider by a selection control signal from the external device, and a frequency division signal selection device that selects a desired frequency division signal. A stop control device that stops frequency dividers other than the generated frequency divider by a stop control signal from an external device, and a switched capacitor filter that operates by a switched capacitor filter driving clock signal output from a frequency division signal selection device. A switched capacitor filter device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17954088A JPH0229110A (en) | 1988-07-19 | 1988-07-19 | Switched capacitor filter device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17954088A JPH0229110A (en) | 1988-07-19 | 1988-07-19 | Switched capacitor filter device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0229110A true JPH0229110A (en) | 1990-01-31 |
Family
ID=16067538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17954088A Pending JPH0229110A (en) | 1988-07-19 | 1988-07-19 | Switched capacitor filter device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0229110A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04312014A (en) * | 1991-04-11 | 1992-11-04 | Matsushita Electric Ind Co Ltd | Switched capacitor filter and its circuit |
| US5460825A (en) * | 1990-05-23 | 1995-10-24 | Mcneil-Ppc, Inc. | Taste mask coatings for preparing chewable pharmaceutical tablets |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58105613A (en) * | 1981-12-17 | 1983-06-23 | Fujitsu Ltd | Switched capacitor filter for general use |
| JPS6318721A (en) * | 1986-07-11 | 1988-01-26 | Hitachi Ltd | Signal processing circuit |
| JPS6390910A (en) * | 1986-10-06 | 1988-04-21 | Seiko Epson Corp | Semiconductor integrated circuit |
-
1988
- 1988-07-19 JP JP17954088A patent/JPH0229110A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58105613A (en) * | 1981-12-17 | 1983-06-23 | Fujitsu Ltd | Switched capacitor filter for general use |
| JPS6318721A (en) * | 1986-07-11 | 1988-01-26 | Hitachi Ltd | Signal processing circuit |
| JPS6390910A (en) * | 1986-10-06 | 1988-04-21 | Seiko Epson Corp | Semiconductor integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5460825A (en) * | 1990-05-23 | 1995-10-24 | Mcneil-Ppc, Inc. | Taste mask coatings for preparing chewable pharmaceutical tablets |
| JPH04312014A (en) * | 1991-04-11 | 1992-11-04 | Matsushita Electric Ind Co Ltd | Switched capacitor filter and its circuit |
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