JPH02281622A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02281622A JPH02281622A JP10242089A JP10242089A JPH02281622A JP H02281622 A JPH02281622 A JP H02281622A JP 10242089 A JP10242089 A JP 10242089A JP 10242089 A JP10242089 A JP 10242089A JP H02281622 A JPH02281622 A JP H02281622A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- opening
- interlayer insulating
- deposited
- opening part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000010410 layer Substances 0.000 claims abstract description 53
- 239000011229 interlayer Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 238000004544 sputter deposition Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 13
- 230000008021 deposition Effects 0.000 abstract description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 abstract description 10
- 239000010937 tungsten Substances 0.000 abstract description 10
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052786 argon Inorganic materials 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 5
- -1 argon ions Chemical class 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 239000007789 gas Substances 0.000 description 9
- 238000001947 vapour-phase growth Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000006722 reduction reaction Methods 0.000 description 3
- ZMZGFLUUZLELNE-UHFFFAOYSA-N 2,3,5-triiodobenzoic acid Chemical compound OC(=O)C1=CC(I)=CC(I)=C1I ZMZGFLUUZLELNE-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に電極配線を
有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having electrode wiring.
従来の半導体装置は、半導体基板上に設けた半導体素子
領域に接続する電極配線を前記半導体素子領域上に設け
た層間絶縁膜に開口部を設けた後前記開口部を含む表面
に蒸着法やスパッタリング法等により堆積した導体層を
パターニングして形成する方法が一般的である。In a conventional semiconductor device, an electrode wiring connected to a semiconductor element region provided on a semiconductor substrate is formed by forming an opening in an interlayer insulating film provided on the semiconductor element region, and then applying vapor deposition or sputtering to the surface including the opening. A common method is to pattern a conductor layer deposited by a method or the like.
また、前記開口部に於ける電極配線の段差被覆性を向上
させる為、開口部側壁に傾斜を施したり、開口部上端の
みを広く開口する方法が採られている。すなわち、第２
図に示す様に、シリコン基板１の上にフィールド酸化膜
２を設けて素子形成領域を区画し、前記素子形成領域上
に設けた酸化膜上にゲート電極３ａ及び配線３ｂを設け
、ゲート電極３ａに整合して前記素子形成領域に不純物
拡散層４を形成した後、層間絶縁膜５を堆積し、層間絶
縁膜５の上にバターニングしたホトレジスト膜を設けて
前記ホトレジスト膜をマスクとして層間絶縁膜５を選択
的にエツチング除去して開口部６を設ける。この時、開
口部６の上端を大きく広げる為、まず、等方性のエツチ
ングにより層間絶縁膜らの半分の膜厚に相当する深さ迄
除去し、更に同一マスクで残りを異方性エツチングによ
り前記ホトレジスト膜パターン寸法どうりに垂直に開口
して盃状の開口部６を形成する。次に、開口部６を含む
表面に導電層７を堆積し、ホトレジスト膜をマスクに導
電層７を選択的にエツチング除去して不純物拡散層４及
び配線３ｂとコンタクトする配線パターンを形成する。In addition, in order to improve the coverage of the step of the electrode wiring in the opening, methods have been adopted in which the side walls of the opening are sloped or only the upper end of the opening is widened. That is, the second
As shown in the figure, a field oxide film 2 is provided on a silicon substrate 1 to demarcate an element formation area, a gate electrode 3a and a wiring 3b are provided on the oxide film provided on the element formation area, and a gate electrode 3a After forming an impurity diffusion layer 4 in the element formation region in accordance with the above, an interlayer insulating film 5 is deposited, a patterned photoresist film is provided on the interlayer insulating film 5, and the interlayer insulating film is formed using the photoresist film as a mask. 5 is selectively etched away to form an opening 6. At this time, in order to widen the upper end of the opening 6, first remove the interlayer insulating film to a depth equivalent to half the film thickness by isotropic etching, and then use the same mask to remove the remaining part by anisotropic etching. A cup-shaped opening 6 is formed by opening perpendicularly to the dimensions of the photoresist film pattern. Next, a conductive layer 7 is deposited on the surface including the opening 6, and is selectively etched away using the photoresist film as a mask to form a wiring pattern in contact with the impurity diffusion layer 4 and the wiring 3b.
しかしながら、回路の高集積化に伴うパターンの微細化
により、開口部６の径及びプロセスマージンａ、ｂは減
少しかつ配線の多層化の要求に応じて層間絶縁膜５が平
坦化されることにより開口部の深さは深くなる。したが
って、第３図に示す様に、開口部６は上端部を広げるこ
となく垂直な側壁を有する深い穴を形成することとなり
導体層７の充分な段差被覆性を得ることが困器となる。However, due to the miniaturization of patterns accompanying higher integration of circuits, the diameter of the opening 6 and the process margins a and b have decreased, and the interlayer insulating film 5 has been flattened in response to the demand for multilayer wiring. The depth of the opening becomes deeper. Therefore, as shown in FIG. 3, the opening 6 forms a deep hole with vertical side walls without widening the upper end, making it difficult to obtain sufficient level coverage of the conductor layer 7.
この問題を克服する為には開口部内部を配線材料で埋め
込む方法が用いられる。これには段差被覆性の良好な気
相成長法を用いて開口部の半径を超える膜厚の配線材を
堆積する方法が一般的である。In order to overcome this problem, a method is used in which the inside of the opening is filled with wiring material. A common method for this purpose is to deposit a wiring material with a thickness exceeding the radius of the opening using a vapor phase growth method that provides good step coverage.
上述した従来の半導体装置の製造方法は、段差被覆性の
良好な気相成長法を用いたとしても、開口部の深さが開
口部の径よりも大きい様な深い開口部の場合、開口部内
部への成長反応ガスの供給は不充分となり、したがって
、開口部の上部に対して底部の膜成長速度は遅くなり第
４図に示す様に開口部内部を埋め込んで導体層８が成長
する前に開口部上端がふさがってしまい、開口部内に空
洞９を生じてしまう。したがって、開口部内に於ける実
効的な電流容量が低下し、接続抵抗の増大やエレクトロ
マイグレーションよる断線等の不具合を生じるという欠
点がある。In the conventional semiconductor device manufacturing method described above, even if a vapor phase growth method with good step coverage is used, in the case of a deep opening where the depth of the opening is larger than the diameter of the opening, the opening The supply of the growth reaction gas to the inside becomes insufficient, and therefore the film growth rate at the bottom of the opening becomes slower than that at the top of the opening, and as shown in FIG. The upper end of the opening becomes blocked, creating a cavity 9 within the opening. Therefore, there is a drawback that the effective current capacity within the opening decreases, resulting in problems such as an increase in connection resistance and disconnection due to electromigration.
本発明の半導体装置の製造方法は、半導体素子領域を備
えた半導体基板上に層間絶縁層を設ける工程と、前記素
子領域上の前記層間絶縁層を選択的にエツチングして開
口部を設ける工程と、前記開口部内の側壁表面のみに第
１の導体層をバイアス・スパッタリング法により堆積す
る工程と、前記開口部を含む前記層間絶縁膜の表面に第
２の導体層を堆積する工程と、前記第２の導体層を選択
的にエツチングして前記開口部の素子領域とコンタクト
し且つ前記層間絶縁層上に延在する電極配線を形成する
工程とを含んで構成される。A method for manufacturing a semiconductor device according to the present invention includes a step of providing an interlayer insulating layer on a semiconductor substrate having a semiconductor element region, and a step of selectively etching the interlayer insulating layer on the element region to form an opening. , a step of depositing a first conductor layer only on the side wall surface in the opening by bias sputtering, a step of depositing a second conductor layer on the surface of the interlayer insulating film including the opening, and selectively etching the second conductor layer to form an electrode wiring that contacts the element region of the opening and extends on the interlayer insulating layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の一実施例を説明するた
め工程順に示した半導体チップの断面図である。FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
まず、第１図（ａ）に示すように、第２図の従来例と同
様の工程によりシリコン基板ｌの上に不純物拡散層４等
の素子領域を形成し、表面に層間絶縁膜５を１．５μｍ
の厚さに堆積した後、所望の位置に配線接続の為の１，
０μｍＸ１．Ｑμｍの断面積を有する開口部６を設ける
。この開口部６はＣＦ４系のプラズマガスを用いた異方
性エツチングで形成される。次に、アルゴンイオンによ
るバイアススパッタリング法を用いて硅化タングステン
層１０を堆積する。深い開口部６に対して通常のスパッ
タリング法による膜の堆積では所謂シャドウィング効果
により、開口部６の底の近傍での堆積速度が遅くなる。First, as shown in FIG. 1(a), an element region such as an impurity diffusion layer 4 is formed on a silicon substrate l by a process similar to that of the conventional example shown in FIG. .5μm
1, for wiring connections at desired locations after depositing to a thickness of
0μm×1. An opening 6 having a cross-sectional area of Qμm is provided. This opening 6 is formed by anisotropic etching using CF4-based plasma gas. Next, a tungsten silicide layer 10 is deposited using a bias sputtering method using argon ions. When a film is deposited in the deep opening 6 by the usual sputtering method, the deposition rate near the bottom of the opening 6 becomes slow due to the so-called shadowing effect.
そして開口部６の上端での堆積がすすむにつれてその効
果がさらに大きくなる。そこでスパッタリング時にシリ
コン基板１側にもバイアスを印加することにより、硅化
タングステン層１０の堆積と逆スパツタが同時に進行し
開口部６の上端での堆積速度を遅くする。これはスパッ
タイオンの入射角度が４５°近傍で最もスパッタ効率が
高いという原理によるもので、バイアスを制御すること
により開口部６の上端での堆積速度を零とし、深さ方向
に堆積速度を高くするとかできる。具体的にはアルゴン
ガス圧が０．５パスカル、硅化タングステン層１０のタ
ーゲット側電力密度が４〜６Ｗ／ｃｍ”、基板パイアス
が−２００〜−４００Ｖである。ここで、スパッタ開始
と同時に開口部６の側壁にのみ、堆積が進行するバイア
ス条件でスパッタを行うことも可能であるが、開口部の
拡散層表面をアルゴンイオンでアタックしない様に制御
することが困難である為、最初に一２００Ｖ程度のバイ
アスを印加し層間絶縁膜５の上にも薄く堆積させる条件
でスパッタし、層間絶縁膜５の上に０．１μｍ以下、開
口部の底部の側壁に０．２μｍ程度の厚さに堆積させる
。As the deposition progresses at the upper end of the opening 6, the effect becomes even greater. Therefore, by applying a bias to the silicon substrate 1 side during sputtering, the deposition of the tungsten silicide layer 10 and the reverse sputtering proceed simultaneously, thereby slowing down the deposition rate at the upper end of the opening 6. This is based on the principle that the sputtering efficiency is highest when the incident angle of sputtered ions is around 45 degrees, and by controlling the bias, the deposition rate at the upper end of the opening 6 is made zero, and the deposition rate is increased in the depth direction. You can do that. Specifically, the argon gas pressure is 0.5 Pascal, the power density on the target side of the tungsten silicide layer 10 is 4 to 6 W/cm'', and the substrate bias is -200 to -400V. It is also possible to perform sputtering under bias conditions that allow deposition to proceed only on the side walls of 6, but since it is difficult to control the surface of the diffusion layer in the opening so as not to attack it with argon ions, first Sputtering is performed under the conditions of applying a moderate bias to deposit a thin layer also on the interlayer insulating film 5, and depositing it to a thickness of 0.1 μm or less on the interlayer insulating film 5 and about 0.2 μm on the sidewall of the bottom of the opening. let
次に、第１図＜ｂ＞に示すように、バイアスを一４００
Ｖ程度に上げて層間絶縁膜５の上部で堆積よりも逆スパ
ツタ速度が速くなる条件とし、層間絶縁膜５の上部の硅
化タングステン層１０が無くなるまでバイアス・スパッ
タリングを行う。しかる後に気相成長法によりタングス
テン層１１を０．８μｍの厚さに堆積する。気相成長は
ＷＦ６ガスのＨ２還元反応によって行う。ＷＦ６ガスの
分圧は１〜３Ｘ １０−’Ｔ ｏ ｒ ｒ、 ）−タル
ガス圧が０．１〜０．２Ｔｏｒｒで成長温度は３５０℃
である。タングステン層１１の成長は全面で一様に進む
が開口部６の内部では硅化タングステン層１０によって
底部が狭くなっている為、底部より埋め込みながら成長
し０．５μｍの厚さに堆積した時点で開口部６内は完全
に埋め込まれた状態になる。さらに、０．３μｍの厚さ
に堆積してタングステン層１１の表面を平坦にする。次
に、ホトレジスト膜をマスクにタングステン層１１を選
択的にエツチング除去して所望の配線パターンを形成す
る。Next, as shown in FIG. 1<b>, the bias is set to -400
Bias sputtering is performed until the tungsten silicide layer 10 on the upper part of the interlayer insulating film 5 disappears under the condition that the reverse sputtering speed is higher than the deposition speed on the upper part of the interlayer insulating film 5. Thereafter, a tungsten layer 11 is deposited to a thickness of 0.8 μm by vapor phase growth. The vapor phase growth is performed by H2 reduction reaction of WF6 gas. The partial pressure of WF6 gas is 1 to 3X 10-' Torr, )-Tar gas pressure is 0.1 to 0.2 Torr, and the growth temperature is 350°C.
It is. The growth of the tungsten layer 11 progresses uniformly over the entire surface, but inside the opening 6, the bottom is narrowed by the tungsten silicide layer 10, so it grows while filling in from the bottom, and when the tungsten layer 11 is deposited to a thickness of 0.5 μm, the opening is opened. The inside of part 6 is completely buried. Furthermore, the surface of the tungsten layer 11 is made flat by depositing it to a thickness of 0.3 μm. Next, the tungsten layer 11 is selectively etched away using the photoresist film as a mask to form a desired wiring pattern.
ここで、第１の導体層として用いた硅化タングステン層
１０の代りにタングステン、モリブデン、硅化モリブデ
ン、チタン、硅化チタン等半導体装置に用い得る導体材
料を用いても良い。Here, instead of the tungsten silicide layer 10 used as the first conductor layer, a conductor material that can be used in semiconductor devices, such as tungsten, molybdenum, molybdenum silicide, titanium, and titanium silicide, may be used.
また、タングステンの気相成長にはＳｉＨ４還元反応を
用いることも可能であり、この場合、Ｈ２還元よりも速
い成長速度を得ることができる。Further, it is also possible to use a SiH4 reduction reaction for vapor phase growth of tungsten, and in this case, a faster growth rate than H2 reduction can be obtained.
なお、前記実施例で用いたＷＦ６の代りにトリイソブチ
ルアルミニウム（以下ＴＩＢＡと記す）を用い、気相成
長によりアルミニウム堆積しても良い。ＴＩＢＡは常温
では液体である為、ＨｅあるいはＡｒガスをバブリング
させこれにＨ２ガスを混合させてソースガスとして反応
室に導入する。また供給量を増加させる為に４０℃程度
に昇温する。この場合も０．８μｍ成長させて第１図（
ｂ）の状態が得られるがアルミニウム配線であることか
らタングステン層の場合に比べ低抵抗の配線が得られる
という利点がある。Note that triisobutylaluminum (hereinafter referred to as TIBA) may be used instead of WF6 used in the above embodiment, and aluminum may be deposited by vapor phase growth. Since TIBA is a liquid at room temperature, He or Ar gas is bubbled, H2 gas is mixed with the bubbled gas, and the mixture is introduced into the reaction chamber as a source gas. Further, in order to increase the supply amount, the temperature is raised to about 40°C. In this case as well, the growth was made to a thickness of 0.8 μm as shown in Figure 1 (
Although the state b) is obtained, since the wiring is made of aluminum, it has the advantage that a wiring having a lower resistance can be obtained than in the case of a tungsten layer.
また、多層配線の上下配線間の接続を行う場合に適用す
ることも可能である。Further, it is also possible to apply the present invention to the case where connections are made between upper and lower wirings of multilayer wiring.
以上説明したように本発明は、配線形成方法としてバイ
アススパッタリング方法により開口部内側壁の底部に厚
く第１の導体層を形成した後、気相成長法により第２の
導体層を開口部を含む表面に堆積することにより、素子
領域と電極配線を接続する為の微細な開口部内を第２の
導体層で完全に充填することができる。また第１の導体
層を開口部内部のみに堆積することによって層間絶縁膜
上に延在する配線は第２の導体層のみで形成される為、
配線の加工が容易となる。したがって、高集積度でかつ
高信頼性の集積回路装置が実現できる効果がある。As explained above, in the present invention, as a wiring forming method, a first conductive layer is formed thickly at the bottom of the inner wall of the opening by a bias sputtering method, and then a second conductive layer is formed by a vapor phase growth method including the opening. By depositing it on the surface, the second conductor layer can completely fill the inside of the minute opening for connecting the element region and the electrode wiring. Furthermore, by depositing the first conductor layer only inside the opening, the wiring extending on the interlayer insulating film is formed only from the second conductor layer.
Wiring processing becomes easier. Therefore, it is possible to realize an integrated circuit device with high degree of integration and high reliability.
第１図（ａ）、（ｂ）は本発明の一実施例を説明するた
めの工程ＩＩｍに示した半導体チップの断面図、第２図
乃至第４図は従来の半導体装置の製造方法の例を説明す
るための半導体チップの断面図である。
１・・・シリコン基板、２・・・フィールド酸化膜、３
ａ・・・ゲート電極、３ｂ・・・配線、４・・・不純物
拡散層、５・・・層間絶縁膜、６・・・開口部、７．８
・・・導体層、９・・・空洞、１０・・・硅化タングス
テン層、１１・・・タングステン層。FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor chip shown in step IIm for explaining an embodiment of the present invention, and FIGS. 2 to 4 are examples of a conventional method for manufacturing a semiconductor device. FIG. 2 is a cross-sectional view of a semiconductor chip for explaining. 1... Silicon substrate, 2... Field oxide film, 3
a... Gate electrode, 3b... Wiring, 4... Impurity diffusion layer, 5... Interlayer insulating film, 6... Opening, 7.8
... Conductor layer, 9... Cavity, 10... Tungsten silicide layer, 11... Tungsten layer.
Claims (1)
設ける工程と、前記素子領域上の前記層間絶縁層を選択
的にエッチングして開口部を設ける工程と、前記開口部
内の側壁表面のみに第１の導体層をバイアス・スパッタ
リング法により堆積する工程と、前記開口部を含む前記
層間絶縁膜の表面に第２の導体層を堆積する工程と、前
記第２の導体層を選択的にエッチングして前記開口部の
素子領域とコンタクトし且つ前記層間絶縁層上に延在す
る電極配線を形成する工程とを含むことを特徴とする半
導体装置の製造方法。a step of providing an interlayer insulating layer on a semiconductor substrate having a semiconductor element region; a step of selectively etching the interlayer insulating layer on the element region to form an opening; and a step of forming an opening only on the sidewall surface within the opening. a step of depositing a first conductor layer by a bias sputtering method, a step of depositing a second conductor layer on the surface of the interlayer insulating film including the opening, and a step of selectively etching the second conductor layer. forming an electrode wiring that contacts the element region of the opening and extends on the interlayer insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10242089A JPH02281622A (en) | 1989-04-21 | 1989-04-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10242089A JPH02281622A (en) | 1989-04-21 | 1989-04-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02281622A true JPH02281622A (en) | 1990-11-19 |
Family
ID=14326958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10242089A Pending JPH02281622A (en) | 1989-04-21 | 1989-04-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02281622A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03190124A (en) * | 1989-12-19 | 1991-08-20 | Mitsubishi Electric Corp | Semiconductor device |
| JP2008028046A (en) * | 2006-07-19 | 2008-02-07 | Ulvac Japan Ltd | Thin-film forming method and copper wiring film forming method |
-
1989
- 1989-04-21 JP JP10242089A patent/JPH02281622A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03190124A (en) * | 1989-12-19 | 1991-08-20 | Mitsubishi Electric Corp | Semiconductor device |
| JP2008028046A (en) * | 2006-07-19 | 2008-02-07 | Ulvac Japan Ltd | Thin-film forming method and copper wiring film forming method |
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