JPH02280475A - Agc circuit - Google Patents

Agc circuit

Info

Publication number
JPH02280475A
JPH02280475A JP10254489A JP10254489A JPH02280475A JP H02280475 A JPH02280475 A JP H02280475A JP 10254489 A JP10254489 A JP 10254489A JP 10254489 A JP10254489 A JP 10254489A JP H02280475 A JPH02280475 A JP H02280475A
Authority
JP
Japan
Prior art keywords
video
signal
agc
input
processing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10254489A
Other languages
Japanese (ja)
Inventor
Fumiaki Honda
本多 文明
Tetsuhiro Maeda
哲宏 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10254489A priority Critical patent/JPH02280475A/en
Publication of JPH02280475A publication Critical patent/JPH02280475A/en
Pending legal-status Critical Current

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  • Television Receiver Circuits (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To avoid an input level of a video processing circuit from being much increased and to attain normal digital conversion or the like for a video processing circuit at the occurrence of horizontal synchronization contract by switching a video signal fed to the video processing circuit into an input video signal before AGC amplification when the horizontal synchronization contract being large attenuation of a horizontal synchronizing signal at a comparator. CONSTITUTION:The circuit is provided with a video amplifier 6 with AGC function whose gain is controlled with an AGC voltage in following to level fluctuation of a horizontal synchronizing signal of an input video signal, amplifying the input video signal with AGC and outputting the result to a video processing circuit 10, a comparator 7 comparing the AGC voltage with a reference voltage detecting the horizontal synchronization contract and outputting a detection signal when the AGC voltage is less than the detection reference voltage and a changeover circuit 9 switching the input of the video processing circuit 10 into the input video signal from the output video signal of the video amplifier 6 at the input of the detection signal. Thus, the input level of the video processing circuit 10 is not too much in the occurrence of horizontal synchronization contract and digital conversion or the like is implemented normally.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、テレビジラン受像機等のAGC回路に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AGC circuit for a television receiver or the like.

〔従来の技術〕[Conventional technology]

従来、テレビジョン受像機(以下TVという)等におい
ては、映像処理回路の入力レベルを一定に保つため、そ
の前段の映像増幅回路の入力映像信号(コンポジット信
号)をAGC回路で処理し、水平同期信号のレベル変化
に従追したAGC電圧を形成し、このAGC電圧により
映像増幅回路の前段の映像中間周波増幅回路(以下VI
P回路という)等の利得をフィーバパック制御してAG
C増幅を行っている。
Conventionally, in television receivers (hereinafter referred to as TVs), etc., in order to keep the input level of the video processing circuit constant, the input video signal (composite signal) of the video amplification circuit in the previous stage is processed by the AGC circuit, and horizontal synchronization is performed. An AGC voltage that follows signal level changes is formed, and this AGC voltage is used to control the video intermediate frequency amplification circuit (hereinafter referred to as VI) in the previous stage of the video amplification circuit.
AG by controlling the gain of P circuit) etc.
C amplification is being performed.

また、特開昭60−217767号公報(HO4N 5
152)には、映像処理回路をデジタル回路で構成した
よりTV等のクリアビジョンにおいて、映像処理回路の
初段のA/D変換器・丘映像検波にも共用し、A/D変
換器でデジタル的に検波された映像信号をAGC検波し
て前記AGC@圧を形成し、この電圧でVIP回路等の
利得をフィードバック制御してAGC増幅するAGC回
路が記載されている。
Also, Japanese Patent Application Laid-Open No. 60-217767 (HO4N5
152), in clear vision devices such as TVs where the video processing circuit is configured with a digital circuit, it is also used for the first-stage A/D converter and hill video detection of the video processing circuit, and the A/D converter is used for digital detection. An AGC circuit is described in which AGC detects a video signal detected by AGC to form the AGC@ voltage, and performs AGC amplification by feedback controlling the gain of a VIP circuit or the like using this voltage.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前記従来のAGC回路の場合、映像処理回路に供給され
る映像信号1常にAGC増幅するため、以下に記載する
問題点がある。
In the case of the conventional AGC circuit, since the video signal 1 supplied to the video processing circuit is always AGC-amplified, there are problems described below.

すなわち、アンテナケーブルの引回し等によって映像処
理回路の前段の伝送路中に等測的1こバイパスフィルタ
が形成されると、周波数の低い水平同期信号のみが大き
く減衰し、いわゆる水平同期縮みが発生する。
In other words, when an isometry single bypass filter is formed in the transmission path before the video processing circuit due to antenna cable routing, etc., only the low frequency horizontal synchronization signal is greatly attenuated, resulting in so-called horizontal synchronization compression. do.

また、チューナの受信電界が弱電界のときにも前記と同
様の水平同期縮みが発生する。
Further, horizontal synchronization compression similar to that described above also occurs when the received electric field of the tuner is weak.

そして、水平同期縮みが発生すると、映像信号部分のレ
ベルが正常であっても大きな利得でAGC増幅が行われ
る。
When horizontal synchronization compression occurs, AGC amplification is performed with a large gain even if the level of the video signal portion is normal.

この場合、映像処理回路の入力レベルが過大になり、例
えば前記クリアビジタンにおいては、A/D変換器で正
常なデジタル変換が行えなくなり、忠実な映像再生が行
えなくなる。
In this case, the input level of the video processing circuit becomes excessive, and, for example, in the clear visitor, the A/D converter cannot perform normal digital conversion, and faithful video reproduction cannot be performed.

本発明は、前記水平同期縮みによる映像処理回路の入力
レベルの過大を防止するようにしたAGC回路を提供す
ることを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide an AGC circuit that prevents an excessive input level of a video processing circuit due to the horizontal synchronization compression.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するため、本発明のAGC回路は、入力
映像信号の水平同期信号のレベル変動に追従したAGC
電圧で利得制御され、前記入力映像信号をAGC増幅し
て映像処理回路に出力するAGC機能付きの映像増幅器
と、 前記AGC電圧と水平同期縮みの検出基準電圧とを比軟
し、前記AGC電圧が前記検出基準電圧以下のとき1こ
検出信号を出力する比較器と、前記検出信号の入力時に
前記映像処理回路の入力を前記映像増幅器の出力映像信
号から前記入力映像信号に切換える切換回路とを備える
In order to achieve the above object, the AGC circuit of the present invention performs an AGC circuit that follows level fluctuations of a horizontal synchronizing signal of an input video signal.
A video amplifier with an AGC function whose gain is controlled by a voltage and which AGC amplifies the input video signal and outputs it to a video processing circuit; A comparator that outputs a single detection signal when the detection reference voltage is lower than the detection reference voltage, and a switching circuit that switches the input of the video processing circuit from the output video signal of the video amplifier to the input video signal when the detection signal is input. .

〔作用〕[Effect]

前記のように構成された本発明のAGC回路の場合、映
像処理回路の前段の映像増幅器で入力映像信号がAGC
増幅され、かつ、水平同期信号が大きく減衰する水平同
期縮みが比較器で検出されると切換回路の切換えに基き
、映像処理回路に供給される映像信号が、映像増幅器の
AGC増・福された出力映像信号からAGC増幅前の入
力映像信号に切換わる。
In the case of the AGC circuit of the present invention configured as described above, the input video signal is processed by the AGC circuit in the video amplifier at the front stage of the video processing circuit.
When the comparator detects horizontal synchronization compression in which the horizontal synchronization signal is amplified and greatly attenuated, the video signal supplied to the video processing circuit is amplified by the AGC of the video amplifier based on switching of the switching circuit. The output video signal is switched to the input video signal before AGC amplification.

そのため、水平同期縮みの発生時、映像処理回路の入力
レベルが過大にならず、映像処理回路のデジタル変換等
が正常に行える。
Therefore, when horizontal synchronization compression occurs, the input level of the video processing circuit does not become excessive, and the video processing circuit can normally perform digital conversion.

〔実施例〕〔Example〕

■実施例について、第1図ないし第3図を参照して以下
に説明する。
(2) Examples will be described below with reference to FIGS. 1 to 3.

第1図はIDTVに適用した場合を示し、(1)はテレ
ビアンテナ、(2)はチューナ、(3)はVIP回路、
(4)は外部ビデオ入力端子である。
Figure 1 shows the case where it is applied to IDTV, where (1) is a TV antenna, (2) is a tuner, (3) is a VIP circuit,
(4) is an external video input terminal.

(5)はAGC回路であり、AGC機能付きの映像増幅
器(6)、比較器(7)、基準電源(8)及び切換回路
としての信号セレクタ(9)からなる。
(5) is an AGC circuit, which includes a video amplifier (6) with an AGC function, a comparator (7), a reference power source (8), and a signal selector (9) as a switching circuit.

CIGはデジタル回路構成の映像処理回路であり、A/
D変換器(Ill 、 Y/C処理回路α3.D/A変
換器曽及びマトリクス回路Q41からなる。α9は画面
再生用のCRTである。
CIG is an image processing circuit with a digital circuit configuration, and A/
It consists of a D converter (Ill), a Y/C processing circuit α3, a D/A converter and a matrix circuit Q41. α9 is a CRT for screen reproduction.

そして、アンテナ(1)の受信信号がチューナ(2)。The received signal from the antenna (1) is sent to the tuner (2).

VIP回路(3)で処理され、コ(7) VIP’回路
(3)からAGCよ(5)の映像増幅器(6)に、受信
チャンネルの映像信号(コンポジット信号)が入力映像
信号として出力される。
The video signal (composite signal) of the receiving channel is processed by the VIP circuit (3), and is output as an input video signal from the VIP' circuit (3) to the video amplifier (6) of AGC (5). .

このとき、チューナ(2+、VIF回路(3)に鼾のA
GC電圧が供給されず、映像増幅器(6)の入力映像信
号がAGC増幅することなく形成される。
At this time, tuner (2+), VIF circuit (3)
No GC voltage is supplied, and the input video signal of the video amplifier (6) is formed without AGC amplification.

そして、映像増幅器(6)は第2図に示すように構成さ
れ、入力映像信号が利得制御型のビデオ増幅! (6a
)及び水平同期ゲー) (6b)に供給される。
The video amplifier (6) is configured as shown in FIG. 2, and the input video signal is gain-controlled video amplification! (6a
) and horizontal synchronization game) (6b).

このとき、同期分対回路(図示せず)からゲート端子(
6c)を介して水平同期ゲート(6b)に水平同期位置
のゲートパルスが供給され、このパルスによって水平同
期ゲート(6b)がオンし、入力映像信号の水平同期信
号のみが誤差増幅器(6d)に供給される。
At this time, the gate terminal (
A gate pulse at the horizontal synchronization position is supplied to the horizontal synchronization gate (6b) through the gate (6c), the horizontal synchronization gate (6b) is turned on by this pulse, and only the horizontal synchronization signal of the input video signal is sent to the error amplifier (6d). Supplied.

そして、誤差増幅器(6d) tこより、水平同期信号
の先頭電圧(ピーク値)と基準電源(6e)のAGC基
準電圧とが誤差増幅され、両電圧の差がローパスフィル
タ(6f)で処理され、水平同期信号のレベル変化に追
従したAGCi圧Vaが形成される。
Then, the error amplifier (6d) amplifies the error between the leading voltage (peak value) of the horizontal synchronizing signal and the AGC reference voltage of the reference power supply (6e), and the difference between the two voltages is processed by the low-pass filter (6f). An AGCi pressure Va that follows the level change of the horizontal synchronization signal is formed.

この電圧Vaがビデオ増逼器(6a)に利得制御電圧と
して供給され、ビデオ増幅器(6a)が入力映像信号を
AGC増幅して信号セレクタ(9)に供給する。
This voltage Va is supplied to the video amplifier (6a) as a gain control voltage, and the video amplifier (6a) amplifies the input video signal by AGC and supplies it to the signal selector (9).

また、AGC電圧Vaが比較器(7)にも供給され、こ
の比較器(7)により、AGC電圧Vaと基準電源(8
)の水平同期縮みの検出基準電エキvbとが比較される
The AGC voltage Va is also supplied to a comparator (7), which compares the AGC voltage Va with the reference power source (8).
) is compared with the horizontal synchronization compression detection reference electric exhaust vb.

このとき、水平同期信号のレベルとAGC[圧とが第3
図の関係を有し、水平同期信号のレベルがや 大きく減衰して水平同期縮みが発生するしき値電圧が同
図の破線の電圧になるとすれば、検出基準電圧vbが破
線の電圧に設定される。
At this time, the level of the horizontal synchronizing signal and the AGC [pressure] are
If the relationship shown in the figure exists, and the threshold voltage at which the level of the horizontal synchronization signal attenuates a little and horizontal synchronization compression occurs is the voltage indicated by the broken line in the figure, then the detection reference voltage vb is set to the voltage indicated by the broken line. Ru.

そのため、AGCjt圧が検出基準電圧vbより低下す
る水平同期縮みの発生時、比較器(7)の出力信号がハ
イレベルからローレベルに反転し、ローレベルの検出信
号が比較器(7)から信号セレクタ(9)に供給される
Therefore, when horizontal synchronous compression occurs where the AGCjt pressure drops below the detection reference voltage vb, the output signal of the comparator (7) is inverted from high level to low level, and the low level detection signal is output from the comparator (7). It is supplied to the selector (9).

そして、比較器(7)の出力信号がローレベルになると
、信号セレクタ(9)からA/D変換器CIυに供給さ
れる信号が、映像増幅器(6)の出力映像信号からこの
増幅器(6)の入力映像信号に切換わる。
Then, when the output signal of the comparator (7) becomes low level, the signal supplied from the signal selector (9) to the A/D converter CIυ is changed from the output video signal of the video amplifier (6) to this amplifier (6). input video signal.

したがって、入力映像信号の水平同期信号のみが大きく
減衰し、AGC増幅fこよってA/D変換器a1)の入
力レベルが過大船こなるときに、A/D fi換器αυ
の入力信号がAGC増幅前の入力映像信号に切換わり、
映像信号部分のデジタル変換が正常に行われる。
Therefore, when only the horizontal synchronizing signal of the input video signal is greatly attenuated and the input level of the A/D converter a1) becomes excessive due to the AGC amplification f, the A/D fi converter αυ
The input signal is switched to the input video signal before AGC amplification,
Digital conversion of the video signal part is performed normally.

そして、A/D変換器αυの出力信号がY/C処理回路
aのに供給され、この処理回路α2iこよりY/C分離
、走査変換、補間処理等がデジタル的に行われる。
The output signal of the A/D converter αυ is supplied to a Y/C processing circuit a, and Y/C separation, scan conversion, interpolation processing, etc. are digitally performed by this processing circuit α2i.

さらに、処理回路(2)の出力信号がD/A変換器αa
でアナログ変換されてマトリクス回路0小に供給され、
このマトリクス回路0毛で3原色信号に変換されこの3
原色信号がCRTQSに供給される。
Furthermore, the output signal of the processing circuit (2) is transmitted to the D/A converter αa.
is converted into analog and supplied to the matrix circuit 0,
This matrix circuit converts into 3 primary color signals and these 3
Primary color signals are provided to the CRTQS.

なお、ビデオ戸旧−−ダ、ビデオディスク等の映像寺 機器からビデオ入力端子(4)供給された映像信号(コ
ンポジット信号)を再生する場合にも、前記と同様の処
理が施される。
Note that the same processing as described above is also performed when reproducing a video signal (composite signal) supplied to the video input terminal (4) from a video equipment such as a video player or a video disc.

そして、前記実施例ではIDTVに適用したが、揮々の
TV及び映像機器に適用することができるのは勿論であ
る。
In the above embodiment, the invention is applied to an IDTV, but it goes without saying that it can be applied to various TVs and video equipment.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように構成されているため、以
下に記載する効果を奏する。
Since the present invention is configured as described above, it produces the effects described below.

映像処理回路の前段の映像増幅器で入力映像信号がAG
C増幅され、かつ、水平同期信号が大きく減衰する水平
同期縮みが比較器で検出されると、切換回路の切換えに
基き、映像処理回路に供給される映像信号が、映像増幅
器のAGC増幅された出力映像信号からAGC増幅前の
入力映像信号に切換わる。
The input video signal is AGed by the video amplifier before the video processing circuit.
When the comparator detects horizontal synchronization compression in which the horizontal synchronization signal is amplified and the horizontal synchronization signal is greatly attenuated, the video signal supplied to the video processing circuit is amplified by the AGC of the video amplifier based on the switching of the switching circuit. The output video signal is switched to the input video signal before AGC amplification.

そのため、水平同期縮みの発生時、映像処理回路の入力
レベルが過大にならず、映像処理回路のデジタル変換等
が正常に行え、入力映像信号の異常時にも忠実な映像再
生が行える。
Therefore, when horizontal synchronization compression occurs, the input level of the video processing circuit does not become excessive, the digital conversion of the video processing circuit, etc. can be performed normally, and faithful video reproduction can be performed even when the input video signal is abnormal.

【図面の簡単な説明】[Brief explanation of drawings]

図面は本発明のAGC回路の1実施例を示し、第1図は
ブロック図、第2図は映像増幅器の詳細なブロック図、
第3図は水平同期信号のレベルとAGC電圧との関係図
である。 (6)・・・AGC機能付き映像増幅器、(7)・・・
比較器、(9)・・信号セレクタ、叫・・・映像処理回
路。 2−一一今よ−ナ 3−VIF日鯵 5−AGC[ilP%− 6−吠像漕τ品5 7=−zこや気管シ 9−−一福↑−已し77 第 1 図 10−  武傳幼理ω玲 11−A/Dで捩3 12−−− Y/C、Q理つ琢 13−−−0/A受橡へ 14−−−マド;)7人EJ%− 15−−−C9丁
The drawings show one embodiment of the AGC circuit of the present invention, FIG. 1 is a block diagram, FIG. 2 is a detailed block diagram of a video amplifier,
FIG. 3 is a diagram showing the relationship between the level of the horizontal synchronizing signal and the AGC voltage. (6)...Video amplifier with AGC function, (7)...
Comparator, (9)...signal selector, signal...video processing circuit. 2-11 Imayo-na 3-VIF Japanese horse mackerel 5-AGC [ilP%- 6-Bozoko τ product 5 7=-z Koya trachea 9--Ichifuku↑-Yoshi 77 1st Figure 10 - Takeden Yori ω Rei 11-A/D and twist 3 12--- Y/C, Q Ritsu Taku 13---0/A acceptance to 14---Mad;) 7 people EJ%- 15 ---C9-cho

Claims (1)

【特許請求の範囲】[Claims] (1)入力映像信号の水平同期信号のレベル変動に追従
したAGC電圧で利得制御され、前記入力映像信号をA
GC増幅して映像処理回路に出力するAGC機能付きの
映像増幅器と、 前記AGC電圧と水平同期縮みの検出基準電圧とを比較
し、前記AGC電圧が前記検出基準電圧以下のときに検
出信号を出力する比較器と、 前記検出信号の入力時に前記映像処理回路の入力を前記
映像増幅器の出力映像信号から前記入力映像信号に切換
える切換回路と を備えたことを特徴とするAGC回路。
(1) The gain is controlled by the AGC voltage that follows the level fluctuation of the horizontal synchronization signal of the input video signal, and the input video signal is
A video amplifier with an AGC function that amplifies GC and outputs it to a video processing circuit, compares the AGC voltage with a detection reference voltage for horizontal synchronization compression, and outputs a detection signal when the AGC voltage is less than the detection reference voltage. and a switching circuit that switches the input of the video processing circuit from the output video signal of the video amplifier to the input video signal when the detection signal is input.
JP10254489A 1989-04-20 1989-04-20 Agc circuit Pending JPH02280475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10254489A JPH02280475A (en) 1989-04-20 1989-04-20 Agc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10254489A JPH02280475A (en) 1989-04-20 1989-04-20 Agc circuit

Publications (1)

Publication Number Publication Date
JPH02280475A true JPH02280475A (en) 1990-11-16

Family

ID=14330195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10254489A Pending JPH02280475A (en) 1989-04-20 1989-04-20 Agc circuit

Country Status (1)

Country Link
JP (1) JPH02280475A (en)

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