JPH02274492A - Manufacture of substrate for circuit - Google Patents
Manufacture of substrate for circuitInfo
- Publication number
- JPH02274492A JPH02274492A JP9359689A JP9359689A JPH02274492A JP H02274492 A JPH02274492 A JP H02274492A JP 9359689 A JP9359689 A JP 9359689A JP 9359689 A JP9359689 A JP 9359689A JP H02274492 A JPH02274492 A JP H02274492A
- Authority
- JP
- Japan
- Prior art keywords
- die
- punching
- punched
- circuit
- female
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000004080 punching Methods 0.000 claims abstract description 26
- 238000003825 pressing Methods 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 239000011888 foil Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 22
- 230000013011 mating Effects 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Landscapes
- Nonmetal Cutting Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、平押処理で打抜き体に生じたバリを圧縮偏平
化するようにした回路用基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a circuit board in which burrs generated on a punched body during flat pressing are compressed and flattened.
従来の技術及び課題
従来、第１図のように、金属基板の上に樹脂絶縁層を介
して金属箔からなる回路形成層を有する回路用基板の大
判体２を、打抜き機のオス型１とメス型３の間に配置し
、これをオス型とメス型の嵌合下に打抜いて基板単位と
しての打抜き体４を製造する方法が知られていた。BACKGROUND ART Conventionally, as shown in FIG. 1, a large-sized circuit board 2 having a circuit forming layer made of metal foil on a metal substrate via a resin insulating layer is cut using a male die 1 of a punching machine. There has been known a method of manufacturing a punched body 4 as a board unit by disposing it between female molds 3 and punching it while the male mold and female mold are fitted together.
しかしながら、図の如（打抜き体４の周縁部に反返り状
のバリ４１が生じる問題点があった。かかるバリは、回
路用基板を金属基板側から打抜いた場合には裏面側に生
じて装置本体への装着を阻害し、回路形成層側から打抜
いた場合には金属基板と樹脂絶縁層を剥離する原因とな
り、いずれの場合もそのままでは実用に供することがで
きない。However, as shown in the figure, there was a problem in that a curved burr 41 was formed on the periphery of the punched body 4. When a circuit board is punched from the metal board side, such burrs are formed on the back side. It obstructs attachment to the main body of the device, and when punched from the circuit forming layer side, it causes separation of the metal substrate and the resin insulating layer, and in either case, it cannot be put to practical use as it is.
単なる金属平板等の場合には研磨処理によりバリを容易
に除去できるが、回路用基板の場合には、破損しやすい
金属箔の回路形成層があるため研磨処理は適用できない
。In the case of a simple flat metal plate, burrs can be easily removed by polishing, but in the case of a circuit board, polishing cannot be applied because there is a circuit forming layer of metal foil that is easily damaged.
従って、本発明は回路形成層を損傷させることな（、バ
リ問題を克服することを課題とする。Therefore, an object of the present invention is to overcome the burr problem without damaging the circuit forming layer.
課題を解決するための手段
本発明は、バリを圧縮偏平化することにより前記の問題
点を克服したものである。Means for Solving the Problems The present invention overcomes the above problems by compressing and flattening the burr.
すなわち、本発明は、メス型とオス型の間に被打抜き板
を介在させてメス型とオス型の嵌合下に打抜き体を形成
するようにした打抜き機を用いて、金属基板の上に樹脂
絶縁層を介して金属箔からなる回路形成層を有する回路
用基板の大判体を単位基板に打抜いて形成した打抜き体
を、押圧型で平押して打抜き体に生じたバリを圧縮偏平
化することを特徴とする回路用基板の製造方法を提供す
るものである。That is, the present invention uses a punching machine in which a punched plate is interposed between the female die and the male die to form a punched body under the female die and the male die when they are fitted together, and a die is formed on a metal substrate. A punched body formed by punching out a large size circuit board having a circuit forming layer made of metal foil through a resin insulating layer into a unit board is pressed flat with a pressing die to compress and flatten the burrs generated on the punched body. The present invention provides a method for manufacturing a circuit board characterized by the following.
実施例
本発明においては、打抜き体に生じたバリを押圧型で平
押して圧縮偏平化する。第２図にその処理方式を例示し
た。この例では、打抜き体４をそのバリ４１側を下側に
してメス型６に入れ、これを押圧型５で平押してバリ４
１をメス型６の底部におけるテーパ一部６１を介し圧縮
偏平化する。Embodiment In the present invention, burrs generated on a punched body are flattened by pressing with a pressing die. FIG. 2 shows an example of the processing method. In this example, the punched body 4 is put into the female die 6 with its burr 41 side facing down, and is pressed flat with the pressing die 5 to form the burr 4.
1 is compressed and flattened through a tapered portion 61 at the bottom of the female mold 6.
一方、第３図の例では打抜き体４を、バリ４１側を上側
にしてメス型６に入れ、これを抑圧型７で平押してバリ
４１を押圧型７の先端部におけるテーパー状の周縁部７
１を介し圧縮偏平化する。このように、本発明において
は適宜な抑圧型等を用いて平押処理してよい。On the other hand, in the example shown in FIG. 3, the punched body 4 is placed in the female mold 6 with the burr 41 side facing upward, and is pressed flat with the pressing mold 7 to remove the burr 41 from the tapered peripheral edge 7 at the tip of the pressing mold 7.
Compress and flatten via 1. As described above, in the present invention, the flat pressing process may be performed using an appropriate suppression mold or the like.
処理効率に優れる本発明の方式は、平押処理を打抜き処
理と同時に行う方式である。第４図にその方式を例示し
た。この例では、オス型８１及び押圧型８２を併設した
オス型本体８と、そのオス型８１、ないし押圧型８２が
嵌合する窪み９１を複数併設したメス型本体９を有する
打抜き機を用いる。メス型本体９は、間欠運動方式のタ
ーンテーブルからなり、打抜き処理（平押処理）と同期
して窪み単位にターンするようになっている。これによ
り、先の打抜き処理で形成された打抜き体４が自動的に
押圧型８２に対応する位置に配置され、かつ空の窪み９
１がオス型８１に対応する位置に配置される。その結果
、打抜き処理と同時に平押処理がなされる。なお平押処
理を終えた打抜き体は、適宜な手段で窪み９１より回収
される。The method of the present invention, which has excellent processing efficiency, is a method in which the flat pressing process is performed simultaneously with the punching process. Figure 4 shows an example of this method. In this example, a punching machine is used that has a male die main body 8 with a male die 81 and a pressing die 82, and a female die main body 9 with a plurality of recesses 91 into which the male die 81 or the press die 82 fit. The female die main body 9 is composed of an intermittent movement type turntable, and turns in units of depressions in synchronization with the punching process (flat pressing process). As a result, the punched body 4 formed in the previous punching process is automatically placed in the position corresponding to the pressing die 82, and the empty depression 9
1 is placed at a position corresponding to the male mold 81. As a result, the flat pressing process is performed simultaneously with the punching process. The punched body after the flat pressing process is recovered from the depression 91 by an appropriate means.
本発明の方法が平押対象とする打抜き体は、第５図の如
く金属基板４４の上に樹脂絶縁層４３を介して金属箔か
らなる回路形成層４２を有する回路用基板４である。そ
の回路用基板は、ビス止め等に利用される孔を同時に打
抜き形成されたものであってもよい。孔の形成は、例え
ば打抜き用のオス型に、孔形成用のビン状刃を突出状態
に設けることにより行うことができる。The punched object to be pressed in the method of the present invention is a circuit board 4 having a circuit forming layer 42 made of metal foil on a metal substrate 44 with a resin insulating layer 43 interposed therebetween, as shown in FIG. The circuit board may also be one in which holes used for screw fixing etc. are punched out at the same time. The holes can be formed, for example, by providing a protruding bottle-shaped blade for hole formation on a male die for punching.
前記の打抜き体は、基板単位の回路形成層パターンを連
設してなる大判体（２）を、単位基板に打抜いて形成さ
れる。打抜き対象の大判体については特に限定はない。The punched body is formed by punching out a large size body (2) in which circuit formation layer patterns are arranged in series on a unit board basis into unit boards. There are no particular limitations on the large format to be punched.
一般には、アルミニウム等からなる厚さ１〜４ＩＩＩ１
１の金属基板の上に、ポリイミド等からなる厚さ２０〜
５００ｕｍの樹脂絶縁層を介し、銅箔等からなる厚さｌ
Ｏ〜２００μｌの金属箔を設けたものが対象とされる。Generally, it is made of aluminum etc. and has a thickness of 1 to 4III1.
1. On top of the metal substrate 1, a layer made of polyimide etc. with a thickness of 20~
Thickness l made of copper foil etc. through a 500um resin insulation layer
The target is one provided with a metal foil of 0 to 200 μl.
その樹脂絶縁層は、セラミック粉末等の充填剤を含有し
ていてもよい。The resin insulating layer may contain filler such as ceramic powder.
また、回路形成層を形成する金属箔は、無加工状態、区
画パターン化状態、回路パターン化状態など、任意な状
態にあってよい。Further, the metal foil forming the circuit forming layer may be in any state, such as an unprocessed state, a section patterned state, a circuit patterned state, or the like.
平押対象の打抜き体は、金属基板側より打抜いたもので
あってもよいし、回路形成層側より打抜いたものであっ
てもよい。なお、打抜き時ないし平押時おいて回路形成
層が損傷することを防止するため、フィルム等で回路形
成層を被覆保護してもよい。The punched body to be flat pressed may be punched from the metal substrate side or may be punched from the circuit forming layer side. In addition, in order to prevent the circuit forming layer from being damaged during punching or flat pressing, the circuit forming layer may be covered and protected with a film or the like.
発明の効果
本発明の方法によれば、回路形成層を損傷させることな
くバリを圧縮偏平化することができ、打抜き体からなる
回路用基板を支障なく実用に供することができ、その製
造効率にも優れている。平押処理を打抜き処理と同時に
行う方式にあっては、その製造効率に特に優れている。Effects of the Invention According to the method of the present invention, burrs can be compressed and flattened without damaging the circuit forming layer, and a circuit board made of a punched body can be put into practical use without any problems, and its manufacturing efficiency is improved. is also excellent. A method in which the flat pressing process is performed simultaneously with the punching process is particularly excellent in manufacturing efficiency.
第１図はバリ発生状態の説明図、第２図は実施例の説明
断面図、第３図は他の実施例の説明断面図、第４図はさ
らに他の実施例の説明断面図、第５図は打抜き体として
の回路用基板の断面図である。
第
１：オス型
２：被打抜き板（回路用基板の大判体）３：メス型
４：打抜き体（単位基板）
４１：バリ
４２：回路形成層
４３：樹脂絶縁層
４４：金属基板
５．７；押圧型
６；メス型
８：オス型本体
８１：オス型
８２：押圧型
９：メス型本体
９１：窪み
第
図
第４図
特許出願人 三菱電線工業株式会社FIG. 1 is an explanatory diagram of a burr generation state, FIG. 2 is an explanatory sectional view of an embodiment, FIG. 3 is an explanatory sectional diagram of another embodiment, and FIG. 4 is an explanatory sectional diagram of another embodiment. FIG. 5 is a sectional view of a circuit board as a punched body. 1st: Male mold 2: Punching board (large circuit board) 3: Female mold 4: Punching body (unit board) 41: Burr 42: Circuit forming layer 43: Resin insulation layer 44: Metal substrate 5.7 ; Pressing mold 6; Female mold 8: Male mold main body 81: Male mold 82: Pressing mold 9: Female mold main body 91: Recess Diagram 4 Patent applicant Mitsubishi Cable Industries, Ltd.
Claims (2)
型とオス型の嵌合下に打抜き体を形成するようにした打
抜き機を用いて、金属基板の上に樹脂絶縁層を介して金
属箔からなる回路形成層を有する回路用基板の大判体を
単位基板に打抜いて形成した打抜き体を、押圧型で平押
して打抜き体に生じたバリを圧縮偏平化することを特徴
とする回路用基板の製造方法。1. Using a punching machine that forms a punched body under the mating female and male molds by interposing a punched plate between the female mold and the male mold, the die is cut onto a metal substrate through a resin insulating layer. A circuit characterized in that a punched body formed by punching out a large size circuit board having a circuit forming layer made of metal foil into a unit board is pressed flat with a pressing die to compress and flatten burrs generated on the punched body. method for manufacturing substrates for
みを併設したメス型を有する打抜き機を用いて、打抜き
処理と平押処理を同時に行うことを特徴とする請求項１
に記載の製造方法。2. Claim 1 characterized in that the punching process and the flat pressing process are performed simultaneously using a punching machine having a male die with a press die and a female die with a fitting recess for the press die.
The manufacturing method described in.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9359689A JPH02274492A (en) | 1989-04-12 | 1989-04-12 | Manufacture of substrate for circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9359689A JPH02274492A (en) | 1989-04-12 | 1989-04-12 | Manufacture of substrate for circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02274492A true JPH02274492A (en) | 1990-11-08 |
Family
ID=14086693
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9359689A Pending JPH02274492A (en) | 1989-04-12 | 1989-04-12 | Manufacture of substrate for circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02274492A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018202482A (en) * | 2017-05-30 | 2018-12-27 | ファインツール インターナショナル ホールディング アーゲー | Method for manufacturing punched component |
-
1989
- 1989-04-12 JP JP9359689A patent/JPH02274492A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018202482A (en) * | 2017-05-30 | 2018-12-27 | ファインツール インターナショナル ホールディング アーゲー | Method for manufacturing punched component |
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