JPH02271634A - Formation of multi-layer wiring - Google Patents
Formation of multi-layer wiringInfo
- Publication number
- JPH02271634A JPH02271634A JP9182989A JP9182989A JPH02271634A JP H02271634 A JPH02271634 A JP H02271634A JP 9182989 A JP9182989 A JP 9182989A JP 9182989 A JP9182989 A JP 9182989A JP H02271634 A JPH02271634 A JP H02271634A
- Authority
- JP
- Japan
- Prior art keywords
- wiring material
- substrate
- connection hole
- step coverage
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015572 biosynthetic process Effects 0.000 title claims description 6
- 239000000463 material Substances 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000956 alloy Substances 0.000 claims abstract description 18
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 18
- 230000008018 melting Effects 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 24
- 229910052782 aluminium Inorganic materials 0.000 claims description 24
- 238000007738 vacuum evaporation Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 abstract description 25
- 238000001771 vacuum deposition Methods 0.000 abstract description 13
- 239000007788 liquid Substances 0.000 abstract description 3
- 229910052736 halogen Inorganic materials 0.000 abstract description 2
- 150000002367 halogens Chemical class 0.000 abstract description 2
- 238000009825 accumulation Methods 0.000 abstract 2
- 230000005855 radiation Effects 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 description 22
- 239000002245 particle Substances 0.000 description 16
- 230000000694 effects Effects 0.000 description 14
- 239000010408 film Substances 0.000 description 11
- 238000001704 evaporation Methods 0.000 description 10
- 230000008020 evaporation Effects 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 239000010949 copper Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical group [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- -1 composed of AI Chemical compound 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置製造工程における多層配線形成方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming multilayer wiring in a semiconductor device manufacturing process.
本発明は、半導体装置製造工程における多層配線形成方
法に関し、更に詳しくは、半導体装置の内部多層配線に
おいて、アルミニウム（ＡＩ）またはＡＩを主体とする
合金からなる配線材料で接続孔を埋め込む、ステップカ
バレッジに優れた多層配線形成方法に関する。The present invention relates to a method for forming multilayer wiring in a semiconductor device manufacturing process, and more specifically to a step coverage method for filling contact holes with wiring material made of aluminum (AI) or an alloy mainly composed of AI in internal multilayer wiring of a semiconductor device. The present invention relates to a method for forming multilayer interconnects with excellent performance.
ＬＳＩ等の半導体装置は、素子の高集積度化および多層
化に伴い、内部配線幅が微細化し、接続孔のアスペクト
比すなわち孔の深さと直径の比は例えば１以上と大きな
値が採用されつつある。この接続孔を例えば八１または
Ａ１を主体とする合金等からなる配線材料で埋め込む多
層配線形成方法の重要性が高まってきた。As semiconductor devices such as LSIs become more highly integrated and multi-layered, the internal wiring width becomes finer, and the aspect ratio of the contact hole, that is, the ratio of the depth to the diameter of the hole, is becoming larger, for example, 1 or more. be. The importance of a multilayer wiring formation method in which the connection hole is filled with a wiring material made of, for example, an alloy mainly composed of 81 or A1 has been increasing.
従来よりＡＩまたはＡＩを主体とする合金からなる配線
材料を、薄膜の形状で基体上に形成する方法は、平行平
板型等のスパッタリング法が主として用いられてきた。Conventionally, as a method for forming a wiring material made of AI or an alloy mainly composed of AI on a substrate in the form of a thin film, a parallel plate sputtering method or the like has been mainly used.
しかし、従来からのスパッタリング法においても、アス
ペクト比の大きな接続孔になると、その内部にはいわゆ
るシャドウィング効果のため配線材料が入って行けず、
接続孔の底部や側壁でのステップカバレッジ特性に劣っ
ていた。この様子を従来のスパッタリング法における接
続孔への配線材料のステップカバレッジを示す断面図で
ある第７図、および同じく接続孔部分のシャドウィング
効果の説明図である第８図に基づき説明する。However, even in the conventional sputtering method, when a contact hole has a large aspect ratio, the wiring material cannot enter inside the hole due to the so-called shadowing effect.
The step coverage characteristics at the bottom and side walls of the connection hole were poor. This situation will be explained based on FIG. 7, which is a cross-sectional view showing the step coverage of the wiring material to the connection hole in the conventional sputtering method, and FIG. 8, which is also a diagram illustrating the shadowing effect in the connection hole portion.
第７図ａは、平行平板型等従来の通常のスパッタリング
法におけるステップカバレッジである。FIG. 7a shows step coverage in a conventional conventional sputtering method such as a parallel plate type sputtering method.
同図に示される通り、接続孔３部分の配線材料４のステ
ップカバレッジは悪く、埋め込み特性が良くない。この
原因の一つは、ターゲットの直径が基体の直径に比べて
大きいため、ターゲットからスパッタリングされた配線
材料の粒子、すなわち原子またはその集合体であるクラ
スタの、基体への斜め入射成分が多いことにある。また
他の原因として、スパッタリング法におけるアルゴン（
Ａｒ）等のスパッタリングガス圧力が通常、例えば数ｍ
Ｔｏｒｒと比較的高いことがあげられる。このため、ス
パッタリングされた配線材料の粒子の空間における平均
自由行程が小さい。すなわち、粒子はスパッタリングガ
スと衝突を繰り返しながら、基体表面へ入射することに
なる。これら二つの原因は換言すれば、基体面垂直方向
に対する粒子の入射角度をαとした場合、このαの値が
０°以上９０゜未満の広い範囲に分布すということであ
る。例えばα−３０°の粒子に着目すると、第８図に示
すごとく、接続孔の斜線を施した部分には粒子は入射し
にくく、斜線が重なった部分にはほとんど入射しない。As shown in the figure, the step coverage of the wiring material 4 in the connection hole 3 portion is poor, and the embedding characteristics are not good. One of the reasons for this is that because the diameter of the target is larger than the diameter of the substrate, there are many particles of the wiring material sputtered from the target, that is, atoms or clusters that are aggregates thereof, that are incident obliquely on the substrate. It is in. Another cause is argon (
The sputtering gas pressure such as Ar) is usually several meters, for example.
Torr is relatively high. Therefore, the mean free path in space of the particles of the sputtered wiring material is small. That is, the particles enter the substrate surface while repeatedly colliding with the sputtering gas. In other words, these two causes mean that, when α is the incident angle of particles relative to the direction perpendicular to the substrate surface, the value of α is distributed over a wide range of 0° to less than 90°. For example, focusing on particles at α-30°, as shown in FIG. 8, particles are difficult to enter the hatched portion of the connection hole, and almost never enter the hatched portion.
このシャドウィング効果につき、更に接続孔への配線材
料のステップカバレッジの粒子入射角度依存性のシミュ
レーション図である第５図を参照して説明する。同図す
は前記αがＯｏから６０ｍまで分布している、スパッタ
リング法を想定した場合である。同図に見られる通り、
接続孔への配線材料のステップカバレッジは悪（、先に
述べた第７図ａの結果と良い一致が得られた。This shadowing effect will be further explained with reference to FIG. 5, which is a simulation diagram of the dependence of the step coverage of the wiring material on the connection hole on the particle incident angle. The figure shows a case where the sputtering method is assumed, in which the α is distributed from Oo to 60 m. As seen in the same figure,
The step coverage of the wiring material to the connection hole was poor (although good agreement was obtained with the results shown in FIG. 7a described above).
前記した通常のスパッタリング法での埋め込み特性の悪
さを改良する方法として、基体に負のＤＣバイアス電圧
またはＲＦバイアス電圧を印加しながらスパッタリング
を行うバイアススパッタリング法、基体を加熱しながら
成膜する高温スパッタリング法あるいはこの両方法を併
用する高温バイアススパッタリング法がある（例えば発
明者らによる総説、月刊Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ
Ｗｏｒｌｄ誌、１９８８年２月号、Ｐ、７７参照）。As methods for improving the poor embedding characteristics of the above-mentioned normal sputtering method, there are two methods: bias sputtering, in which sputtering is performed while applying a negative DC bias voltage or RF bias voltage to the substrate, and high-temperature sputtering, in which a film is formed while heating the substrate. There is a high-temperature bias sputtering method that uses a method or a combination of both methods (for example, a review by the inventors, Monthly Sem1conductor).
(See World magazine, February 1988 issue, p. 77).
これらの方法は、いずれも基体上に堆積したＡＩやＡｌ
を主体とした合金等の配線材料の再スパツタリングや、
あるいは熱エネルギーによる表面マイグレーションを促
進して、埋め込み特性を改善して平坦化を達成しようと
いうものである。These methods all remove AI or Al deposited on the substrate.
Re-sputtering of wiring materials such as alloys mainly based on
Alternatively, the idea is to promote surface migration using thermal energy to improve the embedding characteristics and achieve planarization.
しかし、これらの改良方法を用いても、アスペクト比が
１以上の接続孔になると、孔内部へ入射する配線材料粒
子の量が不足し、第７図すに示すごとく接続孔内部に空
隙を残したまま、堆積膜の表面のみが連結してしまう。However, even if these improvement methods are used, when a connection hole has an aspect ratio of 1 or more, the amount of wiring material particles entering the hole is insufficient, leaving a void inside the connection hole as shown in Figure 7. As a result, only the surfaces of the deposited films are connected.
この状態になると、接続孔部分でのエレクトロマイグレ
ーションや断線の発生等、多層配線の信幀性が極端に低
下する。In this state, the reliability of the multilayer wiring is extremely reduced due to occurrence of electromigration and disconnection in the connection hole portion.
従って、本発明の課題は、半導体等の基体上に形成され
た接続孔へのステップカバレッジに優れた、ＡＩまたは
ＡＩを主体とする合金からなる配線材料による、多層配
線形成方法を提供することである。Therefore, an object of the present invention is to provide a method for forming multilayer wiring using a wiring material made of AI or an alloy mainly composed of AI, which has excellent step coverage to connection holes formed on a substrate such as a semiconductor. be.
前記課題について研究を重ねた結果、本発明者らは、接
続孔内部へのステップカバレッジは、基体への粒子の垂
直入射成分の多い真空蒸着法がスパッタリング法に比べ
て優れているとの計算結果を得るに至った。このシミュ
レーション結果を第５図ａに示す。同図はαがＯｏから
１０’までの狭い範囲に分布している場合のステップカ
バレッジであり、垂直入射成分の多い真空蒸着法を想定
したものである。ここで見られる通り、真空蒸着法によ
る接続孔への配線材料のステップカバレッジは、先に述
べた第５図すのスパッタリング法のシミュレーション結
果に比べて良好である。As a result of repeated research on the above-mentioned problem, the present inventors have calculated that the vacuum evaporation method, in which there is a large number of particles perpendicularly incident on the substrate, is superior to the sputtering method in terms of step coverage inside the connection hole. I ended up getting this. The simulation results are shown in FIG. 5a. The figure shows step coverage when α is distributed in a narrow range from Oo to 10', assuming a vacuum evaporation method with many normal incidence components. As seen here, the step coverage of the wiring material to the connection hole by the vacuum evaporation method is better than the simulation results of the sputtering method shown in FIG. 5 described above.
すなわち、本発明による多層配線形成方法は、接続孔を
有する半導体等の基体にＡＩまたはＡｌを主体とする合
金からなる配線材料を真空蒸着すると同時に、堆積膜の
ステップカバレッジを確実なちとするため、基体を４５
０℃以上ＡＩまたはＡｌを主体とする合金の融点以下に
加熱しながら、前記真空蒸着を行うものである。That is, in the multilayer wiring forming method according to the present invention, a wiring material made of AI or an alloy mainly composed of Al is vacuum-deposited on a substrate such as a semiconductor having contact holes, and at the same time, in order to ensure step coverage of the deposited film, 45 base
The vacuum evaporation is performed while heating to a temperature of 0° C. or higher and lower than the melting point of the alloy mainly composed of AI or Al.
基体の加熱温度は、４５０℃未満では接続孔部分での配
線材料の堆積膜のステップカバレッジが充分でなく、一
方、配線材料の融点を越えると、液体となった配線材料
の表面張力や粘性流動のため平坦性が悪化し、共に本発
明の効果を発揮することができない。If the heating temperature of the substrate is lower than 450°C, the step coverage of the deposited film of the wiring material in the connection hole portion will not be sufficient, whereas if it exceeds the melting point of the wiring material, the surface tension and viscous flow of the liquid wiring material will occur. Therefore, the flatness deteriorates, and the effects of the present invention cannot be exhibited.
基体の加熱方法は、特に限定されるものではないが、例
えば抵抗加熱ヒータによる方法、ハロゲンランプやアー
クランプ照射による方法等が用いられる。The method of heating the substrate is not particularly limited, but for example, a method using a resistance heater, a method using irradiation with a halogen lamp or an arc lamp, etc. are used.
真空蒸着装置は、これも特に限定されるものではな（、
例えば抵抗加熱、電子ビーム加熱、高周波加熱等の手段
によりＡ１またはＡＩを主体とする合金からなる配線材
料を蒸発させる装置が用いられる。真空蒸着時のチャン
バ内圧力は、通常の真空蒸着で用いられる真空度で充分
であり、−例として１０− ’Ｔｏｒｒであれば良い。The vacuum evaporation equipment is not particularly limited either (
For example, an apparatus is used that evaporates a wiring material made of an alloy mainly composed of A1 or AI by means of resistance heating, electron beam heating, high frequency heating, or the like. The pressure inside the chamber during vacuum evaporation is sufficient to be the degree of vacuum used in normal vacuum evaporation, and may be, for example, 10' Torr.
要は配線材料の蒸発粒子の平均自由行程が大きく、基体
に対する垂直入射成分がスパッタリング法に比べて充分
大きな割合を占めるような真空度ならば良いのであり、
本発明の効果を損なわない範囲内で、任意に選定するこ
とが可能である。In short, the degree of vacuum is sufficient as long as the mean free path of the evaporated particles of the wiring material is large and the normal incidence component to the substrate accounts for a sufficiently large proportion compared to the sputtering method.
It can be arbitrarily selected within a range that does not impair the effects of the present invention.
真空蒸着法は、蒸発源の面積が基体の面積に比べて小さ
い、また堆積膜形成時のチャンバ内の真空度は例えば１
０− ’Ｔｏｒｒとスパッタリング法と比較してはるか
に高真空度であり、このため蒸発源からの粒子の平均自
由行程が大きく、基体面垂直方向に対する粒子の入射角
度αが小さい。すなわち基体面への粒子の垂直入射成分
が多い。よって基体面に垂直に形成された深い接続孔の
底部にも容易に配線材料の粒子が入射でき、接続孔の内
部に配線材料を堆積することができる。In the vacuum evaporation method, the area of the evaporation source is small compared to the area of the substrate, and the degree of vacuum in the chamber during deposition film formation is, for example, 1.
The degree of vacuum is much higher than that of the sputtering method at 0-' Torr, and therefore the mean free path of the particles from the evaporation source is large, and the incident angle α of the particles with respect to the direction perpendicular to the substrate surface is small. That is, there are many components of particles that are perpendicularly incident on the substrate surface. Therefore, particles of the wiring material can easily enter the bottom of the deep connection hole formed perpendicular to the base surface, and the wiring material can be deposited inside the connection hole.
さらに基体を４５０℃以上ＡＩまたはＡＩを主体とする
合金からなる配線材料の融点以下に加熱する方法を併用
しているので、堆積した配線材料の表面マイグレーシヨ
ンが同時に行われ、堆積膜のステップカバレッジはさら
に優れたものとなる。Furthermore, since a method of heating the substrate to 450°C or higher and below the melting point of the wiring material made of AI or an alloy mainly composed of AI is used, surface migration of the deposited wiring material is performed at the same time, resulting in step coverage of the deposited film. becomes even better.
以上の作用により、半導体等の基体上の深い接続孔をＡ
ＩまたはＡＩを主体とする合金からなる配線材料で埋め
込む多層配線形成方法において、接続孔への埋め込み特
性に優れ、しかも接続孔部分の配線材料堆積膜表面の平
坦性の良いステップカバレッジに優れた多層配線の形成
が可能となる。Due to the above action, deep connection holes on substrates such as semiconductors can be
In a multilayer wiring formation method in which wiring material is filled with a wiring material made of an alloy mainly composed of I or AI, the multilayer wiring has excellent embedding characteristics in connection holes and excellent step coverage with good flatness of the surface of the wiring material deposited film in the connection hole portion. It becomes possible to form wiring.
以下、本発明の実施例につき図面を参照しながら説明を
加える。Hereinafter, embodiments of the present invention will be explained with reference to the drawings.
裏施皿土
シリコン等の基体１に例えばＣＶＤ法により酸化シリコ
ン（ＳｉＯ□）からなる絶縁膜２を約０．８３μｍの厚
さに形成したのち、ここに直径約０．４３μｍ、アスペ
クト比約１．９の接続孔３を開口する。After forming an insulating film 2 made of silicon oxide (SiO□) to a thickness of about 0.83 μm on a substrate 1 made of silicon or the like using a CVD method, a film with a diameter of about 0.43 μm and an aspect ratio of about 1 is formed. .9 connection hole 3 is opened.
次に本発明の第１の実施例による多層配線形成方法を示
す概略断面図である第１図のごとく、前記基体１を真空
蒸着装置１１のチャンバ内のヒータブロック５に密着し
て設置し、ｓｏｏ”ｃに加熱する。Next, as shown in FIG. 1, which is a schematic cross-sectional view showing the multilayer wiring forming method according to the first embodiment of the present invention, the base 1 is placed in close contact with the heater block 5 in the chamber of the vacuum evaporation apparatus 11, Heat to soo”c.
チャンバ内圧力は、真空ポンプ１０により例えば１０−
ｂＴｏｒｒに減圧する。純度ファイブナインの高純度
ＡＩを電子ビーム９の照射によりハース８内で溶解し、
蒸発源７とする。なお、蒸発源７から基体１を臨む見込
み角度αは略１０°以内となるようにした。The pressure inside the chamber is set to, for example, 10 - by the vacuum pump 10.
Reduce pressure to bTorr. High-purity AI with a purity of five nines is melted in the hearth 8 by irradiation with an electron beam 9,
Let it be evaporation source 7. Note that the expected angle α of the substrate 1 from the evaporation source 7 was set to within approximately 10°.
なお、この見込み角度は、前述した基体面垂直方向に対
する粒子の入射角度と実質的に同一である。Note that this angle of view is substantially the same as the incident angle of the particles with respect to the direction perpendicular to the substrate surface described above.
以上の方法により、基体ｌ上に高純度旧からなる配線材
料４を真空蒸着し接続孔３への埋め込みを行った。この
結果を、本発明の実施例による接続孔への配線材料のス
テップカバレッジを示す断面図である第３図に基づいて
説明する。同図に示されるようにアスペクト比約１．９
の接続孔３内部は高純度ＡＩからなる配線材料４により
充分に埋め込まれており、堆積した配線材料４の表面の
平坦性もよく、ステップカバレッジに優れたものであっ
た。By the method described above, the wiring material 4 made of high-purity copper was vacuum-deposited on the substrate 1 and filled into the connection hole 3. The results will be explained based on FIG. 3, which is a cross-sectional view showing the step coverage of the wiring material to the connection hole according to the example of the present invention. As shown in the figure, the aspect ratio is approximately 1.9.
The inside of the contact hole 3 was sufficiently filled with the wiring material 4 made of high-purity AI, and the surface of the deposited wiring material 4 had good flatness and excellent step coverage.
叉脂斑主
第２図は本発明の第２の実施例による多層配線形成方法
を示す概略断面図である。本実施例では、基体Ｉの直径
りが実施例Ｉよりも大きい基体に、均一な真空蒸着を施
す場合について述べる。Figure 2 is a schematic cross-sectional view showing a method for forming multilayer wiring according to a second embodiment of the present invention. In this example, a case will be described in which uniform vacuum deposition is performed on a substrate whose diameter is larger than that in Example I.
本実施例による多層配線形成方法は、前記実施例１に準
拠しており、次の３つの点においてのみ実施例１と相違
している。The multilayer wiring forming method according to this embodiment is based on the first embodiment, and differs from the first embodiment only in the following three points.
１、基体ｌをヒータブロック５に密着設置したまま、回
転軸６を中心として、真空蒸着が行われている間回転さ
せる。1. The substrate 1 is placed in close contact with the heater block 5 and rotated about the rotating shaft 6 while vacuum deposition is being performed.
２、回転軸６と、蒸発源７の中心部にたてた垂線との距
離が、基体１の直径りの略２となる位置に、蒸発源７の
位置を第２図のごとくずらす。2. The position of the evaporation source 7 is shifted to a position where the distance between the rotating shaft 6 and a perpendicular line drawn to the center of the evaporation source 7 is approximately 2 the diameter of the base 1, as shown in FIG.
３、遮蔽板１２を配設し、真空蒸着中の基体１の略半分
が蒸発源７から隠れるようにする。すなわち、蒸発源７
からの見込み角度が略１０’以内となる基体１部分にの
み、真空蒸着が行われるように装置を構成する。3. A shielding plate 12 is provided so that approximately half of the substrate 1 during vacuum evaporation is hidden from the evaporation source 7. That is, evaporation source 7
The apparatus is configured so that vacuum deposition is performed only on a portion of the substrate 1 whose viewing angle is within approximately 10'.
以上説明した真空蒸着装置により、実施例１で述べた方
法に準じて、基体１上に貰純度ＡＩからなる配線材料４
を真空蒸着し、接続孔３への埋め込みを行った。本実施
例による結果は、同じく第３図に示される通りであり、
広い基体１全面にわたり接続孔３内へ配線材料４が良好
に埋め込まれており、堆積した配線材料４の表面の平坦
性もよく、ステップカバレッジに優れていた。なお、遮
蔽板１２はこれを設けなくても接続孔３内への埋め込み
特性は充分に良好であったが、遮蔽板１２を設けて、蒸
発源７から基体１を臨む見込み角度αを略１０゜以内に
制限することによって、大きな直径りを有する基体ｌの
全面にわたり、より良好な配線材料の埋め込みが可能と
なる。Using the vacuum evaporation apparatus described above, according to the method described in Example 1, a wiring material 4 made of high-purity AI is deposited on the substrate 1.
was vacuum-deposited and filled into the connection hole 3. The results of this example are as shown in FIG.
The wiring material 4 was well embedded into the connection hole 3 over the entire surface of the wide base 1, and the surface of the deposited wiring material 4 had good flatness and excellent step coverage. Note that the characteristics of embedding the shielding plate 12 into the connection hole 3 were sufficiently good even without providing the shielding plate 12; By limiting the diameter to within 100°, it is possible to better embed the wiring material over the entire surface of the substrate l having a large diameter.
本実施例による方法は、ヒータブロック５に小さな直径
を有する基体を複数個設置し、各基体に均一な真空蒸着
を施して配線材料を埋め込む場合にも、優れた効果を発
揮した。The method according to the present example also exhibited excellent effects when a plurality of substrates having small diameters were installed in the heater block 5 and wiring material was embedded in each substrate by uniform vacuum deposition.
１３および ゞ
本実施例３においては、基体加熱温度を４５０″Ｃおよ
び５５０℃に選び、一方比較例においては基体加熱温度
を４００℃および基体加熱なしで略室温のまま真空蒸着
を行った。その他真空蒸着装置および真空蒸着の方法は
、実施例１に準拠した。13 and ゞIn Example 3, the substrate heating temperature was selected to be 450''C and 550°C, while in the comparative example, the substrate heating temperature was 400°C, and vacuum deposition was performed at approximately room temperature without substrate heating.Others The vacuum evaporation device and the vacuum evaporation method were based on Example 1.
以上述べた実施例３および比較例による多層配線形成方
法の結果を、先に述べた実施例１および実施例２の結果
とあわせて、接続孔への配線材料の埋め込みにおける基
体加熱温度と平坦度の関係図である第４図に示す。同図
において平坦度とは、接続孔３の深さをｄｌ、接続孔部
分の配線材料４の堆積層の凹みの深さをｄ２とした場合
、１ ｄｉ／ｄ＋で定義される値を意味するものとす
る。つまり、平坦度１が完全な平坦性をもった埋め込み
が行われ、ステップカバレッジに優れていることを意味
し、平坦度０ではｄ、−ｄｔであり、平坦化の効果がほ
とんど得られないことを意味する。この平坦度が略０．
９以上あれば、多層配線形成における接続孔の平坦性に
優れたステップカバレッジの良い埋め込みが達成された
と考えられる。The results of the multilayer wiring forming method according to Example 3 and Comparative Example described above are combined with the results of Example 1 and Example 2 described above to determine the substrate heating temperature and flatness when embedding the wiring material into the connection hole. This is shown in FIG. 4, which is a relationship diagram. In the figure, flatness means a value defined by 1 di/d+, where dl is the depth of the connection hole 3 and d2 is the depth of the depression in the deposited layer of the wiring material 4 in the connection hole portion. shall be taken as a thing. In other words, a flatness of 1 means that embedding is performed with perfect flatness and excellent step coverage, while a flatness of 0 means d, -dt, which means that almost no flattening effect is obtained. means. This flatness is approximately 0.
If it is 9 or more, it is considered that filling with good step coverage and excellent flatness of contact holes in multilayer wiring formation has been achieved.
第４図に見られる通り、基体加熱温度４５０℃以上で平
坦度０．９以上が達成されており、接続孔内部における
空隙も観察されなかった。基体加熱温度５００℃以上で
は、平坦度１．０と完全平坦化が達成されている。平坦
化の効果は、第４図には５５０℃までしか示していない
が、純ＡＩの融点である６６０℃に至るまで平坦度が略
１．０と優れた値を示した。しかし融点を越えると、基
体１上に堆積した配線材料４は液体として存在するため
、その表面張力と粘性流動のため凝集塊を形成する傾向
が表れ、本発明の効果を達成することができなかった。As seen in FIG. 4, a flatness of 0.9 or higher was achieved at a substrate heating temperature of 450° C. or higher, and no voids were observed inside the connection holes. At a substrate heating temperature of 500° C. or higher, complete flatness with a flatness of 1.0 is achieved. Although the flattening effect is only shown up to 550° C. in FIG. 4, the flatness showed an excellent value of approximately 1.0 up to 660° C., which is the melting point of pure AI. However, when the melting point is exceeded, the wiring material 4 deposited on the substrate 1 exists as a liquid, and therefore tends to form aggregates due to its surface tension and viscous flow, making it impossible to achieve the effects of the present invention. Ta.
このＩＦＲＩＮは、純Ａ１に限らず、配線材料としてＡ
Ｉを主体とした合金、すなわちＡＩ−Ｃｕ（銅）合金、
＾１−Ｓｉ （シリコン）合金等においても、融点の値
は若干具なるものの、同じ結果を示した。This IFRIN is not limited to pure A1, but can also be used as a wiring material.
I-based alloy, i.e. AI-Cu (copper) alloy,
The same results were obtained for ^1-Si (silicon) alloys, etc., although the melting point values were slightly different.
一方、同じく第４図に示されるごとく、基体加熱温度が
４５０℃に満たない比較例においては、平坦度は０．９
未満の値に急激に低下し、やはり本発明の目的を達成す
ることができなかった。特に基体加熱をせず、略室温で
真空蒸着を行った場合は、比較例による接続孔への配線
材料のステップカバレッジを示す断面図である第６図に
示されるように、接続孔３内部に大きな空隙が存在した
。これは基体加熱と真空蒸着法とを併用するときのみに
得られる本発明による多層配線形成方法の優れた効果を
立証するものである。On the other hand, as shown in FIG. 4, in the comparative example where the substrate heating temperature was less than 450°C, the flatness was 0.9.
As a result, the object of the present invention could not be achieved. In particular, when vacuum deposition is performed at approximately room temperature without heating the substrate, the inside of the connection hole 3 is A large void existed. This proves the excellent effect of the multilayer wiring forming method according to the present invention, which can be obtained only when substrate heating and vacuum evaporation are used together.
以上、本発明の実施例について説明を加えたが、本発明
の趣旨は、接続孔を有する基体を４５０℃以上ＡＩまた
はＡＩを主体とする合金からなる配線材料の融点以下に
加熱しながら、該配線材料の真空蒸着を行うことに特徴
がある。この際、蒸発源からの基体被蒸着部分を臨む見
込み角度は、略１０°以内にとどめることが望ましい。Although the embodiments of the present invention have been described above, the gist of the present invention is to heat the substrate having connection holes to 450°C or higher and lower than the melting point of the wiring material made of AI or an alloy mainly composed of AI. The feature is that the wiring material is vacuum evaporated. At this time, it is desirable that the viewing angle from the evaporation source toward the portion of the substrate to be evaporated is kept within approximately 10 degrees.
しかし、真空蒸着装置内への基体収容枚数や基体直径の
大型化の趨勢に鑑みて、工業的実用化の見地からは、こ
の見込み角度の値は特に制限を加えるものではな（、本
発明の効果を損なわない範囲内で任意に選定することが
可能である。However, in view of the trend of increasing the number of substrates accommodated in a vacuum evaporation apparatus and the diameter of the substrate, from the viewpoint of industrial practical application, the value of this angle of view is not particularly limited (the present invention It can be arbitrarily selected within a range that does not impair the effect.
以上詳述した通り、半導体等からなる基体上に形成され
た接続孔をＡＩまたはＡＩを主体とする合金からなる配
線材料で埋め込む多層配線形成方法において、基体を４
５０℃以上該配線材料の融点以下に加熱しながら配線材
料を真空蒸着することにより、接続孔への埋め込み特性
に優れ、しかも接続孔部分の配線材料堆積膜表面の平坦
性の良いステップカバレッジに優れた多層配線の形成が
可能となった。As detailed above, in the multilayer wiring forming method in which contact holes formed on a substrate made of a semiconductor or the like are filled with wiring material made of AI or an alloy mainly composed of AI, the substrate is
By vacuum-depositing the wiring material while heating it to a temperature above 50°C and below the melting point of the wiring material, it has excellent embedding characteristics in the connection hole, and also has excellent step coverage with good flatness of the surface of the wiring material deposited film in the connection hole area. It became possible to form multilayer wiring.
本発明によれば、従来の通常のスパッタリング法はもと
より、バイアススパッタリング法等、ステップカバレッ
ジに優れているとされていた方法によっても困難であっ
た、アスペクト比が１を越える接続孔をも良好に埋め込
むことが可能となる。According to the present invention, connection holes with an aspect ratio exceeding 1 can be formed successfully, which has been difficult not only with conventional sputtering methods but also with methods that are considered to have excellent step coverage, such as bias sputtering methods. It becomes possible to embed it.
しかも接続孔内部の配線材料に空隙が存在することもな
く、エレクトロマイグレーションや断線の懸念のない信
頼性に冨んだ多層配線の形成が可能となり、半導体装置
製造工程における本発明の寄与は大きい。In addition, there are no voids in the wiring material inside the contact hole, making it possible to form highly reliable multilayer wiring without concerns about electromigration or disconnection, and the present invention greatly contributes to the semiconductor device manufacturing process.
第１図は本発明の第１の実施例による多層配線形成方法
を示す概略断面図、第２図は本発明の第２の実施例によ
る多層配線形成方法を示す概略断面図、第３図は本発明
の実施例による接続孔への配線材料のステップカバレッ
ジを示す断面図、第４図は接続孔への配線材料の埋め込
みにおける基体加熱温度と平坦度の関係図、第５図は接
続孔への配線材料のステップカバレッジの粒子入射角度
依存性のシミュレーション図、第６図は比較例による接
続孔への配線材料のステップカバレッジを示す断面図、
第７図は従来のスパッタリング法における接続孔への配
線材料のステップカバレッジを示す断面図、そして第８
図は従来のスパッタリング法における接続孔部分のシャ
ドウィング効果の説明図である。
１・・・−・−一−−−−−−基体
２−−−−−−−−−−−−一絶縁膜
３−・−一−−−−・・−・−接続孔
４− ・配線材料
５−・−・−−一−−−・−ヒータブロック７・・−・
−−−一−−−一−−蒸発源本発明の第１の実施例１：
：Ｊ：る
多層配線形域方法玉示す椰賂頚面図
本発明の実施例にＪる接続孔への
配線材料のステップカバレッジと示す断面口筒３図
７１ １冒本η０熟泪υ文（℃）接続孔へ
の配線材料の埋めこみにおける
基体加熱温度と平土踪の関係図
第４叉
本発明の第２の実施例による
多層配線形成衣ラムと示す砥路断面回
ａ、α＝ａ′Ｎｉａ° ｂ、ｃＣ＝０’−６
０’揚続孔への配線材料のステップカバレッジの粒子入
射角度依存ｌ庄のシミュレーション図“第５図
比較例による接続ｊしへの配線材料の
ステップ乃ノ〈レッジと示す断面図
第６図FIG. 1 is a schematic sectional view showing a method for forming multilayer wiring according to a first embodiment of the present invention, FIG. 2 is a schematic sectional view showing a method for forming multilayer wiring according to a second embodiment of the invention, and FIG. A cross-sectional view showing the step coverage of the wiring material into the connection hole according to an embodiment of the present invention, FIG. 4 is a diagram showing the relationship between substrate heating temperature and flatness in embedding the wiring material into the connection hole, and FIG. 5 shows the step coverage of the wiring material into the connection hole. Fig. 6 is a cross-sectional view showing the step coverage of the wiring material to the connection hole according to a comparative example;
Figure 7 is a cross-sectional view showing the step coverage of wiring material to contact holes in the conventional sputtering method;
The figure is an explanatory diagram of the shadowing effect of the connection hole portion in the conventional sputtering method. 1...---1--Base 2--Insulating film 3--1--Connection hole 4-- Wiring material 5-----1---Heater block 7...
---1--1--Evaporation source First embodiment of the present invention 1:
: J: A cross-sectional view showing the step coverage of the wiring material to the connection hole in the embodiment of the present invention. ℃) Relationship diagram between substrate heating temperature and flat surface during embedding of wiring material into the connection hole 4th cross-sectional diagram of the grinding path showing the multilayer wiring forming coat ram according to the second embodiment of the present invention, α=a' Nia° b, cC=0'-6
Figure 5 is a simulation diagram showing the dependence of the step coverage of the wiring material on the 0' lift hole on the particle incident angle.
Claims (1)
ミニウムを主体とした合金からなる配線材料を埋め込む
多層配線形成方法であって、基体を４５０℃以上前記配
線材料の融点以下に加熱しながら、該配線材料を真空蒸
着することを特徴とする多層配線形成方法。A multilayer wiring forming method in which a wiring material made of aluminum or an aluminum-based alloy is embedded in a connection hole formed on a substrate, the wiring being heated to a temperature of 450° C. or more and below the melting point of the wiring material. A multilayer wiring formation method characterized by vacuum evaporation of materials.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1091829A JP2832990B2 (en) | 1989-04-13 | 1989-04-13 | Multilayer wiring forming method and vacuum deposition apparatus used for the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1091829A JP2832990B2 (en) | 1989-04-13 | 1989-04-13 | Multilayer wiring forming method and vacuum deposition apparatus used for the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02271634A true JPH02271634A (en) | 1990-11-06 |
| JP2832990B2 JP2832990B2 (en) | 1998-12-09 |
Family
ID=14037494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1091829A Expired - Fee Related JP2832990B2 (en) | 1989-04-13 | 1989-04-13 | Multilayer wiring forming method and vacuum deposition apparatus used for the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2832990B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5525158A (en) * | 1992-10-26 | 1996-06-11 | Mitsubishi Denki Kabushiki Kaisha | Thin film deposition apparatus |
| JP2002151438A (en) * | 2000-09-04 | 2002-05-24 | Nippon Soken Inc | Method of manufacturing semiconductor device |
| WO2017081798A1 (en) * | 2015-11-12 | 2017-05-18 | 株式会社島津製作所 | Semiconductor device and semiconductor detector, methods for manufacturing same, and semiconductor chip or substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63287019A (en) * | 1987-05-19 | 1988-11-24 | Nec Corp | Manufacture of semiconductor device |
| JPS6474739A (en) * | 1987-09-17 | 1989-03-20 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1989
- 1989-04-13 JP JP1091829A patent/JP2832990B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63287019A (en) * | 1987-05-19 | 1988-11-24 | Nec Corp | Manufacture of semiconductor device |
| JPS6474739A (en) * | 1987-09-17 | 1989-03-20 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5525158A (en) * | 1992-10-26 | 1996-06-11 | Mitsubishi Denki Kabushiki Kaisha | Thin film deposition apparatus |
| JP2002151438A (en) * | 2000-09-04 | 2002-05-24 | Nippon Soken Inc | Method of manufacturing semiconductor device |
| WO2017081798A1 (en) * | 2015-11-12 | 2017-05-18 | 株式会社島津製作所 | Semiconductor device and semiconductor detector, methods for manufacturing same, and semiconductor chip or substrate |
| JPWO2017081798A1 (en) * | 2015-11-12 | 2018-08-30 | 株式会社島津製作所 | Semiconductor device, semiconductor detector and manufacturing method thereof, semiconductor chip or substrate |
| US10468365B2 (en) | 2015-11-12 | 2019-11-05 | Shimadzu Corporation | Semiconductor device and semiconductor detector, methods for manufacturing same, and semiconductor chip or substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2832990B2 (en) | 1998-12-09 |
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