JPH02265271A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH02265271A JPH02265271A JP1087527A JP8752789A JPH02265271A JP H02265271 A JPH02265271 A JP H02265271A JP 1087527 A JP1087527 A JP 1087527A JP 8752789 A JP8752789 A JP 8752789A JP H02265271 A JPH02265271 A JP H02265271A
- Authority
- JP
- Japan
- Prior art keywords
- word line
- layer
- sections
- impurity
- word
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000000463 material Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- 229920005591 polysilicon Polymers 0.000 abstract description 16
- 238000009792 diffusion process Methods 0.000 abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体メモリ装置に関し、特にワード線の抵抗
低減のための高導電層をワード線上に存しこの高導電層
とワード線とのコンタクト（以下［つり上げコンタクト
Ｊと称する）をメモリセル・アレイに有する集積メモリ
装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device in which a highly conductive layer is provided on a word line to reduce resistance of the word line, and a contact between the highly conductive layer and the word line is provided. (hereinafter referred to as lifting contacts J) in a memory cell array.
メモリセルのトランスファゲート・トランジスタのゲー
トに比較的高比抵抗の材料（たとえばポリシリコン）を
用いた半導体メモリ装置では、第４図に示すようにゲー
トポリシリコンでワード線も構成されるためワード線６
の抵抗が高く、ワード線の末端に向うほど時定数が大き
くなって動作に遅延が生じる。この欠点を除去するため
、従来からワード線に重ねて上層にアルミニウム等の高
導電層５を形成し、メモリセルアレイ内の各所のセル部
間につり上げコンタクト部を設けてそこでゲートポリシ
リコンロとの接続を行なう（コンタクト１）ことにより
、所定の動作時間におさえる工夫がされていた。さらに
従来、拡散工程内に含まれる高ドーズイオン注入時に発
生ずるチャージアップによるゲート酸化膜の絶縁破壊を
避けるため、セルアレイ外部にＮ＋拡散層３を形成し、
これをゲートポリシリコンロと接続することにより、基
板とＮ＋拡散層の間で形成されるダイオードの耐圧以上
の電圧がゲートポリシリコンと基板の間（特にゲート酸
化膜）に印加されることを防ぐことも、上記つり上げコ
ンタクトとは別になされることもあった。In a semiconductor memory device that uses a relatively high resistivity material (for example, polysilicon) for the transfer gate of a memory cell or the gate of a transistor, the word line is also made of gate polysilicon, as shown in Figure 4. 6
The resistance of the word line is high, and the time constant increases toward the end of the word line, causing a delay in operation. In order to eliminate this drawback, conventionally, a highly conductive layer 5 made of aluminum or the like is formed as an upper layer over the word line, and lifting contact portions are provided between cell portions at various locations in the memory cell array. By making the connection (contact 1), an attempt was made to keep the operation time within a predetermined time. Furthermore, conventionally, in order to avoid dielectric breakdown of the gate oxide film due to charge-up that occurs during high-dose ion implantation included in the diffusion process, an N+ diffusion layer 3 is formed outside the cell array.
By connecting this to the gate polysilicon, a voltage higher than the withstand voltage of the diode formed between the substrate and the N+ diffusion layer is prevented from being applied between the gate polysilicon and the substrate (especially to the gate oxide film). This was sometimes done separately from the above-mentioned lifting contact.
上述した従来の半導体装置では高ドーズイオン注入時に
発生するチャージアップによるゲート酸化膜の絶縁破壊
を防ぐ目的で設けられる基板と逆導電型の不純物拡散層
を、第４図に示すようにセルブロック外部に形成するた
め、メモリセルアレイ外にそのための余分な面積が必要
であり、チップ面積の増大をまねいていた。In the conventional semiconductor device described above, an impurity diffusion layer of the opposite conductivity type to the substrate, which is provided for the purpose of preventing dielectric breakdown of the gate oxide film due to charge-up that occurs during high-dose ion implantation, is placed outside the cell block as shown in Figure 4. Therefore, an extra area is required outside the memory cell array, leading to an increase in the chip area.
本発明は、チャージアップを避けるための基板と反対導
電型の不純物層をセルブロック間に形成しているワード
線のつり上げコンタクト部の下に設け、つり上げコンタ
クト部の下でワード線を不純物層に接続する構造を有す
ることを特徴とする。In the present invention, an impurity layer of the opposite conductivity type to that of the substrate is provided under the lifting contact portion of the word line formed between cell blocks to avoid charge-up, and the word line is formed in the impurity layer under the lifting contact portion. It is characterized by having a connecting structure.
次に、本発明について図面を参照して説明する。第１図
および第２図を参照すると、本発明の第１の実施例では
メモリセルトランジスタのゲートを兼ねてワード線とし
て図上左右に延びるポリシリコン層６とその上部に重畳
したアルミニウム層５とのワードコンタクト部分１（ワ
ード線のつり上げコンタクト部分）が集中して設けられ
ているセル部とセル部との間のコンタクト部の半導体基
板９（ｐ型）表面にＮ＋拡散不純物層２を集中形成して
いる。各不純物層２はワード線つり上げコンタクト部分
１の直下に配置し、容量ポリシリコン層７を図示のよう
にカット８して、ポリシリコン層６をつり上げコンタク
ト部分１の直下でＮ＋不純物層２に接続している。なお
、セル部の構造は図示を省略したが、従来公知のダイナ
ミックＲＡＭセル構造でよく、例えば基板９上に容量誘
電体層を介して（セル間にあっては厚いフィールド絶縁
層を介して）容量ポリシリコン層を一面に配置しくセル
・トランジスタのゲート部およびビット線接続部を除く
）、セルトランジスタのゲーｌ〜を兼ねるワード線を第
１図のように左右に走らせ（セルトランジスタ中ではゲ
ート絶縁膜上に、容量ポリシリコン層がある部分ではそ
の上に重ねる）、さらにワード線上にビット線（図示せ
ず〉を第１図で上下に走らせて各セルトランジスタの拡
散層にコンタクトさせたものでよい。各セル部には多数
のメモリセルが配置される。Next, the present invention will be explained with reference to the drawings. Referring to FIGS. 1 and 2, in the first embodiment of the present invention, a polysilicon layer 6 which also serves as the gate of a memory cell transistor and extends from left to right in the figure as a word line, and an aluminum layer 5 superimposed on the polysilicon layer 6 are used. An N+ diffused impurity layer 2 is formed in a concentrated manner on the surface of the semiconductor substrate 9 (p-type) in the contact area between the cell parts where word contact parts 1 (word line lifting contact parts) are provided in a concentrated manner. are doing. Each impurity layer 2 is placed directly under the word line lifting contact portion 1, and the capacitive polysilicon layer 7 is cut 8 as shown, and the polysilicon layer 6 is connected to the N+ impurity layer 2 directly under the lifting contact portion 1. are doing. Although the structure of the cell part is not shown, it may be a conventionally known dynamic RAM cell structure, for example, a capacitive polyamide layer is formed on the substrate 9 through a capacitive dielectric layer (through a thick field insulating layer between cells). The silicon layer is placed on one surface (excluding the gate part of the cell transistor and the bit line connection part), and word lines that also serve as gates of the cell transistor are run left and right as shown in Figure 1 (in the cell transistor, the gate insulating film is In some areas where there is a capacitive polysilicon layer, it may be layered on top of the capacitive polysilicon layer), and a bit line (not shown) may be run above and below the word line (not shown) to contact the diffusion layer of each cell transistor. A large number of memory cells are arranged in each cell section.
第３図に示した本発明の第２の実施例では、セル部間の
数ケ所にあるワード線つり上げコンタクト部に設けるＮ
１不純物層４をつり上げコンタクト部−つ置きに設置し
、かつ各つηあげコンタクト部において、ワード線６−
つ置きに不純物層４を設けている。高集積化に伴いワー
ド線が接近して隣り合ったすべてのワード線のつり上げ
コンタクト部分１の下方にＮ＋不純物層を隣接して形成
できない場合、数ケ所のつり上げコンタクト領域を利用
して、Ｎ＋不純物層４を分散させて形成できるという利
点がある。なおこの場合、Ｎ＋不純物層のない部分では
コンタクト１を省略してもよい。In the second embodiment of the present invention shown in FIG.
1 impurity layer 4 is placed every other raised contact part, and in each raised contact part, a word line 6-
Impurity layers 4 are provided alternately. When word lines become closer together with higher integration and it is not possible to form N+ impurity layers adjacently under the lifting contact portions 1 of all adjacent word lines, N+ impurity layers can be formed using several lifting contact regions. There is an advantage that the layer 4 can be formed in a dispersed manner. Note that in this case, the contact 1 may be omitted in the portion where there is no N+ impurity layer.
以上説明したように、本発明においては高ドーズイオン
注入時に発生するチャージアップによるゲート酸化膜の
絶縁破壊を避けるための基板と逆導電型の不純物拡散層
をワード線のつり上げコンタクト部分の下方に形成し、
ワード線との接続をつり上げコンタクト部分の下で行う
構成とすることによってセルアレイ外部に形成していた
不純物拡散層を削除し、チップサイズを１％程度小さく
できる。また、高集積化に伴いワード線が接近し合った
場合でも、複数のワード線のつり上げコンタクト部分を
利、用できるという効果がある。As explained above, in the present invention, an impurity diffusion layer of a conductivity type opposite to that of the substrate is formed below the lifting contact portion of the word line in order to avoid dielectric breakdown of the gate oxide film due to charge-up that occurs during high-dose ion implantation. death,
By configuring the word line to be connected under the raised contact portion, the impurity diffusion layer formed outside the cell array can be eliminated, and the chip size can be reduced by about 1%. Further, even when word lines are brought closer to each other due to higher integration, there is an effect that the lifting contact portions of a plurality of word lines can be used.
第１図は本発明の第１の実施例の一部平面図、第２図は
第１図のＡ−Ａ’線における断面図、第３図は本発明の
第２の実施例の一部平面図、第４図は従来の半導体メモ
リ装置の一部平面図である。
１・・・ワード線つり上げコンタクト、２，３．４・・
・Ｎ＋不純物層、５・・・アルミニウム層、６・・・ゲ
ートポリシリコン層、７・・・容量ポリシリコン層、８
・・・容量ポリシリコン層をカットした部分、９・・・
半導体基板。FIG. 1 is a partial plan view of the first embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA' in FIG. 1, and FIG. 3 is a partial plan view of the second embodiment of the present invention. FIG. 4 is a partial plan view of a conventional semiconductor memory device. 1...Word line lifting contact, 2, 3.4...
・N+ impurity layer, 5... aluminum layer, 6... gate polysilicon layer, 7... capacitive polysilicon layer, 8
...The part where the capacitive polysilicon layer was cut, 9...
semiconductor substrate.
Claims (1)
スファーゲートをも兼ねるワード線と、前記ワード線に
重なるように配置され、かつ一定距離毎に前記ワード線
に接続される低比抵抗導電層とを有する半導体メモリ装
置において、前記ワード線と前記導電層との接続コンタ
クトの下方の半導体基板表面に前記基板とは逆導電型の
不純物層を有し、前記接続コンタクトの下で前記ワード
線が前記不純物層に接続する構造を有することを特徴と
する半導体メモリ装置。a word line formed of a relatively high resistivity material and also serving as a transfer gate of a memory cell; and a low resistivity conductive layer arranged to overlap the word line and connected to the word line at regular intervals. In the semiconductor memory device, an impurity layer of a conductivity type opposite to that of the substrate is provided on a surface of the semiconductor substrate below a connection contact between the word line and the conductive layer, and the word line is connected to the conductive layer under the connection contact. A semiconductor memory device characterized by having a structure connected to an impurity layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1087527A JPH02265271A (en) | 1989-04-05 | 1989-04-05 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1087527A JPH02265271A (en) | 1989-04-05 | 1989-04-05 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02265271A true JPH02265271A (en) | 1990-10-30 |
Family
ID=13917470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1087527A Pending JPH02265271A (en) | 1989-04-05 | 1989-04-05 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02265271A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018525823A (en) * | 2015-08-28 | 2018-09-06 | マイクロン テクノロジー， インク． | Semiconductor device including conductive wire, and method of manufacturing semiconductor device including conductive wire |
-
1989
- 1989-04-05 JP JP1087527A patent/JPH02265271A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018525823A (en) * | 2015-08-28 | 2018-09-06 | マイクロン テクノロジー， インク． | Semiconductor device including conductive wire, and method of manufacturing semiconductor device including conductive wire |
| US10388601B2 (en) | 2015-08-28 | 2019-08-20 | Micron Technology, Inc. | Semiconductor devices including conductive lines and methods of forming the semiconductor devices |
| US10811355B2 (en) | 2015-08-28 | 2020-10-20 | Micron Technology, Inc. | Methods of forming semiconductor devices |
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