JPH02265248A - Manufacture of mos-type transistor - Google Patents
Manufacture of mos-type transistorInfo
- Publication number
- JPH02265248A JPH02265248A JP8569189A JP8569189A JPH02265248A JP H02265248 A JPH02265248 A JP H02265248A JP 8569189 A JP8569189 A JP 8569189A JP 8569189 A JP8569189 A JP 8569189A JP H02265248 A JPH02265248 A JP H02265248A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- impurity
- ions
- concentration
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 239000000969 carrier Substances 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 4
- 238000013459 approach Methods 0.000 abstract description 2
- 125000006850 spacer group Chemical group 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 208000022010 Lhermitte-Duclos disease Diseases 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＭＯＳ型トランジスタ、特にＬＤＤ（Ｌｉｇ
ｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ）構造を有するトラ
ンジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to MOS transistors, particularly LDDs (Lig
The present invention relates to a method of manufacturing a transistor having a doped drain structure.
（従来の技術）
トランジスタが微細化されるに伴ない、ドレイン近傍に
電界が集中しホットキャリアが発生し、閾値変動等の特
性劣化を引き起こす。従来、この電界を緩和するために
第３図に示すように、２種類の不純物濃度を有し、チャ
ネル側に低濃度の不純物領域がくる構造即ちＬＤＤ構造
のトランジスタが多く使用されている。第３図において
、６はポリシリコン、７はゲート酸化膜、８はスペーサ
９は不純物拡散領域（低濃度）、１０は不純物拡散領域
（高濃度）、・１１は基板である。(Prior Art) As transistors become smaller, the electric field concentrates near the drain and hot carriers are generated, causing characteristic deterioration such as threshold fluctuation. Conventionally, in order to alleviate this electric field, as shown in FIG. 3, transistors having two types of impurity concentrations and a low concentration impurity region on the channel side, that is, an LDD structure, are often used. In FIG. 3, 6 is polysilicon, 7 is a gate oxide film, 8 is a spacer 9, an impurity diffusion region (low concentration), 10 is an impurity diffusion region (high concentration), and 11 is a substrate.
（発明が解決しようとする課題）
しかしながら、上記従来のＬＤＤ構造のトランジスタは
、以前のトランジスタよりホットキャリアの発生は抑え
られているものの皆無ではなく、しかもホットキャリア
の発生する箇所がスペーサーの下となり、このスペーサ
ーは気相成長した酸化膜であるためトラップ準位が多く
トラップされ易い、さらにスペーサーには強制的に電位
を与えないので、トラップされたホットキャリアは直接
チャネル部に影響を及ぼすことになる。(Problem to be Solved by the Invention) However, although the conventional LDD structure transistor described above has suppressed the generation of hot carriers compared to previous transistors, it is not completely eliminated, and furthermore, the location where hot carriers are generated is under the spacer. Since this spacer is an oxide film grown in a vapor phase, it has many trap levels and is easily trapped.Furthermore, since a potential is not forcibly applied to the spacer, the trapped hot carriers will not directly affect the channel part. Become.
本発明は上記従来の問題を解決するＭＯ３型トランジス
タの製造方法を提供することを目的とするものである。An object of the present invention is to provide a method for manufacturing an MO3 type transistor that solves the above-mentioned conventional problems.
（課題を解決するための手段）
本発明は上記目的を達成するために、トランジスタとし
ては、ＬＤＤ構造の低濃度不純物領域の上にトラップ準
位の少ない熱酸化膜がくるようにする。この熱酸化膜上
にはゲート電極となるポリシリコンを成長させた構造で
ある。上記構造のトランジスタを形成するため、半導体
基板上に絶縁膜を形成し、絶縁膜上にポリシリコンを成
長させ、前記ポリシリコン中の不純物濃度がポリシリコ
ン上端から下端へ負の濃度勾配をもつようにさせるよう
にする製造方法である。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a transistor in which a thermal oxide film with few trap levels is placed over a low concentration impurity region of an LDD structure. The structure is such that polysilicon, which will become the gate electrode, is grown on this thermal oxide film. In order to form a transistor with the above structure, an insulating film is formed on a semiconductor substrate, polysilicon is grown on the insulating film, and the impurity concentration in the polysilicon has a negative concentration gradient from the top end of the polysilicon to the bottom end. This is a manufacturing method that allows the
（作 用）
したがって、本発明の製造方法によって作成されたトラ
ンジスタは、不純物領域に電界が集中し、ホットキャリ
アが発生しても上の熱酸化膜はトラップ準位が少ないた
めトラップされにくい。また、トラップされたとしても
熱酸化には強制的に電圧が印加されているので、トラッ
プされたキャリアがチャネル部に悪影響を及ぼすことは
ない。さらに、低濃度の不純物領域は水平方向に濃度勾
配をもっており、濃度分布が均一な場合程相互コンダク
タンスの低下のないトランジスタを製造することができ
る。(Function) Therefore, in the transistor manufactured by the manufacturing method of the present invention, even if the electric field is concentrated in the impurity region and hot carriers are generated, the upper thermal oxide film is difficult to be trapped because there are few trap levels. Furthermore, even if trapped carriers are trapped, a voltage is forcibly applied during thermal oxidation, so the trapped carriers will not have a negative effect on the channel portion. Furthermore, the low concentration impurity region has a concentration gradient in the horizontal direction, and a transistor with less reduction in mutual conductance can be manufactured when the concentration distribution is uniform.
（実施例）
第１図は本発明の一実施例の工程によって製造されたト
ランジスタの構造断面を示す図である。(Example) FIG. 1 is a diagram showing a structural cross section of a transistor manufactured by the process of an example of the present invention.
第１図において、１はポリシリコン、２はグー１−酸化
膜、３は不純物拡散領域（低濃度）、４は不純物拡散領
域（高濃度）、５は基板である。In FIG. 1, 1 is polysilicon, 2 is a goo 1-oxide film, 3 is an impurity diffusion region (low concentration), 4 is an impurity diffusion region (high concentration), and 5 is a substrate.
第２図は本発明の一実施例の工程を示す図である。第２
図において、数字１〜５は第１図の対応する数字と同一
の内容を示している。FIG. 2 is a diagram showing the steps of an embodiment of the present invention. Second
In the figure, numbers 1 to 5 indicate the same contents as the corresponding numbers in FIG.
次に本発明の製造方法を説明する。基板５を熱酸化しゲ
ート酸化膜２を形成する（第２図（ａ））。Next, the manufacturing method of the present invention will be explained. The substrate 5 is thermally oxidized to form a gate oxide film 2 (FIG. 2(a)).
次にゲート酸化膜２上にゲート電極用のポリシリコン１
を成長させ、さらにポリシリコン１の全面にイオン注入
を行うと不純物濃度勾配をもつポリシリコンが形成され
る（第２図（ｂ））。このとき、不純物イオンが基板５
に突き抜けないように加速電圧を設定する必要がある。Next, polysilicon 1 for gate electrode is placed on gate oxide film 2.
When ion implantation is performed on the entire surface of polysilicon 1, polysilicon having an impurity concentration gradient is formed (FIG. 2(b)). At this time, impurity ions are
It is necessary to set the accelerating voltage so that it does not penetrate.
次に、ゲート電極部にレジストによりマスクをした後ポ
リシリコンエツチングを行うと、ポリシリコン中の不純
物濃度は基板に近づくにつれて小さくなる。例えばＳＦ
、を用いたプラズマエツチングをすると、ポリシリコン
中のイオン注入による不純物濃度プロファイルに対応し
た第２図（ｃ）に示されるポリシリコン壬ツチング形状
が形成される。Next, when polysilicon etching is performed after masking the gate electrode portion with a resist, the impurity concentration in the polysilicon decreases as it approaches the substrate. For example, SF
When plasma etching is performed using , a polysilicon etching shape shown in FIG. 2(c) corresponding to the impurity concentration profile due to ion implantation into polysilicon is formed.
次に、ポリシリコン膜厚の薄い部分のみ不純物イオンが
突き抜ける条件でイオン注入を行うと。Next, ion implantation is performed under conditions that allow impurity ions to penetrate only the thin portions of the polysilicon film.
基板５に不純物拡散領域（低濃度）３が形成される（第
２図（ｄ））。さらに、ポリシリコンの膜厚の大小にか
かわらずポリシリコンが注入マスクとなる条件でイオン
注入を行うと、不純物拡散領域（高濃度）４が形成され
（第２図（ｅ））、第１図のＬＤＤ構造のトランジスタ
を得ることができる。An impurity diffusion region (low concentration) 3 is formed in the substrate 5 (FIG. 2(d)). Furthermore, regardless of the thickness of the polysilicon film, if ion implantation is performed under the condition that polysilicon serves as an implantation mask, an impurity diffusion region (high concentration) 4 is formed (FIG. 2(e)), and as shown in FIG. A transistor with an LDD structure can be obtained.
（発明の効果）
本発明は上記実施例から明らかなように、トランジスタ
の信頼性向上が大きく図られたＬＤＤ構造のトランジス
タを形成することができる。また、従来のＬＤＤ構造を
形成する時のようなスペーサーを必要としないため、気
相成長及びエツチングの工程が省略できる効果を有する
。(Effects of the Invention) As is clear from the above embodiments, the present invention can form a transistor with an LDD structure in which the reliability of the transistor is greatly improved. Furthermore, since a spacer is not required when forming a conventional LDD structure, the process of vapor phase growth and etching can be omitted.
第１図は本発明の一実施例の製造方法によって製造され
たＬＤＤ構造のトランジスタの断面図、第２図は本発明
の一実施例の製造方法の工程図、第３図は従来のＬＤＤ
構造のトランジスタの断面図である。
１．６・・・ポリシリコン、 ２，７・・・ゲート酸化
膜、 ３，９ ・・・不純物拡散領域（低濃度）、４．
１０・・・不純物拡散領域（高濃度）、 ５，１１・・
・基板、 ８・・・スペーサー
特許出願人 松下電子工業株式会社
第
図
ポリシリコン
５茎檄
第
図
第
図
↓
↓
↓
↓
↓イオン麩
第
図
ホ゛リシリコンFIG. 1 is a cross-sectional view of a transistor with an LDD structure manufactured by a manufacturing method according to an embodiment of the present invention, FIG. 2 is a process diagram of a manufacturing method according to an embodiment of the present invention, and FIG. 3 is a conventional LDD
FIG. 2 is a cross-sectional view of a transistor of the structure. 1.6... Polysilicon, 2,7... Gate oxide film, 3,9... Impurity diffusion region (low concentration), 4.
10... Impurity diffusion region (high concentration), 5, 11...
・Substrate, 8... Spacer Patent applicant: Matsushita Electronics Co., Ltd. Figure 5 Polysilicon Figure ↓ ↓ ↓ ↓ ↓ Ion Fu Figure Polysilicon
Claims (1)
リコンを成長させ、前記ポリシリコン中の不純物濃度が
ポリシリコン上端から下端へ負の濃度勾配をもつように
することを特徴とするＭＯＳ型トランジスタの製造方法
。A MOS characterized in that an insulating film is formed on a semiconductor substrate, polysilicon is grown on the insulating film, and the impurity concentration in the polysilicon has a negative concentration gradient from the upper end to the lower end of the polysilicon. A method of manufacturing type transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8569189A JPH02265248A (en) | 1989-04-06 | 1989-04-06 | Manufacture of mos-type transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8569189A JPH02265248A (en) | 1989-04-06 | 1989-04-06 | Manufacture of mos-type transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02265248A true JPH02265248A (en) | 1990-10-30 |
Family
ID=13865867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8569189A Pending JPH02265248A (en) | 1989-04-06 | 1989-04-06 | Manufacture of mos-type transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02265248A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6555885B2 (en) | 2001-01-11 | 2003-04-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| US6730584B2 (en) * | 1999-06-15 | 2004-05-04 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures |
| US6812530B2 (en) | 1999-06-11 | 2004-11-02 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures |
| US8698248B2 (en) | 2007-04-27 | 2014-04-15 | Yoshikazu Moriwaki | Semiconductor device and method of forming the same |
-
1989
- 1989-04-06 JP JP8569189A patent/JPH02265248A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812530B2 (en) | 1999-06-11 | 2004-11-02 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures |
| US6730584B2 (en) * | 1999-06-15 | 2004-05-04 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures |
| US6908803B2 (en) | 1999-06-15 | 2005-06-21 | Micron Technology, Inc. | Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures |
| US6555885B2 (en) | 2001-01-11 | 2003-04-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| US8698248B2 (en) | 2007-04-27 | 2014-04-15 | Yoshikazu Moriwaki | Semiconductor device and method of forming the same |
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