JPH02253647A - Semiconductor case - Google Patents

Semiconductor case

Info

Publication number
JPH02253647A
JPH02253647A JP7375089A JP7375089A JPH02253647A JP H02253647 A JPH02253647 A JP H02253647A JP 7375089 A JP7375089 A JP 7375089A JP 7375089 A JP7375089 A JP 7375089A JP H02253647 A JPH02253647 A JP H02253647A
Authority
JP
Japan
Prior art keywords
sides
semiconductor
lead terminals
external lead
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7375089A
Other languages
Japanese (ja)
Inventor
Takaaki Ichihara
市原　孝彰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7375089A priority Critical patent/JPH02253647A/en
Publication of JPH02253647A publication Critical patent/JPH02253647A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve wiring rate of a printed circuit board by arbitrarily varying pitch intervals of external lead terminals led from the sides of a sealing vessel at the respective sides. CONSTITUTION:The pitch intervals of external lead terminals 3 led from the sides 20a, 21a of a semiconductor case 2 are different, and wider than those of the sides 20a, 21a. External lead terminals 3 of the corresponding number are led to sides 20b, 21b opposed to the sides 20a, 21a. On the other hand, semiconductor placing pads 5 are disposed corresponding to the number of the terminals 3 of a semiconductor case 1 on a printed circuit board 4, and a wiring pattern 6 is printed between the pads. Accordingly, when the case 2 is placed on the board 4, the sides 20a, 20b of wide pitch interval are disposed in the wiring direction of the placing face, the terminals 3 are secured to the pads 5, and mounted. Thus, the wiring rate of the board 4 is improved.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、電子機器等に使用される半導体ケースに関し
、特に外部に導出するリード端子の配線のピッチ間隔を
変化させることによって、プリント配線基板の配線率を
向上させるようにした半導体ケースに関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a semiconductor case used in electronic equipment, etc., and in particular, the present invention relates to a semiconductor case used in electronic equipment, etc., and in particular to a printed wiring board by changing the pitch interval of the wiring of lead terminals led out to the outside. The present invention relates to a semiconductor case that improves wiring efficiency.

［従来の技術］ 従来、この種の半導体ケースは第３図に示すようになっ
ていた。すなわち、封止容器１２から導出する外部リー
ド端子１３の数は各辺とも一定であり、さらにそれぞれ
の端子のピッチ間隔は同一寸法になっていた。[Prior Art] Conventionally, this type of semiconductor case has been designed as shown in FIG. That is, the number of external lead terminals 13 led out from the sealed container 12 was constant on each side, and furthermore, the pitch interval of each terminal was the same dimension.

〔解決すべき課題〕〔Problems to be solved〕

上述した従来の半導体ケースでは、外部リード端子の導
出端子か各辺一定であり、かつ同一寸法のピッチ間隔で
あった。そのため、例えば半導体の高集積化に伴ない外
部リード端子の数が増加した場合には、所定のケースサ
イズに収めるために必然的にリード端子のピッチ間隔を
挟めることになった。In the conventional semiconductor case described above, the lead-out terminals of the external lead terminals are constant on each side and have the same pitch interval. Therefore, for example, when the number of external lead terminals increases due to higher integration of semiconductors, the pitch of the lead terminals has to be narrowed in order to fit within a predetermined case size.

そして、この半導体をプリント配線基板上に搭載した場
合には、半導体の外部リード端子に対応して配設したバ
ッド間が狭くなり、通常に配置されたバッド間での配線
が困難になった。When this semiconductor is mounted on a printed wiring board, the distance between the pads arranged corresponding to the external lead terminals of the semiconductor becomes narrow, making it difficult to wire between the normally arranged pads.

これを解決するために、パット間以外の他のスペースを
利用して配線パターンを行う手段がとられ、必然的にプ
リント配線基板か大型化してきた。また、これにともな
って、プリント配線基板の基板層の数も増加する傾向に
あり、製造のためのコスト高をまねくようになってきた
。In order to solve this problem, methods have been taken to form wiring patterns using spaces other than between the pads, which has inevitably led to larger printed wiring boards. Additionally, along with this, the number of substrate layers of printed wiring boards has also tended to increase, leading to increased manufacturing costs.

本発明は上述した問題点にかんがみてなされたもので、
半導体ケースの外部導出のリード端子のピッチ間隔な各
辺ごとに任意に変化させることによって、半導体の高集
積化にともなうプリント配線基板の配線率の向上を図り
、かつコスト的にも低く抑えることか可能な半導体ケー
スの提供を目的とする。The present invention has been made in view of the above-mentioned problems.
By arbitrarily changing the pitch of the lead terminals extended to the outside of the semiconductor case on each side, it is possible to improve the wiring efficiency of printed wiring boards as semiconductors become more highly integrated, while also keeping costs low. The purpose is to provide a possible semiconductor case.

［課題の解決手段］ 上記目的を達成するために本考案の半導体ケースは、封
止容器の各辺から導出した複数の外部リード端子を有す
る半導体ケースにおいて１封止容器の各辺から導出する
外部リード端子のピッチ間隔を、各辺ごとに任意に変化
させた構成とじである。[Means for Solving the Problems] In order to achieve the above object, the semiconductor case of the present invention has a semiconductor case having a plurality of external lead terminals led out from each side of the sealed container. This is a binding structure in which the pitch interval of the lead terminals is arbitrarily changed for each side.

［実施例］ 以下、本考案の一実施例について図面を参照して説明す
る。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例である半導体ケースの全体斜
視図、第２図は本実施例の半導体ケースを搭載するプリ
ント配線基板の平面図である。FIG. 1 is an overall perspective view of a semiconductor case according to an embodiment of the present invention, and FIG. 2 is a plan view of a printed wiring board on which the semiconductor case of this embodiment is mounted.

図面において、ｌは半導体ケース本体である。In the drawings, l is the semiconductor case body.

この半導体ケース本体ｌは封止容器２と、封止容器２の
四辺から導出する外部リード端子３とて構成されている
。This semiconductor case body 1 is composed of a sealed container 2 and external lead terminals 3 led out from the four sides of the sealed container 2.

このとき、半導体ケース２の辺２０ａと辺２１ａから導
出する外部リード端子３のピッチ間隔は異なっており１
辺２０ａは辺２１ａにくらべそのピッチ間隔は広い、ま
た、辺２０ａに対向する辺２０ｂ、及び辺２１ａに対向
する辺２１ｂには、それぞれ対応する数の外部リード端
子３が導出しである。At this time, the pitch intervals of the external lead terminals 3 led out from the side 20a and the side 21a of the semiconductor case 2 are different.
The pitch of the side 20a is wider than that of the side 21a, and corresponding numbers of external lead terminals 3 are connected to the side 20b opposite to the side 20a and the side 21b opposite to the side 21a.

一方、４はプリント配線基板であり、半導体ケース１の
外部リード端子３の数に対応して半導体搭載用バット５
が配置しである。また、６は配線パターンであり半導体
搭載用バッド５の間に印刷配線されている。On the other hand, 4 is a printed wiring board, and semiconductor mounting bats 5 correspond to the number of external lead terminals 3 of the semiconductor case 1.
is placed. Further, 6 is a wiring pattern, which is printed and wired between the semiconductor mounting pads 5.

したかって、このような構成から、なる半導体ケースを
プリント配線基板に搭載すると、搭載面の配線方向にピ
ッチ間隔の広い辺２０ａ、２０ｂを位置させ、それぞれ
の外部リード端子３を半導体搭載用パッド５上に固定し
、装着を行う。Therefore, when a semiconductor case with such a configuration is mounted on a printed wiring board, the sides 20a and 20b with a wide pitch interval are positioned in the wiring direction of the mounting surface, and the respective external lead terminals 3 are connected to the semiconductor mounting pads 5. Fix it on top and install it.

［発明の効果］ 以上説明したように本発明によれば、半導体ケースの外
部リード端子のピッチ間隔を任意に変化させることによ
ってプリント配線基板の配線率の向上を図るとともに、
コスト的にも低く抑えることが回部になるといった効果
がある。[Effects of the Invention] As explained above, according to the present invention, by arbitrarily changing the pitch interval of the external lead terminals of the semiconductor case, the wiring efficiency of the printed wiring board can be improved, and
Keeping costs low also has the effect of increasing circulation.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例である半導体ケースの全体斜
視図、第２図は本実施例の半導体ケースを搭載するプリ
ント配線基板の平面図、第３図は従来の半導体ケースの
全体斜視図、第４図は従来の半導体ケースを搭載するプ
リント配線基板の平面図である。 ｌ：半導体ケース本体 ２：封止容器 ２０ａ、２０ｂ、２１ａ、２１ｂ：辺 ３：外部リード端子 ４ニブリント配線基板 ５：半導体搭載用バウド ６：配線パターン 代理人　弁理士　渡　辺　喜　平 第 図 第 図 第 図 第 図FIG. 1 is an overall perspective view of a semiconductor case that is an embodiment of the present invention, FIG. 2 is a plan view of a printed wiring board on which the semiconductor case of this embodiment is mounted, and FIG. 3 is an overall perspective view of a conventional semiconductor case. 4 are plan views of a printed wiring board on which a conventional semiconductor case is mounted. l: Semiconductor case body 2: Sealing container 20a, 20b, 21a, 21b: Side 3: External lead terminal 4 Niblint wiring board 5: Semiconductor mounting board 6: Wiring pattern agent Patent attorney Kihei Watanabe Figure Figure

Claims (1)

【特許請求の範囲】[Claims] 封止容器の各辺から導出した複数の外部リード端子を有
する半導体ケースにおいて、封止容器の各辺から導出す
る外部リード端子のピッチ間隔を各辺ごとに任意に変化
させたことを特徴とする半導体ケース。A semiconductor case having a plurality of external lead terminals led out from each side of the sealed container, characterized in that the pitch interval of the external lead terminals led out from each side of the sealed container is arbitrarily changed for each side. semiconductor case.
JP7375089A 1989-03-28 1989-03-28 Semiconductor case Pending JPH02253647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7375089A JPH02253647A (en) 1989-03-28 1989-03-28 Semiconductor case

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7375089A JPH02253647A (en) 1989-03-28 1989-03-28 Semiconductor case

Publications (1)

Publication Number Publication Date
JPH02253647A true JPH02253647A (en) 1990-10-12

Family

ID=13527238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7375089A Pending JPH02253647A (en) 1989-03-28 1989-03-28 Semiconductor case

Country Status (1)

Country Link
JP (1) JPH02253647A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57127155A (en) * 1981-01-27 1982-08-07 Citizen Watch Co Ltd Switchover mechanism
JPS57192058A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor device
JPS58173810A (en) * 1982-04-06 1983-10-12 Matsushita Electric Ind Co Ltd Inductance element

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57127155A (en) * 1981-01-27 1982-08-07 Citizen Watch Co Ltd Switchover mechanism
JPS57192058A (en) * 1981-05-22 1982-11-26 Hitachi Ltd Semiconductor device
JPS58173810A (en) * 1982-04-06 1983-10-12 Matsushita Electric Ind Co Ltd Inductance element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages

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