JPH02246120A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPH02246120A JPH02246120A JP6726989A JP6726989A JPH02246120A JP H02246120 A JPH02246120 A JP H02246120A JP 6726989 A JP6726989 A JP 6726989A JP 6726989 A JP6726989 A JP 6726989A JP H02246120 A JPH02246120 A JP H02246120A
- Authority
- JP
- Japan
- Prior art keywords
- silicon layer
- layer
- thin film
- polycrystalline silicon
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 4
- 230000003647 oxidation Effects 0.000 claims abstract 3
- 238000007254 oxidation reaction Methods 0.000 claims abstract 3
- 239000012535 impurity Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 23
- 239000010408 film Substances 0.000 abstract description 19
- 238000011109 contamination Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
【産業上の利用分野】
本発明は、液晶デイスプレィやプリンターのサーマル・
ヘッドや撮像装置の駆動素子となる薄膜トランジスタの
製造方法に関する。
〔従来の技術１
従来の技術としては特開昭６３−１３６６７３号公報に
記載されたものがある。これは第２図の（ａ）に示すよ
うに絶縁基板ｌｌ上に第１半導体１２を積層した後、エ
ネルギービーム１７を照射し第１半導体１２を再結晶半
導体膜２１に変換する６次に第２図（ｂ）に示すように
第２半導体１３と絶縁膜１４を構成した後、エネルギー
ビームを照射して低抵抗な第２半導体１３を活性化し、
さらに低抵抗化し、薄膜トランジスタを分離するために
再結晶半導体膜２１をエツチングする。この後、第２図
（Ｃ）に示すようにゲート絶祿膜１５を推積し、さらに
低抵抗な第３半導体膜１６を積層し、ソース部分とドレ
イン部分にフォトリソ技術でコンタクトホールを形成し
てゲート電極７、ソース電極９とドレイン電極８を製作
し薄膜トランジスタを構成するものである。
〔発明が解決しようとする課題１
しかし、上記の従来の薄膜トランジスタの製造方法は、
第２図（ｂ）に示すように第２半導体１３と絶縁膜１４
を島状に形成する際に、再結晶半導体膜２１の表面が露
出しているため、再結晶半導体膜２１の表面が傷つきや
すいうえに汚染されやすく、薄膜トランジスタの信頼性
を下げる原因となっていた。
さらに、第２図（Ｃ）に示すようにゲート絶縁１１１１
５を積層するためにゲート絶縁膜１５と再結晶半導体膜
２１の間の界面準位が高く、薄膜トランジスタの電気的
特性が悪くなるものが多いという問題点を有していた。
そこで、本発明は、ゲート絶縁膜と半導体との界面準位
を低くおさえ、半導体表面に損傷を与えることのない薄
膜トランジスタの製造方法を提供することを目的とする
。
〔課題を解決するための手段］
上記課題を解決するため、本発明の薄膜トランジスタの
製造方法は絶縁性基体上に第１非晶質シリコン層と不純
物推積層を推積した後、前記第１非晶質シリコン層と前
記不純物推積層ヘレーザ・ビームを照射して前記第１非
晶質シリコン層を低抵抗シリコン層に変換する工程と、
前記低抵抗シリコン層をドレイン領域とソース領域に島
状に残す工程と、前記低抵抗シリコン層上とチャネル領
域上に第２非晶質シリコン層を積層した後、前記レーザ
・ビームを照射し前記第２非晶質シリコン層を多結晶シ
リコン層に変換した後、前記多結晶シリコン層を水蒸気
を含む酸素雰囲気中で熱酸化して酸化シリコン層を形成
する工程と、前記酸化シリコン層上にゲート電極を構成
し、前記酸化シリコン層に開口部を形成しドレイン電極
とソース電極を製作する工程とからなることを特徴とす
る。
〔実 施 例］
以下に本発明の実施例を図面にもとづいて説明する。第
１図（ａ）において、絶縁性基体ｌ上に第１非晶質シリ
コン層２を成膜し、第１図（ｂ）に示すようにリンやポ
ロンなどの不純物を含有する不純物推積層３を積層した
後、レーザ・ビームｌＯを照射し第１図（Ｃ）における
ように不純物推積層３中の不純物を第１非晶質シリコン
層２中へ拡散させ低抵抗シリコン層４を形成する０次に
第１図（ｄ）に示すように低抵抗シリコン層４をドレイ
ン領域１８とソース領域１９に島状に残し第１図（ｅ）
に示すように第２非晶質シリコン層２１を積層し島状に
形成した後、再びレーザ・ビーム１０を照射し第２非晶
質シリコン層２１を多結晶シリコン層に変換した後、第
１図（ｆ）に示すように多結晶シリコン層５の表面を水
蒸気を含む酸素雰囲気中で６００℃はどの温度で熱酸化
し、酸化シリコン層６を形成する。この工程において、
多結晶シリコン層５の表面から酸化するため多結晶シリ
コン層５は薄膜化でき酸化シリコン層６と酸化されずに
残った多結晶シリコン層５との界面は、外部雰囲気にさ
らされ汚染されることはなく、界面が損傷を受けること
もない、このため、多結晶シリコン層５を半導体層とし
、酸化シリコン層６をゲート絶縁膜とする薄膜トランジ
スタの界面準位密度は低くおさえることが可能で。
素子特性は良好で信頼性も高いものとなる。
次の工程からは通常の薄膜トランジスタの製造方法と同
様であり、第１図（９）に示すようにゲート電極７を構
成した後、第１図（ｈ）に示すように酸化シリコン層６
に開口部を形成し、ドレイン電極８とソース電極９を構
成して薄膜トランジスタが完成する。
【発明の効果Ｊ
本発明の薄膜トランジスタの製造方法は、以上説明した
ように、半導体層となる多結晶シリコン層を形成した後
、水蒸気を含む酸素雰囲気中で熱酸化してゲート絶縁膜
を構成するという工程によって、半導体層の表面の汚染
や損傷を防ぎ、界面準位密度の低い高信頼性かつ高性能
な薄膜トランジスタを実現しえる効果を有する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to thermal
The present invention relates to a method for manufacturing thin film transistors that serve as drive elements for heads and imaging devices. [Prior Art 1] A conventional technique is one described in Japanese Patent Application Laid-open No. 136673/1983. As shown in FIG. 2(a), the first semiconductor 12 is laminated on an insulating substrate 11, and then an energy beam 17 is irradiated to convert the first semiconductor 12 into a recrystallized semiconductor film 21. After configuring the second semiconductor 13 and the insulating film 14 as shown in FIG. 2(b), the low-resistance second semiconductor 13 is activated by irradiation with an energy beam,
The recrystallized semiconductor film 21 is etched to further lower the resistance and separate the thin film transistors. After this, as shown in FIG. 2(C), a gate isolation film 15 is deposited, a third semiconductor film 16 with low resistance is further deposited, and contact holes are formed in the source and drain parts using photolithography. A gate electrode 7, a source electrode 9, and a drain electrode 8 are fabricated to form a thin film transistor. [Problem to be solved by the invention 1 However, the above-mentioned conventional thin film transistor manufacturing method
As shown in FIG. 2(b), the second semiconductor 13 and the insulating film 14
When forming the thin film transistor into an island shape, the surface of the recrystallized semiconductor film 21 is exposed, so the surface of the recrystallized semiconductor film 21 is easily damaged and contaminated, which is a cause of lowering the reliability of the thin film transistor. . Furthermore, as shown in FIG. 2(C), the gate insulator 1111
5, the interface state between the gate insulating film 15 and the recrystallized semiconductor film 21 is high, and the electrical characteristics of the thin film transistors often deteriorate. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a thin film transistor in which the interface state between a gate insulating film and a semiconductor is kept low and the semiconductor surface is not damaged. [Means for Solving the Problems] In order to solve the above problems, the method for manufacturing a thin film transistor of the present invention includes depositing a first amorphous silicon layer and an impurity estimation layer on an insulating substrate, and then depositing the first non-crystalline silicon layer and an impurity estimation layer on an insulating substrate. converting the first amorphous silicon layer into a low resistance silicon layer by irradiating the crystalline silicon layer and the impurity layer with a laser beam;
After leaving the low-resistance silicon layer in the form of islands in the drain region and source region, and stacking a second amorphous silicon layer on the low-resistance silicon layer and the channel region, the laser beam is irradiated to After converting the second amorphous silicon layer into a polycrystalline silicon layer, a step of thermally oxidizing the polycrystalline silicon layer in an oxygen atmosphere containing water vapor to form a silicon oxide layer, and forming a gate on the silicon oxide layer. The method is characterized by comprising the steps of forming an electrode, forming an opening in the silicon oxide layer, and manufacturing a drain electrode and a source electrode. [Example] Examples of the present invention will be described below based on the drawings. In FIG. 1(a), a first amorphous silicon layer 2 is formed on an insulating substrate l, and as shown in FIG. 1(b), an impurity presumed layer 3 containing impurities such as phosphorus and poron is formed. After stacking, a laser beam IO is irradiated to diffuse the impurities in the impurity estimation layer 3 into the first amorphous silicon layer 2 to form a low resistance silicon layer 4 as shown in FIG. 1(C). Next, as shown in FIG. 1(d), the low-resistance silicon layer 4 is left in the form of islands in the drain region 18 and source region 19, as shown in FIG. 1(e).
As shown in the figure, after the second amorphous silicon layer 21 is laminated and formed into an island shape, the laser beam 10 is irradiated again to convert the second amorphous silicon layer 21 into a polycrystalline silicon layer, and then the first amorphous silicon layer 21 is laminated and formed into an island shape. As shown in Figure (f), the surface of the polycrystalline silicon layer 5 is thermally oxidized at a temperature of 600° C. in an oxygen atmosphere containing water vapor to form a silicon oxide layer 6. In this process,
Since the surface of the polycrystalline silicon layer 5 is oxidized, the polycrystalline silicon layer 5 can be made thinner, and the interface between the silicon oxide layer 6 and the polycrystalline silicon layer 5 that remains unoxidized is exposed to the external atmosphere and becomes contaminated. Therefore, the interface state density of a thin film transistor in which the polycrystalline silicon layer 5 is used as a semiconductor layer and the silicon oxide layer 6 is used as a gate insulating film can be kept low. The device characteristics are good and the reliability is high. The next step is similar to the manufacturing method of a normal thin film transistor, and after forming the gate electrode 7 as shown in FIG. 1(9), the silicon oxide layer 6 is formed as shown in FIG. 1(h).
An opening is formed in the wafer, and a drain electrode 8 and a source electrode 9 are formed to complete the thin film transistor. Effects of the Invention J As explained above, the method for manufacturing a thin film transistor of the present invention includes forming a polycrystalline silicon layer to serve as a semiconductor layer, and then thermally oxidizing it in an oxygen atmosphere containing water vapor to form a gate insulating film. This process has the effect of preventing contamination and damage to the surface of the semiconductor layer and making it possible to realize highly reliable and high-performance thin film transistors with low interface state density.
第１図（ａ）〜（ｈ）は、本発明の薄膜トランジスタの
製造方法の一実施例の製造工程順の断面図。
第２図（ａ）〜（ｃ）は、従来の薄膜トランジスタの製
造方法の製造工程順の断面図である。
絶縁性基体
第１非晶質シリコン層
不純物推積層
低抵抗シリコン層
多結晶シリコン層
酸化シリコン層
ゲート電極
ドレイン電極
ソース電極
レーザ・ビーム
絶縁基板
・第１半導体
・第２半導体
・絶縁膜
・ゲート絶縁膜
・第３半導体膜
・エネルギービーム
・ドレイン領域
・ソース領域
・チャネル領域
・再結晶半導体膜
出願人 セイコーエプソン株式会社
代理人 弁理士 鈴 木 喜三部（化１名）発１０ レ
ーザし〜ひ
第
図
第
図FIGS. 1(a) to 1(h) are cross-sectional views showing the order of manufacturing steps in an embodiment of the method for manufacturing a thin film transistor of the present invention. FIGS. 2(a) to 2(c) are cross-sectional views in the order of manufacturing steps in a conventional thin film transistor manufacturing method. Insulating substrate First amorphous silicon layer Impurity stack layer Low resistance silicon layer Polycrystalline silicon layer Silicon oxide layer Gate electrode Drain electrode Source electrode Laser beam Insulating substrate First semiconductor Second semiconductor Insulating film Gate insulating film・Third semiconductor film ・Energy beam ・Drain region ・Source region ・Channel region ・Recrystallized semiconductor film Applicant Seiko Epson Co., Ltd. Agent Patent attorney Kisabe Suzuki (1st name) 10 Laser shield diagram Diagram
Claims (1)
積層を推積した後、前記第１非晶質シリコン層と前記不
純物推積層へレーザ・ビームを照射して前記第１非晶質
シリコン層を低抵抗シリコン層に変換する工程と、前記
低抵抗シリコン層をドレイン領域とソース領域に島状に
残す工程と、前記低抵抗シリコン層上とチャネル領域上
に第２非晶質シリコン層を積層した後、前記レーザ・ビ
ームを照射し前記第２非晶質シリコン層を多結晶シリコ
ン層に変換した後、前記多結晶シリコン層を水蒸気を含
む酸素雰囲気中で熱酸化して酸化シリコン層を形成する
工程と、前記酸化シリコン層上にゲート電極を構成し、
前記酸化シリコン層に開口部を形成しドレイン電極とソ
ース電極を製作する工程とからなる事を特徴とする薄膜
トランジスタの製造方法。(1) After depositing a first amorphous silicon layer and a presumed impurity layer on an insulating substrate, a laser beam is irradiated to the first amorphous silicon layer and the presumed impurity layer to converting a crystalline silicon layer into a low-resistance silicon layer; leaving the low-resistance silicon layer in the form of islands in the drain and source regions; and forming a second amorphous silicon layer on the low-resistance silicon layer and the channel region. After stacking the silicon layers, the laser beam is irradiated to convert the second amorphous silicon layer into a polycrystalline silicon layer, and then the polycrystalline silicon layer is oxidized by thermal oxidation in an oxygen atmosphere containing water vapor. forming a silicon layer; forming a gate electrode on the silicon oxide layer;
A method for manufacturing a thin film transistor, comprising the steps of forming an opening in the silicon oxide layer and manufacturing a drain electrode and a source electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6726989A JPH02246120A (en) | 1989-03-18 | 1989-03-18 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6726989A JPH02246120A (en) | 1989-03-18 | 1989-03-18 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02246120A true JPH02246120A (en) | 1990-10-01 |
Family
ID=13340074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6726989A Pending JPH02246120A (en) | 1989-03-18 | 1989-03-18 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02246120A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07283415A (en) * | 1994-04-12 | 1995-10-27 | Kodo Eizo Gijutsu Kenkyusho:Kk | Thin-film transistor and its manufacturing method |
| CN104167349A (en) * | 2013-05-16 | 2014-11-26 | 上海和辉光电有限公司 | Preparation method of low temperature polysilicon film |
-
1989
- 1989-03-18 JP JP6726989A patent/JPH02246120A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07283415A (en) * | 1994-04-12 | 1995-10-27 | Kodo Eizo Gijutsu Kenkyusho:Kk | Thin-film transistor and its manufacturing method |
| CN104167349A (en) * | 2013-05-16 | 2014-11-26 | 上海和辉光电有限公司 | Preparation method of low temperature polysilicon film |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6372593B1 (en) | Method of manufacturing SOI substrate and semiconductor device | |
| JPH01162376A (en) | Manufacture of semiconductor device | |
| JPS6010773A (en) | Method of forming 1-element fet-memory capacitor circuit | |
| JPH0451071B2 (en) | ||
| KR19980034500A (en) | Semiconductor device and manufacturing method | |
| JPH02246120A (en) | Manufacture of thin film transistor | |
| JPS6286838A (en) | Manufacture of integrated circuit | |
| JPH1117184A (en) | Semiconductor device and its manufacture | |
| JP2718074B2 (en) | Method of forming thin film semiconductor layer | |
| JPS643046B2 (en) | ||
| JPH0467336B2 (en) | ||
| JP3127866B2 (en) | Method for manufacturing semiconductor device | |
| JPH0231468A (en) | Manufacture of floating gate type semiconductor memory device | |
| JP4309492B2 (en) | Manufacturing method of semiconductor device | |
| JP3189387B2 (en) | Method for manufacturing semiconductor device | |
| JPH0684939A (en) | Manufacture of mis field-effect semiconductor device | |
| JPH02100382A (en) | Field-effect type superconducting transistor and manufacture thereof | |
| JPH06120332A (en) | Semiconductor device | |
| JPS61239671A (en) | Manufacture of semiconductor memory device | |
| JPH01287964A (en) | Manufacture of semiconductor device | |
| JPS61129824A (en) | Manufacture of semiconductor device | |
| JPS6265364A (en) | Manufacture of semiconductor device | |
| JPH0527272B2 (en) | ||
| JPH065596A (en) | Manufacture of semiconductor device | |
| JPH02103930A (en) | Manufacture of semiconductor device |