JPH02241046A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPH02241046A
JPH02241046A JP1062694A JP6269489A JPH02241046A JP H02241046 A JPH02241046 A JP H02241046A JP 1062694 A JP1062694 A JP 1062694A JP 6269489 A JP6269489 A JP 6269489A JP H02241046 A JPH02241046 A JP H02241046A
Authority
JP
Japan
Prior art keywords
pad
wire bonding
wafer
semiconductor integrated
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1062694A
Other languages
Japanese (ja)
Inventor
Takashi Senba
仙波　隆司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1062694A priority Critical patent/JPH02241046A/en
Publication of JPH02241046A publication Critical patent/JPH02241046A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To sufficiently reduce the parasitic capacitance between a pad and a board by providing pads for a wafer prober and a pad for a wire bonding on the periphery of an LSI chip, and cutting the pad for the wafer prober after wafer probing. CONSTITUTION:A pad 4 for a wire bonding, a pad 3 for a wafer prober having larger area than that of the pad 4, wirings 5 for connecting both the pads 3, 4 to an internal circuit are formed on the periphery of a semiconductor integrated circuit chip 1. After the pad 3 is probed, the wirings 5 for connecting the pads 3, 4 to the circuit are cut. Thus, only the pad for wire bonding of small area finally performs a function of a signal pad. Accordingly, parasitic capacitance is reduced, and a parasitic effect of parasitic capacitance of the pad after assembling is particularly reduced in a high frequency circuit.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体集積回路チップの周辺にワイヤボンディ
ング用パッドを備えた半導体集積回路の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit having wire bonding pads around a semiconductor integrated circuit chip.

［従来の技術］ 従来の半導体集積回路（以下、ＬＳＩと呼ぶ）は１第２
図に示すように、ＬＳＩチップ１の回路部２の周辺に複
数の信号パッド６を配置すると共に、各信号パッド６と
回路部２とを配線５にて接続して構成されている。[Prior art] A conventional semiconductor integrated circuit (hereinafter referred to as LSI) has
As shown in the figure, a plurality of signal pads 6 are arranged around a circuit section 2 of an LSI chip 1, and each signal pad 6 and the circuit section 2 are connected with a wiring 5.

このＬＳＩは、信号パッド６がワイヤボンディング用パ
ッドとウェハープローバ用パッドとを共有したものとな
っている。In this LSI, the signal pad 6 is a wire bonding pad and a wafer prober pad.

［発明が解決しようとする課題］ 上述した従来のＬＳＩにおいては、信号パッドｅは、ウ
ェハープローピングの際にウェハープローハ用パッドと
して使用され、更にワイヤボンディングの際にボンディ
ング用パッドとして使用される。このため、信号パッド
６のサイズは、ウェハープローバに必要なパッドサイズ
と、ワイヤボンディングに必要なパッドサイズの双方を
満足したサイズ、即ち大きい方のサイズによって決定さ
れてしまう。[Problems to be Solved by the Invention] In the conventional LSI described above, the signal pad e is used as a wafer probing pad during wafer probing, and is further used as a bonding pad during wire bonding. . Therefore, the size of the signal pad 6 is determined by the size that satisfies both the pad size required for the wafer prober and the pad size required for wire bonding, that is, the larger size.

従って、高周波ＩＣにおいては、ウェハープローピング
に必要なパッドサイズがパッドの小型化を図るうえでの
制約条件となり、パッドと基板との間の寄生容量を十分
に抑制することができないという問題点があった。Therefore, in high-frequency ICs, the pad size required for wafer probing becomes a constraint in reducing the size of the pad, and there is a problem that parasitic capacitance between the pad and the substrate cannot be sufficiently suppressed. there were.

本発明はかかる問題点に鑑みてなされたものであって、
パッドと基板との間の寄生容量を十分に低減することが
できる半導体集積回路の製造方法を提供することを目的
とする。The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit that can sufficiently reduce parasitic capacitance between a pad and a substrate.

［課題を解決するための手段］ 本発明に係る半導体集積回路の製造方法は、半導体集積
回路チップの周辺にワイヤボンディング用パッドと、前
記ワイヤボンディング用パッドよりも大面積のウェハー
プローバ用のパッドト、コれら両パッドと内部回路とを
接続する配線とを形成し、前記ウェハーブローバ用パッ
ドに対するプローピングを行った後に、前記ウェハープ
ローバ用パッドと前記ワイヤボンディング用パッド及び
内部回路とを接続する配線を切断することを特徴とする
。[Means for Solving the Problems] A method for manufacturing a semiconductor integrated circuit according to the present invention includes: a wire bonding pad around a semiconductor integrated circuit chip; a wafer prober pad having a larger area than the wire bonding pad; After forming wiring connecting these pads to the internal circuit and probing the wafer prober pad, wiring connecting the wafer prober pad to the wire bonding pad and internal circuit is formed. Characterized by cutting.

［作用］ 本発明によれば、ＬＳＩチップの周辺にウェハープロー
バ用パッドとワイヤボンディング用パッドを設け、両パ
ッドを配線によって接続するようにしたので、ワイヤボ
ンディング用パッドのサイズは、ワイヤボンディングに
必要とされるだけのサイズで足りる。そして、ウェハー
プロービングの後にウェハープローバ用パッドを切断す
ることにより、内部回路に接続されるパッドは小型のワ
イヤボンディング用パッドのみとなり、寄生容量の低減
を図ることができる。[Function] According to the present invention, a wafer prober pad and a wire bonding pad are provided around the LSI chip, and the two pads are connected by wiring, so that the size of the wire bonding pad is adjusted according to the size required for wire bonding. A size that is considered to be sufficient is sufficient. By cutting the wafer prober pad after wafer probing, only the small wire bonding pad is connected to the internal circuit, and parasitic capacitance can be reduced.

［実施例コ 以下、添付の図面に基づいて本発明の実施例に係るＬＳ
Ｉの製造方法について説明する。[Example 7] Hereinafter, LS according to an example of the present invention will be described based on the attached drawings.
The method for manufacturing I will be explained.

第１図は本実施例方法を説明するためのＬＳＩチップの
要部構成を示す図である。FIG. 1 is a diagram showing the main part configuration of an LSI chip for explaining the method of this embodiment.

先ず、第１図（ａ）に示すように、ＬＳＩチップ１の回
路部２の周辺部に、大面積のウェハープローバ用パッド
３と小面積のワイヤボンディング用パッド４とが１対１
に対応して形成され、更に、両者が配線５を介して回路
部２に接続される。First, as shown in FIG. 1(a), a large-area wafer prober pad 3 and a small-area wire bonding pad 4 are arranged one-to-one around the circuit section 2 of an LSI chip 1.
Further, both are connected to the circuit section 2 via wiring 5.

この第１図（ａ）の状態でウェハープロービングが行わ
れる。ウェハープロービングの原には、ウェハープロー
バ用パッド３が使用され各種の試験が行われる。Wafer probing is performed in this state shown in FIG. 1(a). A wafer prober pad 3 is used as the basis for wafer probing, and various tests are performed.

プロービングが終了したら、第１図（ｂ）に示すように
、ウェハーブローパ用パッド３とワイヤボンディング用
パッド４及び回路部２とを接続している配線５を切断す
る。この第１図（ｂ）の状態でワイヤボンディングが行
われる。ワイヤボンディングの際にはワイヤボンディン
グ用パッド４が使用される。After the probing is completed, as shown in FIG. 1(b), the wiring 5 connecting the wafer roper pad 3, the wire bonding pad 4, and the circuit section 2 is cut. Wire bonding is performed in this state shown in FIG. 1(b). A wire bonding pad 4 is used during wire bonding.

この結果、得られたＬＳＩの回路部２に接続されたパッ
ドは、小面積のワイヤポンディングパッド４だけとなる
ので、配線パターンと基板との間の寄生容量を従来に比
べて大幅に抑制することができる。As a result, the only pad connected to the circuit section 2 of the LSI is the small-area wire bonding pad 4, which significantly suppresses the parasitic capacitance between the wiring pattern and the board compared to the conventional method. be able to.

［発明の効果コ 以上説明したように本発明は、チップ上に大面積ノウェ
ハーブローパ用パッドと小面積のワイヤボンディング用
パッドとを形成し、両者を配線で接続した後、ウェハー
プロービングを行い、その後、配線を切断してウェハー
プロ、−バ用バッドを切離すようにしたので、最終的に
信号用パッドとして機能するのが小面積のワイヤボンデ
ィング用パッドだけとなる。このため、寄生容量が低減
され、特に高周波回路において組立後のパッドの寄生容
量による寄生効果を低減することができる。[Effects of the Invention] As explained above, the present invention forms a large-area wafer brake pad and a small-area wire bonding pad on a chip, connects them with wiring, and then performs wafer probing. Thereafter, the wiring was cut to separate the wafer pro and -bar pads, so that only the small-area wire bonding pads ultimately functioned as signal pads. Therefore, the parasitic capacitance is reduced, and the parasitic effect due to the parasitic capacitance of the pad after assembly can be reduced, especially in a high frequency circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例方法を工程順に示した図で、第
１図（ａ）は配線切断前のＬＳＩチップの要部を示す平
面図、第１図（ｂ）は配線切断後のＬＳＩチップの要部
を示す平面図、第２図は従来のＬＳＩチップの要部を示
す平面図である。 １：ＬＳＩチップ、２；回路部、３；ウェハープローバ
用パッド、４；ワイヤボンディング用パッド、５；配線
、６；信号パッドFIG. 1 is a diagram illustrating the method according to the present invention in the order of steps. FIG. 1(a) is a plan view showing the main parts of an LSI chip before cutting the wiring, and FIG. 1(b) is a plan view showing the main parts of the LSI chip after cutting the wiring. FIG. 2 is a plan view showing the main parts of a conventional LSI chip. 1: LSI chip, 2: circuit section, 3: wafer prober pad, 4: wire bonding pad, 5: wiring, 6: signal pad

Claims (1)

【特許請求の範囲】[Claims] （１）半導体集積回路チップの周辺にワイヤボンディン
グ用パッドと、前記ワイヤボンディング用パッドよりも
大面積のウェハープローバ用のパッドと、これら両パッ
ドと内部回路とを接続する配線とを形成し、前記ウェハ
ープローバ用パッドに対するプローピングを行った後に
、前記ウェハープローバ用パッドと前記ワイヤボンディ
ング用パッド及び内部回路とを接続する配線を切断する
ことを特徴とする半導体集積回路の製造方法。(1) A wire bonding pad, a wafer prober pad having a larger area than the wire bonding pad, and wiring connecting these pads to the internal circuit are formed around the semiconductor integrated circuit chip; 1. A method of manufacturing a semiconductor integrated circuit, comprising: probing a wafer prober pad, and then cutting a wire connecting the wafer prober pad, the wire bonding pad, and an internal circuit.
JP1062694A 1989-03-15 1989-03-15 Manufacture of semiconductor integrated circuit Pending JPH02241046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1062694A JPH02241046A (en) 1989-03-15 1989-03-15 Manufacture of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1062694A JPH02241046A (en) 1989-03-15 1989-03-15 Manufacture of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02241046A true JPH02241046A (en) 1990-09-25

Family

ID=13207660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1062694A Pending JPH02241046A (en) 1989-03-15 1989-03-15 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02241046A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004041961B3 (en) * 2004-08-31 2006-03-30 Infineon Technologies Ag Integrated semiconductor circuit with integrated capacitance between Kontaktanscluss and substrate and method for their preparation
US7482675B2 (en) 2005-06-24 2009-01-27 International Business Machines Corporation Probing pads in kerf area for wafer testing
WO2009141402A1 (en) * 2008-05-22 2009-11-26 Stmicroelectronics (Grenoble) Sas Method for manufacturing and testing an integrated electronic circuit
US8183695B2 (en) 2007-11-26 2012-05-22 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004041961B3 (en) * 2004-08-31 2006-03-30 Infineon Technologies Ag Integrated semiconductor circuit with integrated capacitance between Kontaktanscluss and substrate and method for their preparation
US7482675B2 (en) 2005-06-24 2009-01-27 International Business Machines Corporation Probing pads in kerf area for wafer testing
US8183695B2 (en) 2007-11-26 2012-05-22 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
WO2009141402A1 (en) * 2008-05-22 2009-11-26 Stmicroelectronics (Grenoble) Sas Method for manufacturing and testing an integrated electronic circuit
FR2931586A1 (en) * 2008-05-22 2009-11-27 St Microelectronics Grenoble METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT
US8232113B2 (en) 2008-05-22 2012-07-31 Stmicroelectronics (Grenoble) Sas Method for manufacturing and testing an integrated electronic circuit

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