JPH0223671A - Non-volatile semiconductor memory device and manufacture thereof - Google Patents
Non-volatile semiconductor memory device and manufacture thereofInfo
- Publication number
- JPH0223671A JPH0223671A JP17354288A JP17354288A JPH0223671A JP H0223671 A JPH0223671 A JP H0223671A JP 17354288 A JP17354288 A JP 17354288A JP 17354288 A JP17354288 A JP 17354288A JP H0223671 A JPH0223671 A JP H0223671A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type diffusion
- type
- semiconductor substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000010410 layer Substances 0.000 claims abstract description 115
- 238000009792 diffusion process Methods 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は不揮発性半導体記憶装置およびその製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.
（従来の技術）
従来のＥＰＲＯＭの断面を第５図に示す。このＥＰＲＯ
Ｍはｐ型シリコン基板１内にドレイン２ａ、およびソー
ス２ｂとなるｎ型拡散層が形成されている。そして、ｐ
型シリコン基板１のチャネルとなる領域上にゲート酸化
膜３ａを介してポリシリコンからなる浮遊ゲート４．絶
縁膜５．およびポリシリコンからなる制御ゲート６を有
している２層構造のゲート電極が形成されており、また
ソースとなるｎ型拡散層２ｂと浮遊ゲート４との間に絶
縁膜３ｂを介してポリシリコンからなる浮遊ゲー）７ａ
が形成されている。(Prior Art) A cross section of a conventional EPROM is shown in FIG. This EPRO
M has an n-type diffusion layer formed in a p-type silicon substrate 1 to become a drain 2a and a source 2b. And p
A floating gate 4 made of polysilicon is formed on a region of the silicon substrate 1 that will become a channel via a gate oxide film 3a. Insulating film5. A gate electrode with a two-layer structure having a control gate 6 made of polysilicon and polysilicon is formed, and polysilicon Floating game consisting of) 7a
is formed.
上述のＥＰＲＯＭの書き込みおよび読み出しの動作原理
を第６図を用いて説明する。The operating principle of writing and reading the above-mentioned EPROM will be explained with reference to FIG.
書き込み時は制御ゲート６に１０数■、ドレインとなる
ｎ型拡散層２ａに数Ｖの電圧をそれぞれ印加し、ｐ型シ
リコン基板１およびソースとなるｎ型拡散層を接地する
。すると容量比により浮遊ゲート４、および７ａに電位
が生じ、ｐ型シリコン基板１のチャネル領域表面に反転
層１１が形成される。そしてドレインとなるｎ型拡散層
２ａに印加された数Ｖの電圧は、はとんど絶縁物３ｂ直
下の基板に生じる空乏層１０に掛り、空乏層１０に高電
界が生じる。このため空乏層１０中で電子および正孔が
発生し、ゲート酸化膜３ａを通して浮遊ゲート４に電子
が注入される。During writing, a voltage of several volts is applied to the control gate 6 and a voltage of several volts to the n-type diffusion layer 2a, which becomes the drain, and the p-type silicon substrate 1 and the n-type diffusion layer, which becomes the source, are grounded. Then, a potential is generated at the floating gates 4 and 7a due to the capacitance ratio, and an inversion layer 11 is formed on the surface of the channel region of the p-type silicon substrate 1. The voltage of several volts applied to the n-type diffusion layer 2a serving as the drain is applied to the depletion layer 10 formed in the substrate directly under the insulator 3b, and a high electric field is generated in the depletion layer 10. Therefore, electrons and holes are generated in the depletion layer 10, and the electrons are injected into the floating gate 4 through the gate oxide film 3a.
これに対して読み出し時は、制御ゲート６に数ｖ１ ド
レインとなる拡散層２ａに数Ｖの電圧をそれぞれ印加し
、ｐ型シリコン基板１およびソースとなるｎ型拡散層２
ｂを接地する。すると浮遊ゲート４に電子が注入されて
いる場合は反転層１１が形成されず電流は流れない。ま
た、電子が注入されていない場合は反転層１１が形成さ
れ、電流は流れる。On the other hand, at the time of reading, a voltage of several volts is applied to the control gate 6 and a voltage of several volts is applied to the diffusion layer 2a which becomes the drain, and the voltage of several volts is applied to the p-type silicon substrate 1 and the n-type diffusion layer 2a which becomes the source.
Ground b. Then, when electrons are injected into the floating gate 4, the inversion layer 11 is not formed and no current flows. Furthermore, when no electrons are injected, an inversion layer 11 is formed and current flows.
（発明が解決しようとする課題）
このように従来のＥＰＲＯＭの書き込み動作（浮遊ゲー
ト４への電子の注入）は、絶縁膜３ｂで隔てられた反転
層１１の間に、ドレインとなるｎ型拡散層２ａに印加さ
れる電圧によって空乏層１０を生じさせ、この空乏層１
０の電界によって発生した電子、正孔対を制御ゲート６
に印加される電圧によって浮遊ゲート４へ電子注入させ
る。(Problem to be Solved by the Invention) As described above, in the write operation (injection of electrons into the floating gate 4) of the conventional EPROM, an n-type diffusion that becomes the drain is performed between the inversion layer 11 separated by the insulating film 3b. A depletion layer 10 is generated by the voltage applied to the layer 2a, and this depletion layer 1
A control gate 6 controls electron and hole pairs generated by an electric field of 0.
Electrons are injected into the floating gate 4 by the voltage applied to the floating gate 4.
また、読み出し動作においても反転層１１の間に空乏層
を生じさせなければチャネル電流を得ることができず、
空乏層１０中で電子・正孔対が発生してしまう。この時
、反転層１１を形成するためには、制御ゲート６に電位
を与えなければならず、読み出し動作を行うことにより
軽い書き込み動作（誤書き込み動作）が発生してしまう
という問題点があった。また、書き込み動作中に浮遊ゲ
−１７ａへの電子注入も軽く起こり、読み出し電流を低
下させるという問題点もあった。Furthermore, in the read operation, a channel current cannot be obtained unless a depletion layer is created between the inversion layers 11.
Electron/hole pairs are generated in the depletion layer 10. At this time, in order to form the inversion layer 11, it is necessary to apply a potential to the control gate 6, and there is a problem in that a light write operation (erroneous write operation) occurs when a read operation is performed. . Further, there is also the problem that electron injection into the floating gate 17a occurs lightly during the write operation, reducing the read current.
本発明は上記問題点を考慮してなされたものであって、
読み出し時に誤書き込み動作を発生させることがなく、
また書き込み動作中に読み出し電流の低下を生じさせな
い不揮発性半導体記憶装置およびその製造方法を提供す
ることを目的とする。The present invention has been made in consideration of the above problems, and includes:
No erroneous write operation occurs during reading,
Another object of the present invention is to provide a nonvolatile semiconductor memory device that does not cause a drop in read current during a write operation, and a method for manufacturing the same.
（課題を解決するための手段）
本発明による不揮発性半導体記憶装置の製造方法は、ｐ
型半導体基板上の所定の領域に第１のｎ型拡散層を形成
する工程と、ｐ型半導体基板上に第１のゲート酸化膜を
形成する工程と、第１のゲート酸化膜上に第１ポリシリ
コン膜、絶縁膜、および第２ポリシリコン膜を順次積層
する工程と、第１ポリシリコン膜、絶縁膜、および第２
ポリシリコン膜からなる積層膜をパターニングして第１
のｎ型拡散層の境界の一部を含む近傍領域上にゲート電
極を形成する工程と、ゲート電極直下以外の第１のゲー
ト酸化膜を除去する工程と、ｐ型半導体基板のゲート電
極形成面側に第２のゲート酸化膜および第３ポリシリコ
ン膜を順次積層する工程と、第１のｎ型拡散層側の第３
ポリシリコン膜を除去する工程と、前記ゲート電極を挟
んで第１のｎ型拡散層と反対側のｐ型半導体基板上に第
２のｎ型拡散層を形成する工程と、前記第１のｎ型拡散
層中にｎ型拡散層を形成する工程と、全面に層間絶縁膜
を堆積する工程と、ゲート電極との接続孔および第２の
ｎ型拡散層との接続孔、ならびに第１のｎ型拡散層とｎ
型拡散層との共用接続孔をそれぞれ開孔する工程と、開
孔された接続孔に金属を埋め込む工程とを備えているこ
とを特徴とする。(Means for Solving the Problems) A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes p
forming a first n-type diffusion layer in a predetermined region on the p-type semiconductor substrate, forming a first gate oxide film on the p-type semiconductor substrate, and forming a first n-type diffusion layer on the first gate oxide film. A step of sequentially stacking a polysilicon film, an insulating film, and a second polysilicon film;
The first layer is patterned by patterning the laminated film made of polysilicon film.
a step of forming a gate electrode on a neighboring region including a part of the boundary of the n-type diffusion layer; a step of removing the first gate oxide film other than directly under the gate electrode; and a step of forming the gate electrode on the gate electrode formation surface of the p-type semiconductor substrate. a process of sequentially laminating a second gate oxide film and a third polysilicon film on the side of the first n-type diffusion layer;
a step of removing the polysilicon film; a step of forming a second n-type diffusion layer on the p-type semiconductor substrate on the opposite side of the first n-type diffusion layer with the gate electrode in between; A step of forming an n-type diffusion layer in the type diffusion layer, a step of depositing an interlayer insulating film on the entire surface, a connection hole with the gate electrode, a connection hole with the second n-type diffusion layer, and the first n-type diffusion layer. type diffusion layer and n
The method is characterized by comprising the steps of respectively opening common connection holes with the mold diffusion layer, and filling the opened connection holes with metal.
本発明による不揮発性半導体記憶装置は、ｐ型半導体基
板上のチャネルとなる領域を挟んでソースおよびドレイ
ンとなるｎ型拡散層を前記ｐ型半導体基板上に形成し、
ドレインとなるｎ型拡散層中にｐ型半導体基板をドレイ
ンとし、ドレインとなるｎ型拡散層をチャネルとする領
域を挟んでソースとなるｎ型拡散層を形成し、ｐ型半導
体基板上のチャネルとなる領域の一部とｎ型拡散層のチ
ャネルとする領域とにまたがるようにゲート酸化膜を介
して第１の浮遊ゲートを形成し、この第１の浮遊ゲート
上に絶縁膜を介して制御ゲートを形成し、ソースとなる
ｎ型拡散層と第１の浮遊ゲトとの間の、ｐ型半導体基板
上のチャネルとなる領域上に、ｐ型半導体基板とはゲー
ト酸化膜を介し、第１の浮遊ゲートとは絶縁膜を介して
第２の浮遊ゲートを形成したことを特徴とする。A non-volatile semiconductor memory device according to the present invention includes forming an n-type diffusion layer to become a source and a drain on the p-type semiconductor substrate, sandwiching a region to become the channel on the p-type semiconductor substrate;
A p-type semiconductor substrate is used as a drain in an n-type diffused layer that becomes a drain, and an n-type diffused layer that becomes a source is formed with a region that uses the n-type diffused layer that becomes a drain as a channel, and a channel on the p-type semiconductor substrate is formed. A first floating gate is formed via a gate oxide film so as to straddle a part of the region to be used as a channel of the n-type diffusion layer, and a control gate is formed on this first floating gate via an insulating film. The p-type semiconductor substrate is connected to the p-type semiconductor substrate via a gate oxide film on the region that will become the channel between the n-type diffusion layer that forms the gate and becomes the source and the first floating gate. The floating gate is characterized in that a second floating gate is formed with an insulating film interposed therebetween.
（作 用）
このように構成された本発明による不揮発性半導体記憶
装置およびその製造方法によれば、ドレインとなる第１
のｎ型拡散層中にｐ型の拡散層が形成される。そして書
き込みは第１のｎ型拡散層とソースとなる第２のｎ型拡
散層間をチャネルとするｎ型トランジスタで行わせ、読
み出しはｐ型半導体基板とｎ型拡散層間の第１のｎ型拡
散層をチャネルとするｐ型トランジスタで行わせること
により読み出し時に誤書き込み動作を発生させることが
なく、又、書き込み動作中に読み出し電流の低下を生じ
させないこととなる。(Function) According to the nonvolatile semiconductor memory device and the manufacturing method thereof according to the present invention configured as described above, the first
A p-type diffusion layer is formed in the n-type diffusion layer. Writing is performed using an n-type transistor whose channel is between the first n-type diffusion layer and a second n-type diffusion layer serving as a source, and reading is performed using the first n-type diffusion layer between the p-type semiconductor substrate and the n-type diffusion layer. By using a p-type transistor that uses the layer as a channel, an erroneous write operation will not occur during reading, and a drop in read current will not occur during the write operation.
（実施例）
第１図に本発明による不揮発性半導体記憶装置の製造工
程の一実施例を示す。第１図（ａ）において、ｐ型シリ
コン基板１の表層内にイオン注入によってドレインとな
るｎ型拡散層２を形成する。(Example) FIG. 1 shows an example of the manufacturing process of a nonvolatile semiconductor memory device according to the present invention. In FIG. 1(a), an n-type diffusion layer 2 which becomes a drain is formed in the surface layer of a p-type silicon substrate 1 by ion implantation.
その後、熱酸化により数百オングストローム（人）のゲ
ート酸化膜３ａを形成し、その上にポリシリコン膜４、
絶縁膜５、およびポリシリコン膜６を順次積層する（第
１図（ａ）参照）。次にレジストを塗布してマスク（図
示せず）を形成し、このマスクを用いてエツチングを行
って、ポリシリコン膜４、絶縁膜５、およびポリシリコ
ン膜６からなるゲート電極１５を形成する（第１図（ｂ
）参照）。なおこの時、ゲート電極１５をｎ型拡散層２
とｐ型半導体基板１のチャネルとなる領域にまたかるよ
うに形成する。ゲート電極１５を形成後、ゲート電極１
５直下の部分を除いてフッ化アンモニウム等を用いてゲ
ート酸化膜３ａを除去する（第１図（ｂ）参照）。その
後熱酸化によりゲート酸化膜３ｂを形成し、その上にポ
リシリコンを堆積してポリシリコン膜７を形成する（第
１図（ｂ）参照）。Thereafter, a gate oxide film 3a of several hundred angstroms (thickness) is formed by thermal oxidation, and a polysilicon film 4,
An insulating film 5 and a polysilicon film 6 are sequentially laminated (see FIG. 1(a)). Next, a resist is applied to form a mask (not shown), and etching is performed using this mask to form a gate electrode 15 consisting of a polysilicon film 4, an insulating film 5, and a polysilicon film 6 ( Figure 1 (b
)reference). At this time, the gate electrode 15 is connected to the n-type diffusion layer 2.
and a region of p-type semiconductor substrate 1 that will become a channel. After forming the gate electrode 15, the gate electrode 1
The gate oxide film 3a is removed using ammonium fluoride or the like, except for the portion immediately below the gate oxide film 3a (see FIG. 1(b)). Thereafter, a gate oxide film 3b is formed by thermal oxidation, and polysilicon is deposited thereon to form a polysilicon film 7 (see FIG. 1(b)).
ＲＩＥ（反応性イオンエツチング）を行うことによりゲ
ート電極１５の、側面だけにポリシリコン膜７を残す。By performing RIE (reactive ion etching), polysilicon film 7 is left only on the side surfaces of gate electrode 15.
レジストを塗布してマスク（図示せず）を形成し、この
マスクを用いてｎ型拡散層側のポリシリコン膜７をＣＤ
Ｅ （反応性ドライエツチング）などで除去する。する
とゲート電極１５の、ｎ型拡散層２と反対側の側面だけ
にポリシリコン膜７ａが残る（第１図（Ｃ）参照）。A resist is applied to form a mask (not shown), and using this mask, the polysilicon film 7 on the n-type diffusion layer side is formed by CD.
Remove by E (reactive dry etching) etc. Then, the polysilicon film 7a remains only on the side surface of the gate electrode 15 opposite to the n-type diffusion layer 2 (see FIG. 1(C)).
その後、イオン注入することによりｎ型拡散層２中にｎ
型拡散層９を形成するとともに、ｐ型半導体基板１のチ
ャネルとなる領域をｎ型拡散層２と挾むようにソースと
なるｎ型拡散層８をそれぞれ形成する（第１図（Ｃ）参
照）。そして層間絶縁膜２０を堆積し、ｎ型拡散層２と
ｎ型拡散層９との共用接続孔、およびゲート電極１５と
の接続孔、ならびにｎ型拡散層８との接続孔を開孔し、
これらの接続孔にＡｌｌなどの金属を埋め込み、電極２
１ａ、２１ｂ、２１ｃを形成する（第１図（ｄ）参照）
。Thereafter, ions are implanted into the n-type diffusion layer 2.
At the same time as forming the type diffusion layer 9, the n-type diffusion layer 8 which becomes the source is formed so as to sandwich the region of the p-type semiconductor substrate 1 which becomes the channel with the n-type diffusion layer 2 (see FIG. 1C). Then, an interlayer insulating film 20 is deposited, and a common connection hole between the n-type diffusion layer 2 and the n-type diffusion layer 9, a connection hole with the gate electrode 15, and a connection hole with the n-type diffusion layer 8 are opened,
Fill these connection holes with metal such as Al, and connect the electrode 2.
1a, 21b, and 21c are formed (see FIG. 1(d)).
.
第２図に本発明による不揮発性半導体記憶装置の一実施
例を示す。この実施例の不揮発性半導体記憶装置（以下
、半導体装置という）は、ｐ型シリコン基板１の表面層
内に、チャネルとなる領域を挟んでｎ型トランジスタの
ドレインおよびソースとなるｎ型拡散層２および８が形
成されている。FIG. 2 shows an embodiment of a nonvolatile semiconductor memory device according to the present invention. The non-volatile semiconductor memory device (hereinafter referred to as a semiconductor device) of this embodiment has an n-type diffusion layer 2 that serves as the drain and source of an n-type transistor in the surface layer of a p-type silicon substrate 1, with a region that will become a channel sandwiched therebetween. and 8 are formed.
そして、ドレインとなるｎ型拡散層２の一部にｐ型トラ
ンジスタのソースとなるｎ型拡散層９が形成されている
。また、ｐ型シリコン基板１のチャネルとなる領域とｎ
型拡散層２とにまたがるように形成されたゲート酸化膜
３ａ上にポリシリコンからなる浮遊ゲート４、絶縁膜５
、およびポリシリコンからなる制御ゲート６を有するゲ
ート電極１５が形成されている。そして、ソースとなる
ｎ型拡散層８と浮遊ゲート４との間に絶縁膜３ｂを介し
てポリシコンからなる浮遊ゲート７ａが配置されている
。An n-type diffusion layer 9, which will become a source of a p-type transistor, is formed in a part of the n-type diffusion layer 2, which will become a drain. In addition, a region that becomes a channel of the p-type silicon substrate 1 and an n
A floating gate 4 made of polysilicon and an insulating film 5 are formed on the gate oxide film 3a formed so as to span the type diffusion layer 2.
, and a gate electrode 15 having a control gate 6 made of polysilicon. A floating gate 7a made of polysilicon is placed between the n-type diffusion layer 8 serving as a source and the floating gate 4 with an insulating film 3b interposed therebetween.
次に、上記実施例の半導体装置の書き込みおよび読み出
しの動作原理を第３図および第４図を用いて説明する。Next, the operating principle of writing and reading of the semiconductor device of the above embodiment will be explained with reference to FIGS. 3 and 4.
第３図において、書き込み時は、制御ゲート６に１０数
Ｖの電圧を印加し、ｎ型拡散層２とｎ型拡散層９を同電
位で数Ｖの電圧を印加する。そしてｐ型シリコン基板１
とソースとなるｎ型拡散層８を接地する。この時、容量
比により浮遊ゲート４および７ａにプラスの電位が生じ
、反転層１１が形成される。そして、ドレインとなるｎ
型拡散層２に印加された数Ｖの電圧のほとんどは、絶縁
物３ｂ直下のｐ型シリコン基板１に生じている空乏層１
０に掛り、高電界を生じる。このため空乏層１０中で電
子および正孔が発生し、電子は浮遊ポリシリコンゲート
４にゲート酸化膜３ａを通して注入される。In FIG. 3, during writing, a voltage of several tens of volts is applied to the control gate 6, and a voltage of several volts is applied to the n-type diffusion layer 2 and the n-type diffusion layer 9 at the same potential. and p-type silicon substrate 1
The n-type diffusion layer 8, which becomes the source, is grounded. At this time, a positive potential is generated in floating gates 4 and 7a due to the capacitance ratio, and inversion layer 11 is formed. Then, n becomes the drain.
Most of the voltage of several volts applied to the type diffusion layer 2 is absorbed by the depletion layer 1 generated in the p-type silicon substrate 1 directly under the insulator 3b.
0, producing a high electric field. Therefore, electrons and holes are generated in depletion layer 10, and the electrons are injected into floating polysilicon gate 4 through gate oxide film 3a.
これに対して読み出し時は、第４図に示すように制御ゲ
ート６、およびｎ型拡散層８、ならびにｐ型シリコン基
板１を接地し、ドレイン、となるｎ型拡散層２、および
ｎ型拡散層９を同電位とし、数■の電圧を印加する。こ
の時、浮遊ゲート４に電子が注入されていなければ正孔
の反転層１０が形成されず、電流は流れない。また、電
子が注入されていれば正孔の反転層１２が形成され、ｎ
型拡散層９、反転層１２、ｐ型シリコン基板の径路で電
流が流れる。On the other hand, at the time of reading, as shown in FIG. Layer 9 is brought to the same potential and a voltage of several square meters is applied. At this time, if electrons are not injected into the floating gate 4, the hole inversion layer 10 will not be formed and no current will flow. Furthermore, if electrons are injected, a hole inversion layer 12 is formed, and n
A current flows through the path between the type diffusion layer 9, the inversion layer 12, and the p-type silicon substrate.
以上述べたことから本実施例によれば、書き込みは、ド
レインとなるｎ型拡散層２とソースとなるｎ型拡散層８
との間をチャネルとするｎ型トランジスタで行い、読み
出しはｐ型シリコン基板１とソースとなるｎ型拡散層９
との間のｎ型拡散層２をチャネルとするｐ型トランジス
タで行うことにより読み出し時の誤書き込みを生じさせ
ないばかりでなく書き込み動作中に読み出し電流の低下
を生じさせないこととなる。As described above, according to this embodiment, writing is performed between the n-type diffusion layer 2 which becomes the drain and the n-type diffusion layer 8 which becomes the source.
Reading is performed by an n-type transistor whose channel is between the p-type silicon substrate 1 and the n-type diffusion layer 9 that serves as the source.
By using a p-type transistor whose channel is the n-type diffusion layer 2 between the write operation and the write operation, not only does erroneous writing during reading not occur, but also no drop in read current occurs during the write operation.
本発明によれば、読み出し時に誤書き込み動作を発生さ
せないばかりでなく、書き込み動作中に読み出し電流の
低下を生じさせないことにより信頼性の向上を計ること
ができる。According to the present invention, reliability can be improved by not only preventing an erroneous write operation from occurring during a read operation, but also preventing a drop in read current from occurring during a write operation.
第１図は本発明による不揮発性半導体記憶装置の製造工
程を示す断面図、第２図は本発明による不揮発性半導体
記憶装置の一実施例を示す断面図、第３図および第４図
は本発明による不揮発性半導体記憶装置の動作を説明す
る断面図、第５図は従来の不揮発性半導体記憶装置を示
す断面図、第６図は従来の不揮発性半導体記憶装置の動
作を説明する断面図である。
１・・・ｐ型シリコン基板、２・・・ｎ型拡散層（ドレ
イン）、３ａ・・・ゲート酸化膜、４・・・ポリシリコ
ン膜（浮遊ゲート）、５・・・絶縁膜、６・・・ポリシ
リコン膜（制御ゲート）、７・・・ポリシリコン膜、７
ａ・・・浮遊ゲート、８・・・ｎ型拡散層（ソース）、
９・・・ｎ型拡散層、１５・・・ゲート電極、２０・・
・層間絶縁膜、２１ ａ ｓ ２ ｌ ｂ ％ ２１
ｃ ・・・電極。
出願人代理人 佐 藤 −雄FIG. 1 is a cross-sectional view showing the manufacturing process of a non-volatile semiconductor memory device according to the present invention, FIG. 2 is a cross-sectional view showing an embodiment of the non-volatile semiconductor memory device according to the present invention, and FIGS. FIG. 5 is a cross-sectional view illustrating the operation of the non-volatile semiconductor memory device according to the invention; FIG. 5 is a cross-sectional view illustrating the conventional non-volatile semiconductor memory device; FIG. be. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... N-type diffusion layer (drain), 3a... Gate oxide film, 4... Polysilicon film (floating gate), 5... Insulating film, 6... ...Polysilicon film (control gate), 7...Polysilicon film, 7
a: floating gate, 8: n-type diffusion layer (source),
9... N-type diffusion layer, 15... Gate electrode, 20...
・Interlayer insulating film, 21 a s 2 l b % 21
c...electrode. Applicant's agent Mr. Sato
Claims (1)
を形成する工程と、前記ｐ型半導体基板上に第１のゲー
ト酸化膜を形成する工程と、前記第１のゲート酸化膜上
に第１ポリシリコン膜、絶縁膜、および第２ポリシリコ
ン膜を順次積層する工程と、前記第１ポリシリコン膜、
絶縁膜、および第２ポリシリコン膜からなる積層膜をパ
ターニングして前記第１のｎ型拡散層の境界の一部を含
む近傍領域上にゲート電極を形成する工程と、前記ゲー
ト電極直下以外の前記第１のゲート酸化膜を除去する工
程と、前記ｐ型半導体基板のゲート電極形成面側に第２
のゲート酸化膜および第３ポリシリコン膜を順次積層す
る工程と、前記第１のｎ型拡散層側の第３ポリシリコン
膜を除去する工程と、前記ゲート電極を挟んで第１のｎ
型拡散層と反対側のｐ型半導体基板上に第２のｎ型拡散
層を形成する工程と、前記第１のｎ型拡散層中にｐ型拡
散層を形成する工程と、全面に層間絶縁膜を堆積する工
程と、前記ゲート電極との接続孔および前記第２のｎ型
拡散層との接続孔、ならびに前記第１のｎ型拡散層とｐ
型拡散層との共用接続孔をそれぞれ開孔する工程と、開
孔された接続孔に金属を埋め込む工程とを備えているこ
とを特徴とする不揮発性半導体記憶装置の製造方法。 ２、ｐ型半導体基板上のチャネルとなる領域を挟んでソ
ースおよびドレインとなるｎ型拡散層を前記ｐ型半導体
基板上に形成し、前記ドレインとなるｎ型拡散層中に前
記ｐ型半導体基板をドレインとし、前記ドレインとなる
ｎ型拡散層をチャネルとする領域を挟んでソースとなる
ｐ型拡散層を形成し、前記ｐ型半導体基板上のチャネル
となる領域の一部と前記ｎ型拡散層のチャネルとする領
域とにまたがるようにゲート酸化膜を介して第１の浮遊
ゲートを形成し、この第１の浮遊ゲート上に絶縁膜を介
して制御ゲートを形成し、前記ソースとなるｎ型拡散層
と第１の浮遊ゲートとの間の、前記ｐ型半導体基板上の
チャネルとなる領域上に、前記ｐ型半導体基板とはゲー
ト酸化膜を介し、前記第１の浮遊ゲートとは絶縁膜を介
して第２の浮遊ゲートを形成したことを特徴とする不揮
発性半導体記憶装置。[Claims] 1. A step of forming a first n-type diffusion layer in a predetermined region on a p-type semiconductor substrate; a step of forming a first gate oxide film on the p-type semiconductor substrate; a step of sequentially laminating a first polysilicon film, an insulating film, and a second polysilicon film on the first gate oxide film, the first polysilicon film,
patterning a laminated film consisting of an insulating film and a second polysilicon film to form a gate electrode on a neighboring region including a part of the boundary of the first n-type diffusion layer; removing the first gate oxide film; and removing a second gate oxide film on the gate electrode forming surface side of the p-type semiconductor substrate.
a step of sequentially stacking a gate oxide film and a third polysilicon film; a step of removing the third polysilicon film on the side of the first n-type diffusion layer;
A step of forming a second n-type diffusion layer on the p-type semiconductor substrate on the opposite side to the type diffusion layer, a step of forming a p-type diffusion layer in the first n-type diffusion layer, and an interlayer insulating layer on the entire surface. a step of depositing a film, a connection hole with the gate electrode, a connection hole with the second n-type diffusion layer, and a connection hole with the first n-type diffusion layer;
1. A method of manufacturing a nonvolatile semiconductor memory device, comprising the steps of: opening common connection holes with a type diffusion layer; and filling the opened connection holes with metal. 2. Form an n-type diffusion layer that will become a source and a drain on the p-type semiconductor substrate across a region that will become a channel on the p-type semiconductor substrate, and form the p-type semiconductor substrate in the n-type diffusion layer that will become the drain. forming a p-type diffusion layer serving as a source across a region in which the n-type diffusion layer serving as the drain serves as a drain, and a region serving as a channel on the p-type semiconductor substrate and a portion of the n-type diffusion layer serving as a channel on the p-type semiconductor substrate. A first floating gate is formed via a gate oxide film so as to span the region of the layer that is to be a channel, a control gate is formed on the first floating gate via an insulating film, and the n A region between the type diffusion layer and the first floating gate, which will become a channel on the p-type semiconductor substrate, is connected to the p-type semiconductor substrate through a gate oxide film and is insulated from the first floating gate. A nonvolatile semiconductor memory device characterized in that a second floating gate is formed through a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17354288A JPH0223671A (en) | 1988-07-12 | 1988-07-12 | Non-volatile semiconductor memory device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17354288A JPH0223671A (en) | 1988-07-12 | 1988-07-12 | Non-volatile semiconductor memory device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223671A true JPH0223671A (en) | 1990-01-25 |
Family
ID=15962462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17354288A Pending JPH0223671A (en) | 1988-07-12 | 1988-07-12 | Non-volatile semiconductor memory device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223671A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0533546A (en) * | 1991-07-25 | 1993-02-09 | Sanyo Electric Co Ltd | Hinge |
| US5488245A (en) * | 1993-03-19 | 1996-01-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of electrically erasing and writing information |
| JPH10184115A (en) * | 1996-10-04 | 1998-07-14 | Federal Hoffmann Inc | Handle device |
-
1988
- 1988-07-12 JP JP17354288A patent/JPH0223671A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0533546A (en) * | 1991-07-25 | 1993-02-09 | Sanyo Electric Co Ltd | Hinge |
| US5488245A (en) * | 1993-03-19 | 1996-01-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of electrically erasing and writing information |
| US5683923A (en) * | 1993-03-19 | 1997-11-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of electrically erasing and writing information and a manufacturing method of the same |
| JPH10184115A (en) * | 1996-10-04 | 1998-07-14 | Federal Hoffmann Inc | Handle device |
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