JPH0223639A - Diamond multilayer circuit substrate - Google Patents
Diamond multilayer circuit substrateInfo
- Publication number
- JPH0223639A JPH0223639A JP17259488A JP17259488A JPH0223639A JP H0223639 A JPH0223639 A JP H0223639A JP 17259488 A JP17259488 A JP 17259488A JP 17259488 A JP17259488 A JP 17259488A JP H0223639 A JPH0223639 A JP H0223639A
- Authority
- JP
- Japan
- Prior art keywords
- diamond
- substrate
- multilayer
- multilayer circuit
- base substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 50
- 239000010432 diamond Substances 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 239000010410 layer Substances 0.000 claims abstract description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 17
- 239000012808 vapor phase Substances 0.000 claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000003786 synthesis reaction Methods 0.000 claims description 8
- 239000007789 gas Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 3
- 239000004215 Carbon black (E152) Substances 0.000 abstract description 2
- 238000010891 electric arc Methods 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 229930195733 hydrocarbon Natural products 0.000 abstract description 2
- 150000002430 hydrocarbons Chemical class 0.000 abstract description 2
- 238000012423 maintenance Methods 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 230000000191 radiation effect Effects 0.000 abstract 1
- 239000012495 reaction gas Substances 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000498 cooling water Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000001308 synthesis method Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置搭載用多層回路基板、より詳しくは、ダイヤ
モンドの絶縁性と放熱特性とを利用したダイヤモンドの
多層回路基板に関し、
従来よりも熱伝導率の高い多層回路基板を提供し、かつ
極めて高い素子実装密度の高性能電子機器に適する多層
回路基板を提供することを目的とし、
気相合成法によって作製されたダイヤモンド下地基板と
、該下地基板の表面上に形成された多層配線と、これら
多層配線の間にあって気相合成法によって形成されたダ
イヤモンドの層間絶縁層とからなることを特徴とするダ
イヤモンド多層回路基板に構成する。[Detailed Description of the Invention] [Summary] This invention relates to a multilayer circuit board for mounting semiconductor devices, more specifically, a diamond multilayer circuit board that utilizes the insulating properties and heat dissipation properties of diamond. With the aim of providing circuit boards and multilayer circuit boards suitable for high-performance electronic devices with extremely high element packaging density, we have developed a diamond base substrate produced by vapor phase synthesis, and A diamond multilayer circuit board is constructed, comprising the formed multilayer wiring and a diamond interlayer insulating layer formed by vapor phase synthesis between the multilayer wiring.
本発明は、半導体装置搭載用多層回路基板、より詳しく
は、ダイヤモンドの絶縁性と放熱特性とを利用したダイ
ヤモンドの多層回路基板に関する。The present invention relates to a multilayer circuit board for mounting semiconductor devices, and more particularly, to a multilayer circuit board made of diamond that utilizes the insulating properties and heat dissipation properties of diamond.
科学技術計算用の超高速コンピュータ（いわゆるスーパ
ーコンピュータ）等の高性能電子機器では、その性能を
上げるために、半導体素子（装置）を高密度に実装しな
ければならず、素子の発熱が多くなり、この発熱をいか
に逃がす（放熱する）かが重要な問題である。In high-performance electronic devices such as ultra-high-speed computers for scientific and technical calculations (so-called supercomputers), in order to improve their performance, semiconductor elements (devices) must be mounted in high density, which causes the elements to generate a lot of heat. An important issue is how to release (radiate) this heat.
従来、半導体素子を直接載せる基板（多層回路基板）に
はアルミナ（熱伝導率２０Ｗ／ｍＫ）製が多く、それよ
りも熱伝導率の高い窒化アルミナや炭化珪素（熱伝導率
２００Ｗ／ｍＫ）製を、近年、用いるようにもなってき
た。Conventionally, substrates (multilayer circuit boards) on which semiconductor elements are directly mounted are often made of alumina (thermal conductivity 20 W/mK), but are also made of alumina nitride or silicon carbide (thermal conductivity 200 W/mK), which have higher thermal conductivity. has come to be used in recent years.
現状では、さらに熱伝導率の高い材料で作られた回路基
板が求められている。Currently, there is a demand for circuit boards made of materials with even higher thermal conductivity.
また、高性能電子機器における実装では、放熱の他に半
導体素子間の高密度配線も考慮する必要がある。従来は
放熱サイドと配線サイドを素子に対して分離する方法（
例えば、素子の表側を配線サイドとし裏側から冷却する
）を採用することが多く、この場合には、実装形態がた
いへん複雑となる欠点があった。Furthermore, when mounting in high-performance electronic equipment, it is necessary to consider not only heat radiation but also high-density wiring between semiconductor elements. Conventionally, the method of separating the heat dissipation side and the wiring side with respect to the element (
For example, it is often the case that the front side of the device is used as the wiring side and the device is cooled from the back side.In this case, there is a drawback that the mounting form becomes very complicated.
本発明の目的は、従来よりも熱伝導率の高い多層回路基
板を提供し、かつ極めて高い素子実装密度の高性能電子
機器に適する多層回路基板を提供することである。An object of the present invention is to provide a multilayer circuit board that has higher thermal conductivity than conventional ones and is suitable for high-performance electronic equipment with extremely high element packaging density.
上述の目的が、気相合成法によって作製されたダイヤモ
ンド下地基板と、該下地基板の表面上に形成された多層
配線と、これら多層配線の間にあって気相合成法によっ
て形成されたダイヤモンドの層間絶縁層とからなること
を特徴とするダイヤモンド多層回路基板によって達成さ
れる。The above purpose is to provide a diamond base substrate produced by vapor phase synthesis, a multilayer wiring formed on the surface of the base substrate, and a diamond interlayer insulation formed by vapor phase synthesis between these multilayer wiring. This is achieved by a diamond multilayer circuit board characterized in that it consists of layers.
ダイヤモンドは、その熱伝導率が２，０ＯＯＷ／ｍＫと
窒化アルミや炭化珪素の１０倍、冬さらに銅の４倍にも
相当するほど大きいので、放熱性の優れた多層回路基板
が得られる。また、ダイモンドは絶縁性も優れ、かつ低
誘導率（５〜６）であるので、これらの点からも多層回
路基板として望ましい。Diamond has a thermal conductivity of 2,000 W/mK, which is 10 times that of aluminum nitride and silicon carbide, and four times that of copper, so a multilayer circuit board with excellent heat dissipation can be obtained. Additionally, diamond has excellent insulation properties and a low dielectric constant (5 to 6), so it is desirable as a multilayer circuit board from these points as well.
以下、添付図面を参照して本発明の実施態様例によって
本発明をより詳しく説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail by way of embodiments with reference to the accompanying drawings.
第１図は本発明に係るダイヤモンド多層回路基板の部分
断面図であり、該多層回路基板はダイヤモンド下地基板
１と、配線層２． ３． ４および５と、ダイヤモンド
層間絶縁層６．７および８とからなる。FIG. 1 is a partial sectional view of a diamond multilayer circuit board according to the present invention, and the multilayer circuit board includes a diamond base substrate 1, a wiring layer 2. 3. 4 and 5, and diamond interlayer insulating layers 6.7 and 8.
下地基板１および層間絶縁層６． ７． ８はダイヤモ
ンドの気相合成法で作られる膜であり、特に本出願人が
特願昭６２−８３３１８号および６２−２２０４３７号
の特許出願にて提案したダイヤモンドの気相合成方法（
以下、直流プラズマジェットＣＶＤ法と呼ぶ）を用いて
製膜するのが好ましい。この直流プラズマジェッ）ＣＶ
Ｄ法においては、反応ガス（炭化水素ガスおよび水素ガ
ス）を直流アーク放電によりプラズマジェットとして噴
出させ、これを冷却した適切な基板にぶつけて、ダイヤ
モンドを基板上に高速に合成させることができる。Base substrate 1 and interlayer insulating layer 6. 7. 8 is a film made by a diamond vapor phase synthesis method, and in particular, the diamond vapor phase synthesis method proposed by the present applicant in patent applications No. 62-83318 and No. 62-220437
It is preferable to form the film using a direct current plasma jet CVD method (hereinafter referred to as DC plasma jet CVD method). This DC plasma jet)CV
In the D method, reactive gases (hydrocarbon gas and hydrogen gas) are ejected as a plasma jet by direct current arc discharge, and the plasma jet is bombarded with a suitable cooled substrate, thereby making it possible to synthesize diamond on the substrate at high speed.
多層配線２． ３． ４はダイヤモンド層間絶縁層６、
７． ８によって被覆されることになるので、モリブ
デン（Ｌ） 、タングステン（Ｗ）、これら金属のシリ
サイドなど高融点導体材料で作られる。Multilayer wiring 2. 3. 4 is a diamond interlayer insulating layer 6;
7. 8, it is made of a high melting point conductive material such as molybdenum (L), tungsten (W), or silicide of these metals.
そして、最上層の配線５は素子との接続が容易にかつ確
実にできるように金（Ａｕ） 、アルミニウム（Ａ１）
などの金属で作られるのが好ましく、例えば、第１図に
示すように、チタン（ＴＩ）層５Ａ、白金（ｐｔ）層５
ＢおよびＡｕ層５Ｃの三層構造の密着力の高い配線５と
することができる。The wiring 5 on the top layer is made of gold (Au) or aluminum (A1) so that it can be easily and reliably connected to the elements.
For example, as shown in FIG. 1, titanium (TI) layer 5A, platinum (PT) layer 5A, etc.
The wiring 5 can have a three-layer structure of B and Au layers 5C with high adhesion.
本発明に係る多層回路基板が次のようにして直流プラズ
マジェッ）ＣＶＤ装置（第２図）を用いて次のように製
造される。A multilayer circuit board according to the present invention is manufactured as follows using a DC plasma jet CVD apparatus (FIG. 2).
この直流プラズマジェッ）ＣＶＤ装置は、真空ポンプ（
図示せず）の排気系につながった排気管１１を有するチ
ャンバ１２の内部に、プラズマトーチ１３、基板ホルダ
１４および基板マニニプレーク１５を備えている。プラ
ズマトーチ１３はアークを発生させる直流電源１６に接
続され、原料ガスの導入管１７および冷却水用管１８が
取付けられ、さらに、チャンバ１２の天井からトーチマ
ニュプレーク１９によって可動に投首されている。This DC plasma jet) CVD equipment uses a vacuum pump (
A plasma torch 13, a substrate holder 14, and a substrate manifold plate 15 are provided inside a chamber 12 having an exhaust pipe 11 connected to an exhaust system (not shown). The plasma torch 13 is connected to a DC power supply 16 that generates an arc, has a raw material gas introduction pipe 17 and a cooling water pipe 18 attached, and is movably extended from the ceiling of the chamber 12 by a torch manipulator 19. .
プラズマトーチ１３の下方にある基板ホルダ１４は冷却
水用管２１が取付けられかつその下の基板マニュプレー
タ１５によって前後・左右・上下方向に移動可能となっ
ている。A cooling water pipe 21 is attached to a substrate holder 14 located below the plasma torch 13, and the substrate holder 14 is movable back and forth, left and right, and up and down by a substrate manipulator 15 below.
まず、上述した直流プラズマジェッ）ＣＶＤ装置（第２
図）の基板ホルダ１４の上にシリコン基板（５０ｘ５０
ｘｌ舶）２２を搭載した。チャンバ１２内部を排気して
から原料ガスとして水素ガス（５０Ａ／ｍ１ｎ）および
メタンガス（０，８４！ ／ｍ１ｎ）を導入管１７を通
してプラズマトーチ１３へ流し、チャンバ１２内圧力を
減圧状態（５０Ｔｏｒｒ）に維持した。First, the above-mentioned DC plasma jet) CVD equipment (second
A silicon substrate (50x50
xl ship) 22. After exhausting the inside of the chamber 12, hydrogen gas (50A/m1n) and methane gas (0.84!/m1n) are flowed as raw material gases through the introduction pipe 17 to the plasma torch 13, and the pressure inside the chamber 12 is reduced to a reduced pressure state (50 Torr). Maintained.
直流電源１６よりプラズマトーチ１３の陽極および陰極
（図示せず）間に直流電流（５ｋＷ）を流してアークを
発生させ、プラズマジェット２４を発生させた。シリコ
ン基板２２とプラズマトーチ１３との距離を一定（４０
＋ｎｍ）に保って、基板マニュプレータ１５によって前
後・左右に移動させながらダイヤモンド膜をシリコン基
板２２上に合成く形成した）。合成時間２０時間で厚さ
１．２ｍｍのダイヤモンド膜を作製した。そして、ＣＶ
Ｄ装置から取出し、ＹへＧレーダによってダイヤモンド
膜を所定寸法（４０Ｘ ４０ ｍｍ ）にカットし、シ
リコン基板２２よりはがし、ダイヤモンド表面を研摩し
してダイヤモンド下地基板１ （４０Ｘ４０ Ｘ １
． Ｏｍｍ）を得た。A DC current (5 kW) was passed between the anode and cathode (not shown) of the plasma torch 13 from the DC power supply 16 to generate an arc and generate a plasma jet 24 . The distance between the silicon substrate 22 and the plasma torch 13 is kept constant (40
+nm) and was moved back and forth and left and right by the substrate manipulator 15 to form a diamond film on the silicon substrate 22). A diamond film with a thickness of 1.2 mm was produced in a synthesis time of 20 hours. And CV
Take it out from the D device, cut the diamond film to a predetermined size (40 x 40 mm) using the G radar, peel it off from the silicon substrate 22, and polish the diamond surface to form a diamond base substrate 1 (40 x 40 x 1).
．． Omm) was obtained.
次に、第３Ａ図に示すように、ダイヤモンド下地基板１
上に真空蒸着（又はスパッタリング）によってＷ層（厚
さ５馳）を全面形成し、フォトリングラフイーによって
所定配線パターン（線幅２０μ、線間隙１２５ｊａ）の
第１配線２を形成した。Next, as shown in FIG. 3A, the diamond base substrate 1
A W layer (5 mm thick) was formed on the entire surface by vacuum evaporation (or sputtering), and the first wiring 2 of a predetermined wiring pattern (line width 20 μm, line gap 125 ja) was formed by photophosphorography.
そして、再び直流プラズマジェッ）ＣＶＤ装置内にセッ
トして、第３Ｂ図に示すように、第１配線２を覆うよう
に下地基板１を含必全面に上述した直流プラズマジェッ
トＣＶＤ法によってダイヤモンド膜（厚さ５０廂）の第
１層間絶縁層６を形成した。このときのダイヤモンドの
製膜条件は、メタンガスを０．５β／ｍｉｎ 、そして
、基板・トーチ間距離を５０ｍｍとした他は同じにして
、下地基板のダイヤモンド結晶粒よりも細かいダイヤモ
ンド膜が得られた。そして、配線相互間のコンタクトを
とるためのバイアホールの位置にＹＡＧレーザを酸素含
有雰囲気下で照射してその部分を焼失させて、バイアホ
ール９を形成した。このときに、バイアホールの表面は
グラファイト化されて導電性を有するので、都合良い。Then, it is set in the DC plasma jet CVD apparatus again, and as shown in FIG. A first interlayer insulating layer 6 having a thickness of 50 cm was formed. The diamond film forming conditions at this time were the same except that methane gas was used at 0.5β/min and the distance between the substrate and the torch was 50 mm, and a diamond film that was finer than the diamond crystal grains on the base substrate was obtained. . Then, the via hole 9 was formed by irradiating a YAG laser in an oxygen-containing atmosphere to the position of the via hole for making contact between the wirings to burn out that part. At this time, the surface of the via hole is graphitized and has conductivity, which is convenient.
第３Ｃ図に示すように、上述したＷ配線形成、ダイヤモ
ンド層間絶縁層形成およびバイアホール形成を繰り返し
て、第２配線３、第２層間絶縁層７、第３配線４、第３
層間絶縁層８およびパイヤホール１０を形成した。As shown in FIG. 3C, by repeating the above-described W wiring formation, diamond interlayer insulation layer formation, and via hole formation, the second wiring 3, the second interlayer insulation layer 7, the third wiring 4, and the third
An interlayer insulating layer 8 and a pie hole 10 were formed.
次に、最上層の配線５として、第１図に示すように、Ｔ
１層（０，５ｒ厚）５Ａ、Ｐｔ層（１ｇｎ厚）５Ｂおよ
びＡｕ層（５ｒ厚）５Ｃの三層構造配線を公知の方法で
形成した。配線５として別な層構造でも形成できる。こ
のようにして本発明に係るダイヤモンド多層回路基板が
得られた。Next, as the uppermost layer wiring 5, as shown in FIG.
A three-layer wiring structure consisting of a single layer (0.5r thickness) 5A, a Pt layer (1gn thickness) 5B, and an Au layer (5r thickness) 5C was formed by a known method. The wiring 5 can also be formed with a different layer structure. In this way, a diamond multilayer circuit board according to the present invention was obtained.
作成した多層回路基板３１をマルチチップキャリアに応
用した例を第４図に示す。この場合には、ダイヤモンド
多層回路基板（４０Ｘ４０ Ｘ １．１５ｍｍ） ３１
の表面に半導体素子チップ（５×５ωｍサイズ）３２を
複数個（９個）ＡＨ−５ｕはんだでグイボンディングし
、チップ３２のパッドと回路基板３１の最上層配線とを
ワイヤー３３（ＡＩワイヤ〉で接続した。FIG. 4 shows an example in which the produced multilayer circuit board 31 is applied to a multichip carrier. In this case, a diamond multilayer circuit board (40X40X1.15mm) 31
A plurality (9 pieces) of semiconductor element chips (5 x 5 ωm size) 32 are bonded to the surface of the board using AH-5U solder, and the pads of the chip 32 and the top layer wiring of the circuit board 31 are connected using wires 33 (AI wires). Connected.
チップを保護するために、アルミ製キャップ３４が取付
けられ、そして接続のためにピン（Ｂｅ −Ｃｕ製、２
．５ ｍｍピッチで２列に、計１２８本）３５が付けら
れていた。An aluminum cap 34 is installed to protect the chip, and pins (made of Be-Cu, 2
．． A total of 128) 35 were attached in two rows at a 5 mm pitch.
得られたダイヤモンド多層回路基板の熱抵抗を調べたと
ころ、従来の同様な構成の多層回路基板と比較して、下
地基板にアルミナを、層間絶縁層に誘電体ガラスを用い
た基板の約１７８０と、また、下地基板にＳｉｃを、層
間絶縁層にシリカガラスを用いた基板の約１７６と小さ
く、極めて放熱効果の高いことがわかった。When we investigated the thermal resistance of the resulting diamond multilayer circuit board, we found that it was approximately 1,780 yen lower than that of a conventional multilayer circuit board with a similar configuration, and that of a board that uses alumina for the base substrate and dielectric glass for the interlayer insulating layer. Moreover, it was found that the substrate using SIC as the base substrate and silica glass as the interlayer insulating layer was as small as about 176 mm, and had an extremely high heat dissipation effect.
本発明によれば、多層回路基板はあらゆる物質中で最も
熱伝導率の高いダイヤモンドを使用しているので、回路
基板の熱抵抗が極めて小さく、放熱性に優れており、発
熱量の多い高速素子や、集積度の高い素子を実装する超
大型コンピュータ、スーパーコンピュータなどにおいて
使用するのに適し、高性能化、高信頼性化、保守の簡素
化に寄与する。According to the present invention, the multilayer circuit board uses diamond, which has the highest thermal conductivity of all materials, so the circuit board has extremely low thermal resistance and excellent heat dissipation, and is capable of handling high-speed elements that generate a large amount of heat. It is suitable for use in ultra-large computers, supercomputers, etc. that implement highly integrated elements, and contributes to higher performance, higher reliability, and simpler maintenance.
第１図は、本発明に係るダイヤモンド多層回路基板の部
分断面図であり、
第２図は、直流プラズマジェットＣＶＤ法のダイヤモン
ド気相合成装置の概略図であり、第３Ａ図、第３Ｂ図お
よび第３Ｃ図は、本発明に係るダイヤモンド多層回路基
板の製造工程を説明する該回路基板の部分断面図であり
、第４図は、本発明に係るダイヤモンド多層回路基板を
用いたマルチツブキャリアの概略断面図である。
１・・・ダイヤモンド下地基板、
２、３．４．５・・・配線、
６、７．８・・・ダイヤモンド層間絶縁層。
本発明のダイヤモンド多層回路基板の断面図第１図
６．７．８
ターイヤモンド層間杷祿Ｉ曽
第３Ａ図
第３Ｂ図
１３Ｃ図
第
図FIG. 1 is a partial sectional view of a diamond multilayer circuit board according to the present invention, FIG. 2 is a schematic diagram of a diamond vapor phase synthesis apparatus using the DC plasma jet CVD method, and FIGS. 3A, 3B, and FIG. 3C is a partial sectional view of a diamond multilayer circuit board according to the present invention, illustrating the manufacturing process of the circuit board, and FIG. 4 is a schematic diagram of a multitub carrier using the diamond multilayer circuit board according to the present invention. FIG. 1... Diamond base substrate, 2, 3.4.5... Wiring, 6, 7.8... Diamond interlayer insulating layer. Cross-sectional view of the diamond multilayer circuit board of the present invention Fig. 1 6.7.8 Fig. 3A Fig. 3B Fig. 13C Fig.
Claims (1)
板と、該下地基板の表面上に形成された多層配線と、こ
れら多層配線の間にあって気相合成法によって形成され
たダイヤモンドの層間絶縁層とからなることを特徴とす
るダイヤモンド多層回路基板。1. Consisting of a diamond base substrate produced by vapor phase synthesis, multilayer wiring formed on the surface of the base substrate, and a diamond interlayer insulating layer formed by vapor phase synthesis between these multilayer interconnects. A diamond multilayer circuit board featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63172594A JP2689986B2 (en) | 1988-07-13 | 1988-07-13 | Electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63172594A JP2689986B2 (en) | 1988-07-13 | 1988-07-13 | Electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0223639A true JPH0223639A (en) | 1990-01-25 |
| JP2689986B2 JP2689986B2 (en) | 1997-12-10 |
Family
ID=15944743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63172594A Expired - Lifetime JP2689986B2 (en) | 1988-07-13 | 1988-07-13 | Electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2689986B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5239746A (en) * | 1991-06-07 | 1993-08-31 | Norton Company | Method of fabricating electronic circuits |
| US5300810A (en) * | 1990-10-03 | 1994-04-05 | Norton Company | Electronic circuit and method with thermal management |
| WO1994020985A1 (en) * | 1993-03-11 | 1994-09-15 | Harris Corporation | Bonded wafer process incorporating diamond insulator |
| EP0632499A2 (en) * | 1993-05-28 | 1995-01-04 | Sumitomo Electric Industries, Ltd | Substrate for semiconductor device |
| EP1119045A3 (en) * | 2000-01-19 | 2007-11-07 | Japan Fine Ceramics Center | Diamond interconnection substrate and a manufacturing method therefor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102012206289B4 (en) | 2012-04-17 | 2016-02-25 | Forschungsverbund Berlin E.V. | Semiconductor device composite structure with heat dissipation structure and associated manufacturing method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58168144U (en) * | 1982-05-01 | 1983-11-09 | 株式会社テクニスコ | Heat dissipation board |
| JPS60128697A (en) * | 1983-12-15 | 1985-07-09 | 住友電気工業株式会社 | Multilayer circuit board for placing semiconductor element |
| JPS60208852A (en) * | 1984-04-03 | 1985-10-21 | Agency Of Ind Science & Technol | Semiconductor solid circuit element |
| JPS62224048A (en) * | 1986-03-26 | 1987-10-02 | Res Dev Corp Of Japan | Semiconductor subsrate made of diamond film |
| JPS62232193A (en) * | 1986-03-31 | 1987-10-12 | 鐘淵化学工業株式会社 | Multilayer high thermal conductivity insulating substrate |
-
1988
- 1988-07-13 JP JP63172594A patent/JP2689986B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58168144U (en) * | 1982-05-01 | 1983-11-09 | 株式会社テクニスコ | Heat dissipation board |
| JPS60128697A (en) * | 1983-12-15 | 1985-07-09 | 住友電気工業株式会社 | Multilayer circuit board for placing semiconductor element |
| JPS60208852A (en) * | 1984-04-03 | 1985-10-21 | Agency Of Ind Science & Technol | Semiconductor solid circuit element |
| JPS62224048A (en) * | 1986-03-26 | 1987-10-02 | Res Dev Corp Of Japan | Semiconductor subsrate made of diamond film |
| JPS62232193A (en) * | 1986-03-31 | 1987-10-12 | 鐘淵化学工業株式会社 | Multilayer high thermal conductivity insulating substrate |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5300810A (en) * | 1990-10-03 | 1994-04-05 | Norton Company | Electronic circuit and method with thermal management |
| US5239746A (en) * | 1991-06-07 | 1993-08-31 | Norton Company | Method of fabricating electronic circuits |
| US5371407A (en) * | 1991-06-07 | 1994-12-06 | Norton Company | Electronic circuit with diamond substrate and conductive vias |
| WO1994020985A1 (en) * | 1993-03-11 | 1994-09-15 | Harris Corporation | Bonded wafer process incorporating diamond insulator |
| EP0632499A2 (en) * | 1993-05-28 | 1995-01-04 | Sumitomo Electric Industries, Ltd | Substrate for semiconductor device |
| EP0632499A3 (en) * | 1993-05-28 | 1995-03-29 | Sumitomo Electric Industries | Substrate for semiconductor device. |
| US5682063A (en) * | 1993-05-28 | 1997-10-28 | Sumitomo Electric Industries, Ltd. | Substrate for semiconductor device |
| EP1119045A3 (en) * | 2000-01-19 | 2007-11-07 | Japan Fine Ceramics Center | Diamond interconnection substrate and a manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2689986B2 (en) | 1997-12-10 |
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