JPH0221829Y2 - - Google Patents
Info
- Publication number
- JPH0221829Y2 JPH0221829Y2 JP1983042050U JP4205083U JPH0221829Y2 JP H0221829 Y2 JPH0221829 Y2 JP H0221829Y2 JP 1983042050 U JP1983042050 U JP 1983042050U JP 4205083 U JP4205083 U JP 4205083U JP H0221829 Y2 JPH0221829 Y2 JP H0221829Y2
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting element
- light
- memory
- led
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000003491 array Methods 0.000 claims description 26
- 230000004044 response Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 12
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 6
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 102100028138 F-box/WD repeat-containing protein 7 Human genes 0.000 description 3
- 101001060231 Homo sapiens F-box/WD repeat-containing protein 7 Proteins 0.000 description 3
- 108091008695 photoreceptors Proteins 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Facsimile Heads (AREA)
- Facsimile Scanning Arrangements (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
【考案の詳細な説明】
（技術分野）
本考案は光プリンタ用発光素子（以下LEDと
いう）アレイの駆動回路に関する。[Detailed Description of the Invention] (Technical Field) The present invention relates to a drive circuit for a light emitting element (hereinafter referred to as LED) array for an optical printer.
（背景技術）
LEDを128個程度モノリシツクに集積したLED
アレイを10個程度用いることによつて光プリンタ
の光源とすることができる。このようなLEDア
レイは製造ロツトの相異等に原因して輝度特性が
異なりひとつのLEDアレイ内及びLEDアレイ間
において、同一特性のものを選択することも難し
い。第１図ａにひとつのLEDアレイ内の輝度バ
ラツキの代表特性を、第１図ｂにLEDアレイ間
の輝度バラツキの代表特性を示す。(Background technology) LED that is monolithically integrated with about 128 LEDs
By using about 10 arrays, it can be used as a light source for an optical printer. Such LED arrays have different brightness characteristics due to differences in manufacturing lots, and it is difficult to select LED arrays with the same characteristics within one LED array or between LED arrays. Figure 1a shows typical characteristics of brightness variations within one LED array, and Figure 1b shows typical characteristics of brightness variations between LED arrays.
第１図ａ，ｂより1LEDアレイ内で輝度バラツ
キが中心値±30％程度のものを10個程度組合せる
ことで、全体で中心値±60％程度に増加する。さ
らにこの中心値についてもプリントヘツド毎に異
なるという欠点を有する。このような欠点を除く
ためにLEDアレイ単位に発光時間を制御し、光
プリンタの感光体に与える光量をほぼ一定となる
ようなLED駆動方法が考えられる。 As can be seen from FIGS. 1a and 1b, by combining about 10 LED arrays with luminance variations of about ±30% of the center value within one LED array, the overall luminance variation increases to about ±60% of the center value. Furthermore, this center value also has the disadvantage that it differs from print head to print head. In order to eliminate this drawback, an LED driving method can be considered in which the light emission time is controlled for each LED array so that the amount of light applied to the photoreceptor of the optical printer is almost constant.
第２図および第３図に従来のLED駆動回路の
１実施例を示す。第２図において１1〜１10は、
夫々128個のLED素子からなるLEDアレイ、２1
〜２10は、夫々安定化抵抗ＲとトランジスタTra
の128対からなる電流増幅器、３1〜３10は、電流
供給端子、４は1280段のシフトレジスタである。 FIGS. 2 and 3 show one embodiment of a conventional LED driving circuit. In Figure 2, 1 1 to 1 10 are
LED array consisting of 128 LED elements each, 2 1
~2 10 are the stabilizing resistor R and transistor Tra, respectively.
3 1 to 3 10 are current supply terminals, and 4 is a 1280-stage shift register.
第２図での動作を第３図を用いて説明する。記
録開始信号Ｓ１の後、極く短いデータ書込時間Ｓ
２の間に画信号Ｑがシフトレジスタ４に記憶され
る。その後直ちに記録時間Ｓ３となり、この時間
Ｓ３内において、各LEDアレイに対応した時間
幅ｔ１〜ｔ１０をもつ電源電流Ｅ１〜Ｅ１０が電
流供給端子３1〜３10へ与えられる。従つて各
LEDアレイ１1〜１10のLEDは電源電流Ｅ１〜Ｅ
１０とシフトレジスタ４からの画信号Q1〜Q1280
に応じて発光し、電源電流Ｅ１〜Ｅ１０における
時間幅ｔ１〜ｔ１０を各LEDアレイ１1〜１10の
輝度と逆比例させることによつて光量を均一化し
ようとするものである。 The operation in FIG. 2 will be explained using FIG. 3. Extremely short data writing time S after recording start signal S1
2, the image signal Q is stored in the shift register 4. Immediately thereafter, recording time S3 begins, and within this time S3, power supply currents E1 to E10 having time widths t1 to t10 corresponding to the respective LED arrays are applied to current supply terminals 3 1 to 3 10 . Therefore each
LED array 1 1 to 1 10 LEDs have power supply current E1 to E
10 and the image signal Q 1 to Q 1280 from shift register 4
The purpose is to equalize the amount of light by making the time widths t1 to t10 of the power supply currents E1 to E10 inversely proportional to the brightness of each LED array 1 1 to 1 10 .
しかし、このような回路構成においては、以下
のような欠点があつた。 However, such a circuit configuration has the following drawbacks.
(1) LEDアレイ単位での光量の均一化はできて
も、LED素子単位での光量の均一化はできな
い。(1) Although it is possible to make the light amount uniform for each LED array, it is not possible to make the light amount uniform for each LED element.
(2) １プリントヘツド内で輝度バラツキが最大と
最小のLED素子を考えた場合、即ち輝度比で
最大／最小＝４倍の場合、発光時間比で４倍と
なる。これは定速回転している感光ドラム上
で、単位面積当りの露光量（即ち、発光輝度×
時間）に多大の差を生じてしまい輝度バラツキ
補正ができにくい。(2) When considering the LED elements with maximum and minimum brightness variations within one print head, that is, when the brightness ratio is maximum/minimum = 4 times, the light emission time ratio is 4 times. This is the amount of exposure per unit area (i.e., luminance x
This results in a large difference in time), making it difficult to correct luminance variations.
（考案の課題）
本考案の目的は、これらの欠点を除去するため
になされたものであり、夫々の各LEDアレイに
おける各LEDを所定光量で発光させること、特
に全てのLEDが光プリンタの感光体に与える露
光量をほぼ一定にさせることにある。(Problem for the invention) The purpose of the invention was to eliminate these drawbacks, and to make each LED in each LED array emit light with a predetermined amount of light. The goal is to keep the amount of light exposure given to the body almost constant.
本考案のLED駆動回路は、前記目的を達成す
るために、それぞれ複数の発光素子から成る複数
の発光素子アレイを時分割で駆動するための
LED駆動回路であつて、
前記発光素子アレイ内の各発光素子により表示
される画素データを格納する画素メモリと、前記
各発光素子アレイのうちの一つを循環的に順次選
択して駆動可能とすると共に、前記発光素子アレ
イ単位で発光時間若しくは供給電圧のいずれか一
方をその発光特性に対応して調整する第１の制御
手段と、前記第１の制御手段により順次選択され
る前記各発光素子アレイ内の各発光素子の発光時
の光量をそれぞれ所定の光量とする如く駆動する
第２の制御手段とを備え、前記第２の制御手段は
前記各発光素子の光量をそれぞれ所定の光量にす
るように、前記各発光素子の発光時間を定める発
光時間調整用データを前記各画素データに対応し
て記憶する発光時間調整用メモリと、前記画素メ
モリからの前記各発光素子アレイの内の一つに対
応した前記画素データの読み出しに対応して前記
画素データ対応の前記発光時間調整用データを読
み出すように、前記画素メモリ及び前記発光時間
調整用メモリを制御する手段と、前記画素メモリ
から読み出された前記画素データを、前記発光時
間調整用メモリから読み出された前記発光時間調
整用データに従つた所定期間だけ前記発光素子ア
レイ内の各発光素子を発光させるように、前記発
光素子アレイ内の各発光素子を駆動する手段とを
有することを特徴とするものである。以下詳細に
説明する。 In order to achieve the above object, the LED driving circuit of the present invention is designed to time-divisionally drive multiple light emitting element arrays each consisting of a plurality of light emitting elements.
The LED driving circuit includes a pixel memory for storing pixel data displayed by each light emitting element in the light emitting element array, and a pixel memory capable of cyclically sequentially selecting and driving one of the light emitting element arrays. and a first control means for adjusting either the light emitting time or the supply voltage for each of the light emitting element arrays in accordance with the light emitting characteristics thereof, and each of the light emitting elements sequentially selected by the first control means. and a second control means for driving each light emitting element in the array to have a predetermined light amount when emitting light, the second control means driving each light emitting element to have a predetermined light amount. a light emitting time adjustment memory that stores light emitting time adjustment data that determines the light emitting time of each of the light emitting elements in correspondence with each of the pixel data; and one of the light emitting element arrays from the pixel memory. means for controlling the pixel memory and the light emission time adjustment memory so as to read out the light emission time adjustment data corresponding to the pixel data in response to reading of the pixel data corresponding to the pixel data; The pixel data is stored in the light emitting element array so that each light emitting element in the light emitting element array emits light for a predetermined period according to the light emitting time adjustment data read from the light emitting time adjustment memory. The invention is characterized in that it has a means for driving each light emitting element. This will be explained in detail below.
（考案の構成および作用）
第４図は、本考案の１実施例を示す結線図、第
５図はその各部の信号図である。第４図において
１1〜１10は夫々128個のLEDからなるLEDアレ
イ、２11は安定化抵抗ＲとトランジスタTraの
128対からなる電流増幅器、３11はその電流供給
端子、５は一致回路、６はカウンタ、７はシリア
ル−パラレル変換器、８は画素メモリ、９はカウ
ンタ、１０はLEDアレイ１1〜１10の各LEDの発
光時間調整量を記憶するメモリ、１１1〜１１10
は可変電源、１２1〜１２10は夫々、電圧供給端
子、１３1〜１３10は、前記可変電源１１1〜１１
10の駆動のON又はOFFをセレクトするスイツチ
である。ここで、電流増幅器２11の各出力端は、
全LEDアレイ１1〜１10において互いに対応する
LEDの一方の電極に共通接続される。また、各
LEDアレイ１1〜１10において全LEDの他方の電
極は、それぞれ対応して設けられている電圧供給
端子１２1〜１２10に共通接続される。更に、電
圧供給端子１２1〜１２10はそれぞれ可変電源１
１1〜１１10に接続され、また可変電源１１1〜１
１10はそれぞれスイツチ１３1〜１３10に接続され
る。(Structure and operation of the invention) FIG. 4 is a wiring diagram showing one embodiment of the invention, and FIG. 5 is a signal diagram of each part thereof. In Figure 4, 11 to 110 are LED arrays each consisting of 128 LEDs, and 211 is a stabilizing resistor R and a transistor Tra.
A current amplifier consisting of 128 pairs, 3 11 is its current supply terminal, 5 is a matching circuit, 6 is a counter, 7 is a serial-parallel converter, 8 is a pixel memory, 9 is a counter, 10 is an LED array 1 1 to 1 10 Memory for storing the light emission time adjustment amount of each LED, 11 1 to 11 10
are variable power supplies, 12 1 to 12 10 are voltage supply terminals, and 13 1 to 13 10 are variable power supplies 11 1 to 11.
This is a switch that selects ON or OFF of 10 drives. Here, each output terminal of the current amplifier 2 11 is
Corresponding to each other in all LED arrays 1 1 to 1 10
Commonly connected to one electrode of the LED. Also, each
The other electrodes of all the LEDs in the LED arrays 1 1 to 1 10 are commonly connected to voltage supply terminals 12 1 to 12 10 provided correspondingly, respectively. Furthermore, the voltage supply terminals 12 1 to 12 10 are each connected to the variable power supply 1
1 1 to 11 10 , and the variable power supply 11 1 to 1
1 10 are connected to switches 13 1 to 13 10 , respectively.
例えば、LEDアレイ１1において各LEDの一方
の電極は電流増幅器２11のそれぞれ対応する出力
端に接続され、また全LEDの他方の電極は電圧
供給端子１２1を介して共通に接続される。 For example, in the LED array 1 1 , one electrode of each LED is connected to the corresponding output terminal of the current amplifier 2 11 , and the other electrodes of all the LEDs are commonly connected via the voltage supply terminal 12 1 .
第４図での動作を第５図を参照して説明する。
記録開始信号Ｓ１の後、極く短いデータ書込時間
Ｓ２の間に画信号Ｑがシリアル−パラレル変換器
７を介してカウンタ６の出力６ａをアドレスとし
た画素メモリ８に記憶される。その後直ちに記録
時間Ｓ３となり、この時間Ｓ３内においてスイツ
チ１３1〜１３10に選択信号SEL１〜SEL１０が
時分割駆動のために順次与えられ、その結果、電
圧調整回路１１1〜１１10が順次駆動状態となり、
その結果電圧供給端子１２1〜１２10に順次電圧
が出力される。カウンタ９はクロツク信号Ｓ５を
カウントしカウンタ６の10倍程度の速度で動作す
る。カウンタ６はクロツクＳ４をカウントし、ク
ロツクＳ４は前記SEL１〜１０信号が変化する毎
に出力される。 The operation in FIG. 4 will be explained with reference to FIG.
After the recording start signal S1, the image signal Q is stored in the pixel memory 8 using the output 6a of the counter 6 as an address via the serial-parallel converter 7 during an extremely short data writing time S2. Immediately thereafter, the recording time S3 begins, and during this time S3, the selection signals SEL1 to SEL10 are sequentially applied to the switches 131 to 1310 for time-division driving, and as a result, the voltage adjustment circuits 111 to 1110 are sequentially brought into the driving state. Then,
As a result, voltages are sequentially output to the voltage supply terminals 12 1 to 12 10 . Counter 9 counts clock signal S5 and operates at about 10 times the speed of counter 6. The counter 6 counts the clock S4, and the clock S4 is output every time the SEL1-10 signals change.
SEL１のタイミングにおいて、画素メモリ８か
らカウンタ６の出力６ａをアドレスとして画素デ
ータが128ビツト分データ出力端子８ａに出力さ
れる。SEL１のタイミングは更にタイミングT1
〜T10に分割され、夫々のタイミングTnにおいて
発光時間調整用メモリ１０からカウンタ９の出力
９ａをアドレスとして調整データが128ビツト分
メモリ１０の出力端子Ｗに出力され、当該データ
と前記画素メモリ８の出力８ａとが比較回路５に
おいて128ビツト分夫々論理積がとられ、その結
果前記電流増幅器２11を駆動し、LEDアレイ１1
に電流が通電される。 At the timing of SEL1, 128 bits of pixel data is output from the pixel memory 8 to the data output terminal 8a using the output 6a of the counter 6 as an address. The timing of SEL1 is further timing T 1
-T10 , and at each timing Tn, 128 bits of adjustment data is output from the light emission time adjustment memory 10 to the output terminal W of the memory 10 using the output 9a of the counter 9 as an address, and the data and the pixel memory 8 are The outputs 8a of 128 bits are logically ANDed in the comparison circuit 5, and as a result, the current amplifier 211 is driven, and the LED array 11 is
A current is applied to the
発光時間調整用メモリ１０にはあらかじめ
LEDアレイ１1の各LEDの発光輝度と逆比例する
如く発光時間ｔ１〜ｔ１２８を設定しておく必要
がある。 In the memory 10 for adjusting the light emitting time,
It is necessary to set the light emission times t1 to t128 so as to be inversely proportional to the light emission brightness of each LED of the LED array 11 .
SEL２〜SEL１０の夫々のタイミングにおいて
も前記同様のデータ処理が行われる。可変電源１
１1〜１１10を夫々独立に設定することで、LED
アレイ１1〜１10に通電される電流値を、LEDア
レイ単位に設定することができる。即ち、LED
アレイ単位間での輝度中心値のバラツキを前記可
変電源１１1〜１１10を独立に設定することで抑
えられる。さらに、夫々のLEDアレイ内での輝
度バラツキは前記発光時間調整用メモリ１０を使
用して順次最適発光時間ｔ１〜ｔ１２８０を読み
出すことにより抑えることができる。 Data processing similar to that described above is also performed at each timing of SEL2 to SEL10. Variable power supply 1
By setting 1 1 to 11 10 independently, the LED
The current value applied to the arrays 1 1 to 1 10 can be set for each LED array. That is, LED
Variation in the central brightness value between array units can be suppressed by independently setting the variable power supplies 11 1 to 11 10 . Furthermore, variations in brightness within each LED array can be suppressed by sequentially reading out the optimum light emitting times t1 to t1280 using the light emitting time adjustment memory 10.
以上説明したように、第１の実施例では、夫々
のLEDアレイ内での輝度バラツキは、発光時間
調整用メモリを使用することで吸収され、LED
アレイ間での輝度バラツキはLEDアレイ毎に駆
動電流を変化させることで吸収することができ
る。従つて、輝度バラツキのない複数のLEDア
レイを選択するのと同一の効果を期待することが
できる。 As explained above, in the first embodiment, the luminance variation within each LED array is absorbed by using the memory for adjusting the light emission time, and the luminance variation within each LED array is absorbed.
Luminance variations between arrays can be absorbed by changing the drive current for each LED array. Therefore, the same effect as selecting a plurality of LED arrays with no variation in brightness can be expected.
第１の実施例は、LEDアレイ間での輝度バラ
ツキを通電電流量を変化させることで吸収する回
路例を説明したが、第６図に示す如く前記LED
アレイ毎の可変電源部を除去あるいはすべて同一
の値とし、即ち通電電流量を各LEDアレイ共通
とし当該通電電流量の通電時間を、LEDアレイ
毎に独立に可変する構成とすれば、LEDアレイ
間の輝度バラツキを吸収することと同等の効果が
生ずる。 In the first embodiment, an example of a circuit was explained in which the variation in brightness between LED arrays is absorbed by changing the amount of current applied, but as shown in FIG.
If the variable power supply section for each array is removed or all the values are set to the same value, that is, the current amount is common to each LED array, and the energization time of the current amount is varied independently for each LED array, the power supply between the LED arrays can be changed. This produces the same effect as absorbing luminance variations.
第６図は、本考案の第２の実施例を示す結線
図、第７図は、その信号説明図である。第６図に
おいて１1〜１10は夫々128個のLEDからなるLED
アレイ、２11は電流増幅器、３11はその電流供給
端子、５は一致回路、６はカウンタ、７はシリア
ル−パラレル変換器、８は画素メモリ、９はカウ
ンタ、１０はLEDアレイ１1〜１10の各LEDの発
光時間調整量を記憶するメモリ、１２1〜１２10
は夫々電圧供給端子、１３1〜１３10はANDゲー
トとTrSELの対からなるスイツチ、１４はパル
ス発生器である。 FIG. 6 is a wiring diagram showing a second embodiment of the present invention, and FIG. 7 is a signal explanation diagram thereof. In Figure 6, 1 1 to 1 10 are LEDs each consisting of 128 LEDs.
array, 2 11 is a current amplifier, 3 11 is its current supply terminal, 5 is a matching circuit, 6 is a counter, 7 is a serial-parallel converter, 8 is a pixel memory, 9 is a counter, 10 is an LED array 1 1 to 1 Memory for storing the light emission time adjustment amount of each of the 10 LEDs, 12 1 to 12 10
are voltage supply terminals, 13 1 to 13 10 are switches consisting of a pair of AND gates and TrSEL, and 14 is a pulse generator.
Ｓ６1〜Ｓ６10は、くり返し周期が同一で、パ
ルスデユーテイ比即ち“１”，“０”の時間比が
夫々異なつているパルス列を意味する。 S6 1 to S6 10 refer to pulse trains having the same repetition period and different pulse duty ratios, that is, the time ratios of "1" and "0".
発光開始時間Ｓ３内において、SEL１〜SEL１
０信号は、巡環的に“１”状態となる。１３1〜
１３10では当該SEL１〜SEL１０信号と前記Ｓ６
１〜Ｓ６10信号の夫々の論理積がとられ、その結
果に応じてTrSELをON、OFFしLEDアレイ１1
〜１10のうち該当するLEDアレイを通電可能な状
態とする。ここで前記パルス発生器１４のパルス
デユーテイ比は、LEDアレイの通電時間の割合
いを示し、当該LEDアレイの輝度中心値に逆比
例するように設定されるものであり、例えばマル
チバイブレータ等の回路を使用することで実現可
能である。 Within the light emission start time S3, SEL1 to SEL1
The 0 signal becomes a "1" state cyclically. 13 1 ~
13 At 10 , the SEL1 to SEL10 signals and the S6
1 to S6 The logical product of each of the 10 signals is taken, and depending on the result, the TrSEL is turned on or off and the LED array 1 1
~1 The corresponding LED array out of 10 is enabled to be energized. Here, the pulse duty ratio of the pulse generator 14 indicates the proportion of the energization time of the LED array, and is set to be inversely proportional to the center brightness value of the LED array. This can be achieved by using
以上説明したことからわかるように、LEDア
レイ毎に、輝度中心値に逆比例するパルス発生器
を備えることでLEDアレイ毎に通電時間が設定
され、従つてLEDアレイ間の露光量の中心値を
均一な値に圧縮することができる。更に、前述の
第１の実施例と同様にして、それぞれLEDアレ
イ内での輝度のバラツキは、発光時間調整用のメ
モリ１０より順次読み出される最適発光時間ｔ１
〜ｔ１２８を用いて各LEDの発光時間を制御す
ることにより減少させることができる。 As can be seen from the above explanation, by providing each LED array with a pulse generator that is inversely proportional to the center brightness value, the energization time can be set for each LED array, and therefore the center value of the exposure amount between LED arrays can be set. Can be compressed to a uniform value. Furthermore, in the same way as in the first embodiment described above, the variation in brightness within each LED array is determined by the optimum light emission time t1 which is sequentially read out from the memory 10 for light emission time adjustment.
It can be reduced by controlling the light emission time of each LED using ~t128.
（考案の効果）
本考案は、通電電流制御回路と発光時間調整用
メモリを備えているので、発光素子の輝度特性を
揃える場合と同一の効果が得られる利点があり、
光プリンタの駆動回路に応用した場合には、感光
体に与える露光量をほぼ均一化できる利点があ
り、高印字品質の画像が得られる。(Effects of the invention) Since the present invention is equipped with a current control circuit and a memory for adjusting light emission time, it has the advantage that the same effect as when the luminance characteristics of light emitting elements are made uniform can be obtained.
When applied to the drive circuit of an optical printer, there is an advantage that the amount of exposure applied to the photoreceptor can be made almost uniform, and images with high print quality can be obtained.
第１図ａは、LEDアレイ内での各LEDの輝度
バラツキの説明図、第１図ｂは複数のLEDアレ
イを組合せた時の輝度バラツキの説明図、第２図
は従来の技術による回路結線図、第３図は第２図
の各部信号の説明図、第４図は本考案の第１実施
例の回路結線図、第５図は第４図の各部信号説明
図、第６図は本考案の別の実施例の回路図、第７
図は第６図の信号説明図である。
１1〜１10……LEDアレイ、２1〜２11……電流
増幅器、３1〜３11……電流供給端子、４……シ
フトレジスタ、５……比較回路、６……カウン
タ、７……シリアル−パラレル変換器、８……画
素メモリ、９……カウンタ、１０……発光時間調
整用メモリ、１１1〜１１10……可変電圧源、１
２1〜１２10……電圧供給端子、１３1〜１３10…
…スイツチ、１４……パルス発生器。
Figure 1a is an explanatory diagram of the brightness variations of each LED within an LED array, Figure 1b is an explanatory diagram of the brightness variations when multiple LED arrays are combined, and Figure 2 is a circuit connection diagram using conventional technology. Figure 3 is an explanatory diagram of the signals of each part in Figure 2, Figure 4 is a circuit connection diagram of the first embodiment of the present invention, Figure 5 is an explanatory diagram of the signals of each part of Figure 4, and Figure 6 is an illustration of the signals of each part of the present invention. Circuit diagram of another embodiment of the invention, No. 7
The figure is an explanatory diagram of the signals in FIG. 6. 1 1 to 1 10 ... LED array, 2 1 to 2 11 ... current amplifier, 3 1 to 3 11 ... current supply terminal, 4 ... shift register, 5 ... comparison circuit, 6 ... counter, 7 ... ... Serial-parallel converter, 8 ... Pixel memory, 9 ... Counter, 10 ... Memory for light emission time adjustment, 11 1 to 11 10 ... Variable voltage source, 1
2 1 ~ 12 10 ... Voltage supply terminal, 13 1 ~ 13 10 ...
...Switch, 14...Pulse generator.
Claims (1)
子アレイを時分割で駆動するためのLED駆動回
路において、 前記発光素子アレイ内の各発光素子により表示
される画素データを格納する画素メモリと、 前記各発光素子アレイのうちの一つを循環的に
順次選択して駆動可能とすると共に、前記発光素
子アレイ単位で発光時間若しくは供給電圧のいず
れか一方をその発光特性に対応して調整する第１
の制御手段と、 前記第１の制御手段により順次選択される前記
各発光素子アレイ内の各発光素子の発光時の光量
をそれぞれ所定の光量とする如く駆動する第２の
制御手段とを備え、 前記第２の制御手段は 前記各発光素子の光量をそれぞれ所定の光量に
するように、前記各発光素子の発光時間を定める
発光時間調整用データを前記各画素データに対応
して記憶する発光時間調整用メモリと、 前記画素メモリからの前記各発光素子アレイの
内の一つに対応した前記画素データの読み出しに
対応して前記画素データ対応の前記発光時間調整
用データを読み出すように、前記画素メモリ及び
前記発光時間調整用メモリを制御する手段と、 前記画素メモリから読み出された前記画素デー
タを、前記発光時間調整用メモリから読み出され
た前記発光時間調整用データに従つた所定期間だ
け前記発光素子アレイ内の各発光素子を発光させ
るように、前記発光素子アレイ内の各発光素子を
駆動する手段と を有することを特徴とするLED駆動回路。[Claims for Utility Model Registration] In an LED drive circuit for time-divisionally driving a plurality of light emitting element arrays each comprising a plurality of light emitting elements, pixel data displayed by each light emitting element in the light emitting element array is stored. a pixel memory capable of cyclically and sequentially selecting one of the light emitting element arrays and driving the light emitting element array, and adjusting either the light emitting time or the supply voltage for each of the light emitting element arrays to correspond to its light emitting characteristics. The first step is to adjust
and a second control means for driving each light emitting element in each of the light emitting element arrays sequentially selected by the first control means so as to set the light amount when emitting light to a predetermined light amount, The second control means stores light emitting time adjustment data that determines the light emitting time of each of the light emitting elements in correspondence with each of the pixel data so that the light amount of each of the light emitting elements becomes a predetermined light amount. an adjustment memory, the pixel so as to read out the light emission time adjustment data corresponding to the pixel data in response to reading out the pixel data corresponding to one of the light emitting element arrays from the pixel memory; means for controlling a memory and the light emission time adjustment memory; and a means for controlling the pixel data read from the pixel memory for a predetermined period according to the light emission time adjustment data read from the light emission time adjustment memory. An LED driving circuit comprising means for driving each light emitting element in the light emitting element array so that each light emitting element in the light emitting element array emits light.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983042050U JPS59149300U (en) | 1983-03-25 | 1983-03-25 | LED drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983042050U JPS59149300U (en) | 1983-03-25 | 1983-03-25 | LED drive circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59149300U JPS59149300U (en) | 1984-10-05 |
| JPH0221829Y2 true JPH0221829Y2 (en) | 1990-06-12 |
Family
ID=30172610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983042050U Granted JPS59149300U (en) | 1983-03-25 | 1983-03-25 | LED drive circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59149300U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52129444A (en) * | 1976-04-22 | 1977-10-29 | Nippon Signal Co Ltd:The | Heat generating element for heating apparatus |
| JPS5632468B2 (en) * | 1978-09-04 | 1981-07-28 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6310293Y2 (en) * | 1979-08-21 | 1988-03-28 |
-
1983
- 1983-03-25 JP JP1983042050U patent/JPS59149300U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52129444A (en) * | 1976-04-22 | 1977-10-29 | Nippon Signal Co Ltd:The | Heat generating element for heating apparatus |
| JPS5632468B2 (en) * | 1978-09-04 | 1981-07-28 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59149300U (en) | 1984-10-05 |
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