JPH02207537A - Manufacture of thin film semiconductor device - Google Patents
Manufacture of thin film semiconductor deviceInfo
- Publication number
- JPH02207537A JPH02207537A JP2745489A JP2745489A JPH02207537A JP H02207537 A JPH02207537 A JP H02207537A JP 2745489 A JP2745489 A JP 2745489A JP 2745489 A JP2745489 A JP 2745489A JP H02207537 A JPH02207537 A JP H02207537A
- Authority
- JP
- Japan
- Prior art keywords
- silicon film
- film
- amorphous silicon
- semiconductor device
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 16
- 239000010703 silicon Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000001257 hydrogen Substances 0.000 claims abstract description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 239000011248 coating agent Substances 0.000 claims abstract 2
- 238000000576 coating method Methods 0.000 claims abstract 2
- 238000000151 deposition Methods 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 80
- 238000010438 heat treatment Methods 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 9
- 239000007789 gas Substances 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 4
- 150000001793 charged compounds Chemical class 0.000 claims description 4
- 230000004048 modification Effects 0.000 claims description 3
- 238000012986 modification Methods 0.000 claims description 3
- 238000000354 decomposition reaction Methods 0.000 claims description 2
- 238000001704 evaporation Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 22
- 239000011521 glass Substances 0.000 abstract description 10
- 238000002425 crystallisation Methods 0.000 abstract description 3
- 230000008025 crystallization Effects 0.000 abstract description 3
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 abstract 1
- 230000001131 transforming effect Effects 0.000 abstract 1
- 238000010899 nucleation Methods 0.000 description 8
- 230000006911 nucleation Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000007943 implant Substances 0.000 description 5
- 238000002441 X-ray diffraction Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- -1 silicon molecular ions Chemical class 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Landscapes
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜半導体装置およびその製造方法に係り、特
にアクティブマトリクス方式のデイスプレィに好適な薄
膜半導体の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film semiconductor device and a method for manufacturing the same, and more particularly to a method for manufacturing a thin film semiconductor suitable for an active matrix display.
アクティブマトリクス方式液晶デイスプレィの大画面化
、高画質化を図るために、薄膜半導体装置である薄膜ト
ランジスタ（工ｈｉｓ Ｆｉｌｎ＋Ｔｒａｎｓｉｓｔｏ
ｒ 、略してＴＰＴ）の材料としてキャリア移動度の大
きい多結晶シリコン膜が用いられている。In order to achieve larger screens and higher image quality for active matrix liquid crystal displays, thin film transistors, which are thin film semiconductor devices, have been developed.
A polycrystalline silicon film with high carrier mobility is used as a material for the material (TPT for short).
キャリア移動度は多結晶シリコン膜の結晶性に強く依存
していることから、特性の良いＴＦＴ＆得るには、結晶
粒をできるだけ大きくしてキャリア移動度を大きくする
ことが望ましい。Since carrier mobility strongly depends on the crystallinity of the polycrystalline silicon film, in order to obtain a TFT with good characteristics, it is desirable to increase carrier mobility by making crystal grains as large as possible.
従来、絶縁基板上に膜を成長させる場合、成長初期には
核が基板上にランダムに形成されるため、最初は結晶粒
は小さく、膜厚の増大につれて結晶粒は大きくなり、結
晶性の優れた多結晶シリコン膜になる。従って結晶粒径
を大きくするには膜厚を厚くしなければならない問題が
あった。この問題を解決するため、特開昭６１−８５８
１５号記載のように、絶縁基板上に生成した核を熱処理
により成長させ、これを種結晶として多結晶シリコン膜
を形成する方法が試みられた。この方法は、結晶性向上
に効果は認められるが、基板上にランダムに生成した核
は熱処理をしてもまだ十分大きくならないため、核の数
は減少せず、結局結晶性や結晶粒径も十分大きくなると
は言えない。Conventionally, when growing a film on an insulating substrate, nuclei are formed randomly on the substrate in the initial stage of growth, so the crystal grains are small at first, and as the film thickness increases, the crystal grains become larger, resulting in excellent crystallinity. It becomes a polycrystalline silicon film. Therefore, there was a problem in that the film thickness had to be increased in order to increase the crystal grain size. In order to solve this problem, Japanese Patent Application Laid-Open No. 61-858
As described in No. 15, a method has been attempted in which nuclei generated on an insulating substrate are grown by heat treatment and a polycrystalline silicon film is formed using the nuclei as seed crystals. Although this method is effective in improving crystallinity, the nuclei generated randomly on the substrate do not become large enough even after heat treatment, so the number of nuclei does not decrease, and the crystallinity and grain size eventually decrease. I can't say it's going to be big enough.
上記従来技術、すなわち絶縁基板上に多結晶シリコン膜
を形成する方法においては、絶縁基板とシリコン膜の界
面での核生成を抑制することが重要である。しかし、上
記従来技術では核の数についての配慮が十分でなく、し
たがって、多結晶シリコン膜の結晶性も十分でない、す
なわち、絶縁基板上に多結晶シリコン膜を形成する場合
、絶縁基板とシリコン膜の熱膨張係数や原子間距離の相
違、あるいは絶縁基板からの不純物導入などにより、基
板界面には歪が集中し、結晶核が生成しゃすい状態にな
っている。そのため、核はランダムに多数生成し、そこ
から結晶粒が成長するため、結晶粒は十分大きくならず
、結晶性は上がらない。In the conventional technique described above, that is, in the method of forming a polycrystalline silicon film on an insulating substrate, it is important to suppress nucleation at the interface between the insulating substrate and the silicon film. However, in the above-mentioned conventional technology, sufficient consideration is not given to the number of nuclei, and therefore the crystallinity of the polycrystalline silicon film is also insufficient. In other words, when forming a polycrystalline silicon film on an insulating substrate, Due to differences in thermal expansion coefficients and interatomic distances, or the introduction of impurities from the insulating substrate, strain is concentrated at the substrate interface, making it easy for crystal nuclei to form. Therefore, many nuclei are randomly generated and crystal grains grow from them, so the crystal grains do not become sufficiently large and the crystallinity does not improve.
このことから、結晶性を上げるには、核発生を結晶化に
必要な最少限に抑制することが重要である。From this, in order to improve crystallinity, it is important to suppress nucleation to the minimum level necessary for crystallization.
本発明の目的は、非晶質シリコン膜とその下地との界面
での結晶の核生成を抑制することにより結晶粒が大きく
、かつキャリア移動度が大きくなるような多結晶シリコ
ン膜を形成できる薄膜半導体装置の製造方法を提供する
ことにある。An object of the present invention is to provide a thin film that can form a polycrystalline silicon film with large crystal grains and high carrier mobility by suppressing crystal nucleation at the interface between an amorphous silicon film and its base. An object of the present invention is to provide a method for manufacturing a semiconductor device.
上記目的は、チャネル領域にあたるシリコン膜の下地部
分を、シリコンと水素で被覆した状態にしておきこの下
地の上に、非晶質シリコン膜を堆積し、熱処理して、非
晶質シリコン膜を多結晶シリコン膜に変換させることに
より達成される。下地のシリコンと水素で被覆した状態
は、水素化アモルファスシリコン膜（以下略してａ−８
ｉ：Ｈ）を形成するか、絶縁基板表面に水素とシリコン
の分子イオンを注入して、水素とシリコンの化合物層を
作り絶縁基板表面をａ−８ｉ：Ｈの表面と同質の状態に
改質して形成する。The above purpose is to coat the base of the silicon film, which corresponds to the channel region, with silicon and hydrogen, deposit an amorphous silicon film on top of this base, and heat-treat it to form a multilayer amorphous silicon film. This is achieved by converting it into a crystalline silicon film. The state in which the underlying silicon and hydrogen are coated is a hydrogenated amorphous silicon film (hereinafter abbreviated as a-8).
i:H) or implant hydrogen and silicon molecular ions onto the surface of the insulating substrate to create a hydrogen and silicon compound layer and modify the surface of the insulating substrate to be the same as the surface of a-8i:H. and form it.
以下、非晶質シリコン膜の結晶成長過程と、下地膜の影
響について述べる。The crystal growth process of an amorphous silicon film and the influence of the underlying film will be described below.
第２図は絶縁基板上に減圧ＣＶＤ法により形成した非晶
質シリコン膜の結晶成長過程を透過型電子顕微鏡にて１
′！察した様子をモデル化した図である。第２図（ａ）
は絶縁基板に非晶質シリコン膜５０を堆積した状態であ
る。このときは膜中に結晶粒はみられない。この膜をＮ
２中６００℃で熱処理すると、第２図（ｂ）のように基
板１と膜５０の界面に結晶粒５１が形成される。膜中や
膜表面にはみられない。よって、結晶核は基板との界面
にのみ生成することがわかる。さらに熱処理を続けると
、第２図（ｃ）のように、結晶粒５１を核として周囲の
アモルファス成分を結晶成分に変換しながら結晶粒５２
が成長する。そして第２図（ｄ）のように隣接する結晶
粒がぶつかった時点で横方向の成長は終わり膜厚方向に
成長する。Figure 2 shows the crystal growth process of an amorphous silicon film formed on an insulating substrate by low pressure CVD using a transmission electron microscope.
′! This figure is a model of what was observed. Figure 2(a)
1 shows a state in which an amorphous silicon film 50 is deposited on an insulating substrate. At this time, no crystal grains are observed in the film. This film is N
2, crystal grains 51 are formed at the interface between the substrate 1 and the film 50, as shown in FIG. 2(b). It is not seen in the membrane or on the membrane surface. Therefore, it can be seen that crystal nuclei are generated only at the interface with the substrate. When the heat treatment is further continued, as shown in FIG. 2(c), the crystal grains 51 are used as cores and the surrounding amorphous components are converted to crystalline components, while the crystal grains 52
grows. Then, as shown in FIG. 2(d), when adjacent crystal grains collide, the lateral growth ends and the film grows in the thickness direction.
このような結晶成長過程をとるため、結晶成長は核の生
成密度に強く依存する。よって核の発生を結晶化に最適
な程度まで抑制することにより、結晶粒をより大きくす
ることが可能となり、結晶性のすぐれた多結晶シリコン
膜を形成できる。そこで、絶縁基板と非晶質シリコン膜
の界面にａ−９ｉ ：Ｈを介在させることにより界面の
状態を変えて減圧ＣＶＤ膜形成し、熱処理後の結晶性を
比較した。Since such a crystal growth process is adopted, crystal growth strongly depends on the density of nucleation. Therefore, by suppressing the generation of nuclei to the optimum level for crystallization, it is possible to make the crystal grains larger, and a polycrystalline silicon film with excellent crystallinity can be formed. Therefore, a low pressure CVD film was formed by interposing a-9i:H at the interface between the insulating substrate and the amorphous silicon film to change the state of the interface, and the crystallinity after heat treatment was compared.
第３図はａ−８ｉ：Ｈ下地の有無での減圧ＣＶＤ多結晶
シリコン膜のＸ線回折スペクトルを示したものである。FIG. 3 shows the X-ray diffraction spectra of low pressure CVD polycrystalline silicon films with and without an a-8i:H underlayer.
多結晶シリコン膜のスペクトルには（１１１）（２２０
）（３１１）の３つの方位を持った回折線が観測された
。この回折線のピーク高さ（Ｘ線回折強度）が膜中の結
晶成分の量を表わしており、強度が強い程、結晶性の優
れた膜である。（１１１）の回折ピークに注目すると、
Ｘ線回折強度は下地膜を形成した場合、形成しない従来
の場合と比べて約１．５倍大きくなっており、結晶性が
良くなっていることがわかる。また、Ｘ線回折ピークの
線幅をもとにシェラ−（Ｓｃｈｅｒｒｅｒ）の式から平
均の結晶子の大きさを算出したところ、下地膜を形成し
た場合、３００Å以上となり、従来に比べて約１．５倍
大きくなっている。The spectrum of polycrystalline silicon film has (111) (220
) (311) diffraction lines with three orientations were observed. The peak height of this diffraction line (X-ray diffraction intensity) represents the amount of crystalline components in the film, and the stronger the intensity, the better the crystallinity of the film. Focusing on the diffraction peak of (111),
When the base film is formed, the X-ray diffraction intensity is about 1.5 times higher than in the conventional case where no base film is formed, indicating that the crystallinity is improved. In addition, when the average crystallite size was calculated from the Scherrer equation based on the line width of the X-ray diffraction peak, it was found to be over 300 Å when a base film was formed, which was about 1 .5 times larger.
以上のことから、非晶質シリコン膜と絶縁基板の間にａ
−Ｓｉ：Ｈを介在させることにより、結晶子の大きさが
３００Å以上と大きく、かつ結晶性のよい膜が得られる
ことがわかる。From the above, it is clear that a
It can be seen that by interposing -Si:H, a film with large crystallite size of 300 Å or more and good crystallinity can be obtained.
上記方法で結晶性が向上するのは次の理由による。絶縁
基板上にａ−３ｉ：Ｈ膜を形成、あるいはＨとＳｉの分
子イオン注入にする絶縁基板の表面改質することにより
、この下地とその上に形成する非晶質シリコン膜との界
面で起こる結晶核の生成が抑制されるためである。すな
わち、結晶核の生成は、界面での熱膨張係数の相違や格
子の歪などに起因するため、絶縁基板や酸化膜とシリコ
ン膜との界面では起こりやすく、５ｉ−５ｉの界面では
おこりにくい、よって界面での核生成を抑制するには界
面に酸化膜を介在させずに５ｉ−３ｉの界面を作ること
が必要となる。すなわち、酸化されにくく、かつシリコ
ン膜との熱膨張係数差の小さい膜ａ−８ｉ：Ｈを非晶質
シリコン膜と絶縁基板の間に介在させれば核発生を抑え
ることができる。ａ−８ｉ：Ｈと単結晶シリコンの自然
酸化膜の生成速度についてはサーフェイスサイエンス３
０．９１ （１９７２）（Ｓｕｒｆ、ｓｃｉ、３０゜９
１、（１９７２））および、ソリッド ステイト エレ
クトロン ２５，８７５ （１９８２）（Ｓｏｌｉｄ
５ｔａｔｅ Ｅｌｅｃｔｒｏｎ ２５．８７５（１９８
２））において論じられており、１０３ｓｅｃで単結晶
シリコンは１．０ｎｍ程度の自然酸化膜ができるがａ−
３ｉ：Ｈは０．１ｎｍ 以下であり、はとんど形成され
てない、よって、このａ−８ｉ：Ｈ上に非晶質シリコン
膜を形成すると、表面の水素が抜けて、そこにシリコン
が結合し、酸化膜の介在しない、熱膨張係数差のない界
面が形成され、核生成の抑制された界面になる。The reason why the above method improves crystallinity is as follows. By forming an a-3i:H film on an insulating substrate or by modifying the surface of the insulating substrate by implanting molecular ions of H and Si, the interface between this base and the amorphous silicon film formed thereon can be improved. This is because the generation of crystal nuclei that occurs is suppressed. In other words, the generation of crystal nuclei is caused by differences in thermal expansion coefficients and lattice distortion at the interface, so it tends to occur at the interface between an insulating substrate or an oxide film and a silicon film, but it is less likely to occur at the 5i-5i interface. Therefore, in order to suppress nucleation at the interface, it is necessary to create a 5i-3i interface without intervening an oxide film at the interface. That is, by interposing the film a-8i:H, which is not easily oxidized and has a small difference in coefficient of thermal expansion with the silicon film, between the amorphous silicon film and the insulating substrate, nucleation can be suppressed. a-8i: Regarding the formation rate of natural oxide film of H and single crystal silicon, see Surface Science 3.
0.91 (1972) (Surf, sci, 30°9
1, (1972)) and Solid State Electron 25,875 (1982) (Solid State Electron 25,875 (1982))
5tate Electron 25.875 (198
As discussed in 2)), a natural oxide film of about 1.0 nm is formed on single crystal silicon in 103 seconds, but a-
3i:H is less than 0.1 nm and is rarely formed. Therefore, when an amorphous silicon film is formed on this a-8i:H, hydrogen on the surface is removed and silicon is formed there. They combine to form an interface with no intervening oxide film and no difference in thermal expansion coefficient, resulting in an interface where nucleation is suppressed.
また、ａ−Ｓｉ：Ｈは６００℃での熱処理をしても結晶
化しないため、ガラス基板とａ−３ｉ：Ｈの界面で核が
生成しても非晶質シリコン膜との界面まで、核が到達し
ない。よって、非晶質膜の核の数は、絶縁法・板の影響
を受けず、ａ−３ｉ：Ｈと非晶質シリコン膜の界面での
み生成する数となるため、核の生成を抑制することがで
きる。このように核の数が少くなるため大きな結晶粒を
得ることができる。In addition, since a-Si:H does not crystallize even after heat treatment at 600°C, even if nuclei are generated at the interface between the glass substrate and a-3i:H, the nuclei will not reach the interface with the amorphous silicon film. is not reached. Therefore, the number of nuclei in the amorphous film is not affected by the insulation method or plate and is generated only at the interface between a-3i:H and the amorphous silicon film, so the generation of nuclei is suppressed. be able to. Since the number of nuclei is reduced in this way, large crystal grains can be obtained.
一方、シリコンを結晶化して、これを種結晶として結晶
成長させる場合、表面には短時間で自然酸化膜が形成さ
れるため、非晶質シリコンとの界面に自然酸化膜が介在
し、同相成長は妨げられる。On the other hand, when silicon is crystallized and used as a seed crystal for crystal growth, a natural oxide film is formed on the surface in a short time, so the natural oxide film is interposed at the interface with amorphous silicon, resulting in in-phase growth. is hindered.
さらに、この自然酸化膜界面では新たな核生成がおこる
ため、核の数は増加し、結晶粒は大きくならない。Furthermore, since new nucleation occurs at this natural oxide film interface, the number of nuclei increases and the crystal grains do not become large.
以下、本発明の一実施例を第１図、第４図により説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 and 4.
第４図Ａに示すように、まずガラス基板１上に直流４極
スパツタリング装置を用いてａ−８ｉ：Ｈ２を膜厚約５
００人形成した。雰囲気ガスとしてＡｒとＨ２を用い、
２Ｘ１０−”Ｐａの状懲で、基板温度３００℃以下にし
てスパッタリングを行った。上記により作製した試料上
に、第４図Ｂで示すように、ＬＰＣＶＤ法を用いて、５
５０℃、１ 、 ＯＴｏｒｒで非晶質シリコン膜３を１
５００人堆積した。次に、第４図Ｃに示すように、Ｎ２
雰囲気中約６００℃で所定時間熱処理することにより、
非晶質シリコン膜３のみが結晶化して、多結晶シリコン
膜４になった。この膜をアイランドホト。As shown in FIG. 4A, first, a-8i:H2 is deposited on a glass substrate 1 to a thickness of approximately 5 mm using a DC 4-pole sputtering device.
00 people formed. Using Ar and H2 as atmospheric gas,
Sputtering was carried out at a substrate temperature of 300° C. or less under conditions of 2×10 −” Pa. As shown in FIG.
The amorphous silicon film 3 was heated at 50°C and 1 O Torr.
500 people deposited. Next, as shown in FIG. 4C, N2
By heat-treating in an atmosphere at about 600℃ for a predetermined time,
Only the amorphous silicon film 3 was crystallized and became a polycrystalline silicon film 4. Island photo this film.
エツチングの工程を通した後、常圧ＣＶＤ法によりゲー
ト絶縁膜用の５ｉＯｚ１８を１０００人堆積させる。次
にゲート電極用のｐｏｌｙ −Ｓ ｉ膜１９を５５０℃
、１ 、 ＯＴｏｒｒの条件で３５００人堆積させる。After passing through the etching process, 1000 layers of 5iOz18 for a gate insulating film are deposited by atmospheric pressure CVD. Next, the poly-Si film 19 for the gate electrode was heated at 550°C.
, 1, 3500 people are deposited under OTorr conditions.
ゲート絶縁膜１９をホト、エッチした後、ソ−ス、ドレ
イン領域１６．１７のインプラを行う。After photo-etching the gate insulating film 19, implantation of source and drain regions 16 and 17 is performed.
条件はリン（Ｐ）を用い、５ Ｘ １０１１５ｃｍ−”
のドーズ量、３０ＫｅＶの電圧である。リンガラスから
なるパッシベーション膜２１を４８０℃で５０００人堆
積させる。さらにＮ２中、６００℃の条件で２０時間熱
処理を行い、インプラ領域を活性化させる。コンタクト
用のホト、エッチ工程の後、ＡＩ２電極２０を６０００
人スパッタする。本実施例のＴＰＴのチャネル幅、チャ
ネル長はそれぞれ３０μｍ、１０μｍである。The conditions are phosphorus (P), 5 x 10115 cm-”
The dose amount is 30 KeV and the voltage is 30 KeV. A passivation film 21 made of phosphorus glass is deposited by 5000 people at 480°C. Further, heat treatment is performed in N2 at 600° C. for 20 hours to activate the implant region. After the photo and etch process for contact, the AI2 electrode 20 was
People spatter. The channel width and channel length of the TPT in this example are 30 μm and 10 μm, respectively.
次に本発明の第２実施例について第５図Ａ〜第５図Ｃお
よび第６図に基づいて説明する。Next, a second embodiment of the present invention will be described based on FIGS. 5A to 5C and FIG. 6.
第５図に示すように、ガラス基板１上にシリコンと水素
の分子イオンを低エネルギーにてイオン注入してガラス
基板表面をＨとＳｉの化合物層６とし、ガラス基板表面
を改質する。As shown in FIG. 5, molecular ions of silicon and hydrogen are implanted into a glass substrate 1 at low energy to form a compound layer 6 of H and Si on the surface of the glass substrate, thereby modifying the surface of the glass substrate.
第６図は、低エネルギーイオン注入装置の説明図である
。真空容器１０１中のアノード電極１０３にガラス基板
１を設置し、容器内へＨｚで希釈したＳｉＨ４ガスを導
入する。容器内圧力は０．５〜５ 、 ＯＴｏｒｒ程度
が良い０次に加熱ヒータ１０４により基板１を２００〜
３００℃に加熱しながらアノード電極１０３に対向する
カソード電極１０２に高周波電圧を印加して両電極間に
グロー放電を発生させてＳｉＨ４ガス、Ｈ２ガスをプラ
ズマ状態１０７とする。プラズマ中のイオンＨ＋、Ｓｉ
”ｔＳ ｉ Ｈ＋、 Ｓ ｉ Ｈ２＋、 Ｓ ｉ＋Ｈａ
は加速電源１１１に接続された加速電極１１０によって
引きだされて、１〜５ｋＶ程度の比較的低い電圧で加速
され。FIG. 6 is an explanatory diagram of a low energy ion implantation device. A glass substrate 1 is placed on an anode electrode 103 in a vacuum container 101, and SiH4 gas diluted at Hz is introduced into the container. The pressure inside the container is 0.5~5, and the substrate 1 is heated to 200 ~
While heating to 300° C., a high frequency voltage is applied to the cathode electrode 102 facing the anode electrode 103 to generate a glow discharge between the two electrodes to bring the SiH4 gas and H2 gas into a plasma state 107. Ions H+, Si in plasma
”tS i H+, S i H2+, S i+Ha
is extracted by an accelerating electrode 110 connected to an accelerating power source 111 and accelerated at a relatively low voltage of about 1 to 5 kV.
基板１に照射され基板表面がＨとＳｉの化合物層６にな
る。この装置は分子イオンを注入できること、大電流が
とれるので表面に多量にイオンを注入できること、低加
速電圧であるため浅く絶縁基板表面にイオン注入可能で
あることから絶縁基板の表面改質に適している。The substrate 1 is irradiated with light, and the surface of the substrate becomes a compound layer 6 of H and Si. This device is suitable for surface modification of insulating substrates because it can implant molecular ions, it can draw a large current so it can implant a large amount of ions into the surface, and its low acceleration voltage allows it to shallowly implant ions into the surface of the insulating substrate. There is.
以上のように表面改質した絶縁基板上に第１実施例と同
様に第４図Ｂに示すようにＬＰＣＶＤ法で非晶質シリコ
ン膜３を堆積した０次に第５図Ｃに示すように、Ｎ２雰
囲気中６００℃で熱処理することにより多結晶シリコン
膜４になった。以下第１実施例と同様のプロセスにてＴ
ＰＴを形成する。As shown in FIG. 4B, an amorphous silicon film 3 was deposited by the LPCVD method on the insulating substrate whose surface had been modified as described above, as in the first embodiment. A polycrystalline silicon film 4 was obtained by heat treatment at 600° C. in an N2 atmosphere. Hereinafter, in the same process as in the first embodiment, T
Form PT.
第１および第２実施例で作ったＴＰＴの結晶性を評価す
るため、電界効果移動度を測定したところ、約５０ａｌ
１２−／ｖ−３となり、従来の絶縁基板に直接能動層で
ある多結晶シリコン膜を形成したＴＰＴに比べて約１．
５倍大きくなり、結晶性の優れた多結晶シリコン膜を得
ることができた。In order to evaluate the crystallinity of TPT made in the first and second examples, the field effect mobility was measured and it was found that approximately 50al
12-/v-3, about 1.1.
It was possible to obtain a polycrystalline silicon film that was five times larger and had excellent crystallinity.
以上、本発明を実施例に基づき説明したが、本発明の上
述の第１及び第２実施例に限定されるものではなく、本
発明の技術的思想に基づく様々の変態が可能である。た
とえば、第１実施例のａ −８ｉ：Ｈの形成法としては
モノシランのグロー放電分解を用いても可能である。基
板温度３００℃以下、ＲＦパワー３００Ｗとした。Although the present invention has been described above based on embodiments, it is not limited to the above-described first and second embodiments of the present invention, and various modifications based on the technical idea of the present invention are possible. For example, glow discharge decomposition of monosilane may be used to form a-8i:H in the first embodiment. The substrate temperature was 300° C. or lower, and the RF power was 300 W.
また、第１実施例ではａ−８ｉ：Ｈを堆積したが、同じ
ように水素を多量に含む膜たとえば、ａ−８ｉＯ：Ｈ，
ａ−８ｉＮ：Ｈ，ａ−８ｉＣ：Ｈを用いることにより同
様の効果があげられる。Further, in the first embodiment, a-8i:H was deposited, but similarly, films containing a large amount of hydrogen, such as a-8iO:H,
Similar effects can be obtained by using a-8iN:H and a-8iC:H.
また、第１および第２実施例において、第４図Ｂの工程
で減圧ＣＶＤ法により非晶質シリコン膜３を形成してい
るが、スパッタ法９分子線蒸着法を使っても同様の効果
があげられる。In addition, in the first and second embodiments, the amorphous silicon film 3 is formed by low pressure CVD in the step shown in FIG. can give.
本発明によれば、結晶粒径が大きく、結晶性の良い多結
晶シリコン膜を得ることができ、ひいては、キャリア移
動度の大きいＴＰＴを得ることができる。According to the present invention, a polycrystalline silicon film having a large crystal grain size and good crystallinity can be obtained, and as a result, a TPT with high carrier mobility can be obtained.
第１図は本発明第一実施例のＴＰＴの構造を示す図、第
２図は非晶質シリコン膜の熱処理における結晶成長過程
のモデル図、第３図は下地膜有無での多結晶シリコン膜
のＸ線回折スペクトルの比較図、第４図は本発明第一実
施例の各製造工程における第１図のＴＰＴの構造を示す
図、第５図は本発明第二実施例の絶縁基板改質工程にお
ける構造を示す図、第６図は低エネルギーイオン注入装
置を示す図である。
１・・・ガラス基板、２・・・ａ−３ｉ：Ｎ１３・・・
非晶質シリコン膜、４・・・多結晶シリコン膜、５・・
・イオン注入、６・・・ＨとＳｉの化合物層、１６・・
・ソース電極、１７・・・ドレイン電極、１８・・・ゲ
ート絶縁膜、１９・・・ゲート電極、２０・・・ＡΩ電
極、２１・・・リンガラス、１０１・・・真空容器、１
０２・・・カソード電極、１０３・・・アノード電極、
１０４・・・加熱ヒータ、１０７・・・プラズマ状態、
１１０・・・加速電極、１１１・・・加速電源。
第
幻
（Ｃ）
回ｊｆｒ角
、２θ
（すFig. 1 is a diagram showing the structure of TPT according to the first embodiment of the present invention, Fig. 2 is a model diagram of the crystal growth process during heat treatment of an amorphous silicon film, and Fig. 3 is a polycrystalline silicon film with and without a base film. 4 is a diagram showing the structure of the TPT of FIG. 1 in each manufacturing process of the first embodiment of the present invention, and FIG. 5 is a diagram showing the structure of the TPT of FIG. 1 in the second embodiment of the present invention. FIG. 6 is a diagram showing a structure in a process, and FIG. 6 is a diagram showing a low energy ion implantation apparatus. 1...Glass substrate, 2...a-3i:N13...
Amorphous silicon film, 4... Polycrystalline silicon film, 5...
・Ion implantation, 6...H and Si compound layer, 16...
- Source electrode, 17... Drain electrode, 18... Gate insulating film, 19... Gate electrode, 20... AΩ electrode, 21... Phosphorus glass, 101... Vacuum vessel, 1
02... Cathode electrode, 103... Anode electrode,
104... Heater, 107... Plasma state,
110... Accelerating electrode, 111... Accelerating power source. Phantom (C) times jfr angle, 2θ (s
Claims (1)
ンと水素で被覆する工程と、第１の非晶質シリコン膜を
前記被覆した基板上に形成する工程と第１の非晶質シリ
コン膜のみを結晶成分に変換する熱処理工程を具備する
ことを特徴とする薄膜半導体装置の製造方法。 ２、前記第１項記載の下地部分は、水素化アモルファス
シリコン膜を堆積する、あるいは絶縁基板表面にシリコ
ンと水素の分子イオンを注入することにより形成するこ
とを特徴とする薄膜半導体装置の製造方法。 ３、前記第２項記載の水素化アモルファスシリコン膜を
モノシランのグロー放電分解、水素を含む雰囲気ガス中
でのスパッタ法を用いて形成することを特徴とする薄膜
半導体装置の製造方法。 ４、前記第１項記載の非晶質シリコン膜を減圧ＣＶＤ法
、スパッタ法、分子線蒸着法を用いて形成することを特
徴とする薄膜半導体装置の製造方法。 ５、前記第２項記載の方法により表面を水素とシリコン
で被覆することを特徴とする絶縁基板の、表面改質方法
。[Claims] 1. A step of coating a base portion of an active layer to be formed on an insulating substrate with silicon and hydrogen; a step of forming a first amorphous silicon film on the coated substrate; 1. A method for manufacturing a thin film semiconductor device, comprising a heat treatment step for converting only one amorphous silicon film into a crystalline component. 2. A method for manufacturing a thin film semiconductor device, characterized in that the underlying portion described in item 1 is formed by depositing a hydrogenated amorphous silicon film or by implanting molecular ions of silicon and hydrogen into the surface of an insulating substrate. . 3. A method for manufacturing a thin film semiconductor device, characterized in that the hydrogenated amorphous silicon film described in item 2 is formed using glow discharge decomposition of monosilane and sputtering in an atmospheric gas containing hydrogen. 4. A method for manufacturing a thin film semiconductor device, characterized in that the amorphous silicon film described in item 1 is formed using a low pressure CVD method, a sputtering method, or a molecular beam evaporation method. 5. A method for surface modification of an insulating substrate, characterized in that the surface is coated with hydrogen and silicon by the method described in item 2 above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2745489A JPH02207537A (en) | 1989-02-08 | 1989-02-08 | Manufacture of thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2745489A JPH02207537A (en) | 1989-02-08 | 1989-02-08 | Manufacture of thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02207537A true JPH02207537A (en) | 1990-08-17 |
Family
ID=12221570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2745489A Pending JPH02207537A (en) | 1989-02-08 | 1989-02-08 | Manufacture of thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02207537A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06291316A (en) * | 1992-02-25 | 1994-10-18 | Semiconductor Energy Lab Co Ltd | Thin film insulated gate semiconductor device and manufacture thereof |
| US5894151A (en) * | 1992-02-25 | 1999-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having reduced leakage current |
| US5962897A (en) * | 1992-06-18 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6028333A (en) * | 1991-02-16 | 2000-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US6486495B2 (en) | 1990-07-24 | 2002-11-26 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6709907B1 (en) | 1992-02-25 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
-
1989
- 1989-02-08 JP JP2745489A patent/JPH02207537A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7026200B2 (en) | 1990-07-24 | 2006-04-11 | Semiconductor Energy Laboratory Co. Ltd. | Method for manufacturing a semiconductor device |
| US6486495B2 (en) | 1990-07-24 | 2002-11-26 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
| US6028333A (en) * | 1991-02-16 | 2000-02-22 | Semiconductor Energy Laboratory Co., Ltd. | Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors |
| US5894151A (en) * | 1992-02-25 | 1999-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having reduced leakage current |
| US7649227B2 (en) | 1992-02-25 | 2010-01-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of forming the same |
| US7148542B2 (en) | 1992-02-25 | 2006-12-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of forming the same |
| US6709907B1 (en) | 1992-02-25 | 2004-03-23 | Semiconductor Energy Laboratory Co., Ltd. | Method of fabricating a thin film transistor |
| JPH06291316A (en) * | 1992-02-25 | 1994-10-18 | Semiconductor Energy Lab Co Ltd | Thin film insulated gate semiconductor device and manufacture thereof |
| US5962897A (en) * | 1992-06-18 | 1999-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US6790749B2 (en) | 1992-10-09 | 2004-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7109108B2 (en) | 1992-10-09 | 2006-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device having metal silicide |
| US6624477B1 (en) | 1992-10-09 | 2003-09-23 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
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| US6455875B2 (en) | 1992-10-09 | 2002-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having enhanced field mobility |
| US7723788B2 (en) | 1992-10-09 | 2010-05-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US8017506B2 (en) | 1992-10-09 | 2011-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
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