JPH02207377A - Arrangement design supporting device - Google Patents
Arrangement design supporting deviceInfo
- Publication number
- JPH02207377A JPH02207377A JP1030285A JP3028589A JPH02207377A JP H02207377 A JPH02207377 A JP H02207377A JP 1030285 A JP1030285 A JP 1030285A JP 3028589 A JP3028589 A JP 3028589A JP H02207377 A JPH02207377 A JP H02207377A
- Authority
- JP
- Japan
- Prior art keywords
- parts
- arrangement
- net
- wiring
- specified
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 19
- 239000000919 ceramic Substances 0.000 claims description 4
- 230000008878 coupling Effects 0.000 abstract description 4
- 238000010168 coupling process Methods 0.000 abstract description 4
- 238000005859 coupling reaction Methods 0.000 abstract description 4
- 230000003993 interaction Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 5
- 238000000605 extraction Methods 0.000 description 2
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電気機器の実装設計における配置設計支援装置
に関し、特にPWB、セラミック配線板の部品配置処理
の支援方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a layout design support device for packaging design of electrical equipment, and particularly to a support method for component layout processing for PWBs and ceramic wiring boards.
従来の部品配置支援装置の部品の選択は、部品のシンボ
ル番号をファイル上の出現層、もしくは、ソート順で並
べ、設計者はそれらから部品を選んで回路図を見ながら
配置していた。When selecting components using conventional component placement support devices, the symbol numbers of the components are arranged in the layer in which they appear in the file or in sorted order, and the designer selects the components from these and places them while looking at the circuit diagram.
上述した従来の部品配置設計支援装置は、選んだ部品の
接続情報を設計者が回路図上で確認してから配置しなく
てはならないという欠点と、部品配置後、バスやクロッ
ク等のクリティカルバスがルータ−の配線条件によって
は、設計者の意図した通りの配線パターンにならないと
いう欠点がある。The conventional component placement design support device described above has the drawback that the designer must check the connection information of the selected component on the circuit diagram before placing it, and after placing the component, it is necessary to check the connection information of the selected component on the circuit diagram before placing it. However, depending on the wiring conditions of the router, the wiring pattern may not be as intended by the designer.
本発明の配線設計支援装置の構成は、プリント配線板及
びセラミック配線板の部品配置設計において、その部品
間の論理接続情報を入力する入力手段と、前記部品の配
置上、軸となるNET (バス、クロック等のクリティ
カルバス)の概略的な配線通路を配線可能領域上に指定
する指定手段と、前記入力手段により入力された論理接
続情報より、前記指定手段で指定されたNETと接続す
る部品を抽出する抽出手段と、この抽出手段で抽出され
た部品を前記指定手段で指定されたNETとの接続結合
度の高い順に並べる第1の配置手段と、この第1の配置
手段で並べられた部品と接続する部品をグループ化して
接続結合度の順に並べる第2の配置手段と、前記第1の
配置手段で並べられた部品を前記指定手段で指定された
NETの概略配線通路を参考に会話型に配置処理させる
第1の配置処理手段と、前記第2の配置手段で並べられ
た部品を前記第1の配置処理手段により処理された部品
配置を参考に会話型に配置処理させる第2の配置処理手
段と、前記指定手段で指”定されたNETの概略配線通
路を次の配線処理に引渡す手段とを含んで構成されるこ
とを特徴とする。The configuration of the wiring design support device of the present invention includes an input means for inputting logical connection information between the components in component layout design of printed wiring boards and ceramic wiring boards, and a NET (bus) that is the axis in the layout of the components. , a critical bus such as a clock, etc.) on the routeable area, and a component to be connected to the NET specified by the specifying means based on the logical connection information inputted by the input means. an extraction means for extracting; a first arrangement means for arranging the parts extracted by the extraction means in order of the degree of connection with the NET specified by the specification means; and parts arranged by the first arrangement means. a second arranging means for grouping the parts to be connected to and arranging them in the order of connection degree; and a second arranging means for grouping the parts connected to each other and arranging them in the order of connection degree; a first arrangement processing means that performs placement processing on the parts arranged by the second arrangement processing means; and a second arrangement that performs arrangement processing of the parts arranged by the second arrangement processing means in an interactive manner with reference to the parts arrangement processed by the first arrangement processing means. The present invention is characterized in that it includes a processing means and a means for passing the general wiring path of the NET specified by the specifying means to the next wiring process.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)及び(b)は本発明の一実施例の実行フロ
ーチャートである。FIGS. 1(a) and 1(b) are execution flowcharts of an embodiment of the present invention.
処理1・・・プリント配線板(以下、PWBと称す)及
びセラミック配線板の部品間の論理接続情報を入力し、
記憶域Aへ格納する。Process 1: Input logical connection information between parts of printed wiring board (hereinafter referred to as PWB) and ceramic wiring board,
Store in storage area A.
処理2・・・配置上、軸となるバス、クロック等のクリ
ティカルバス(NET)のNET名と概略配線経路を第
2図(a)に示す様に、記憶域Bへ格納する。Process 2: NET names and rough wiring routes of critical buses (NETs) such as buses serving as axes and clocks are stored in storage area B as shown in FIG. 2(a).
処理3・・・記憶域Aより、処理2で指定したNETと
接続する部品を抽出し、記憶域Cへ格納する。Process 3: Extracts the component connected to the NET specified in process 2 from storage area A and stores it in storage area C.
処理4・・・記憶域C上に格納された部品と記憶域B上
のNETとの接続結合度を記憶域Aより計算し、結合度
順位を記憶域Cへ格納する。記憶域Cの例を第3図に示
す。Process 4: The degree of connection between the parts stored in storage area C and the NET in storage area B is calculated from storage area A, and the degree of connection ranking is stored in storage area C. An example of storage area C is shown in FIG.
処理5・・・記憶域C上の各部品と接続する部品を記憶
域Aより抽出し、グループ化して記憶域りへ格納する。Process 5: Components connected to each component on storage area C are extracted from storage area A, grouped, and stored in the storage area.
処理6・・・記憶域り上の部品と記憶域C上の対応する
部品との接続結合度を記憶域Aより計算し、結合度順位
を記憶域りへ格納する。記憶域りの例を第4図に示す。Process 6: Calculate the degree of connection between the component on the storage area A and the corresponding component on the storage area C from the storage area A, and store the degree of connection rank in the storage area A. An example of the storage area is shown in FIG.
処理7・・・記憶域C上の部品を記憶域B上の指定NE
Tとの結合度層に指定NETの概略径・路付近に配置す
る。第2図(b)に上述の例を示す。配置済の部品は記
憶域C上にフラグ1を立てる。Process 7...Specify parts in storage area C to storage area B NE
It is placed near the approximate path/path of the specified NET in the coupling degree layer with T. FIG. 2(b) shows the above example. A flag 1 is set in the storage area C for the placed parts.
処理8・・・記憶域C上の全部品について配置したら、
処理9へ進む、そうでなければ、処理7へ戻る。Process 8... After placing all the parts on storage area C,
Proceed to process 9; otherwise, return to process 7.
処理9・・・記憶域り上の各部品を各グループ内での接
続結合度層に処理7で配置した部品のまわりに配置して
いく、配置済部品にはフラグ1を立て、記憶域りへ格納
する。一つの部品が複数のグループにまたがる場合、1
つのグループで配置された時、他のグループの配置済フ
ラグも1を立てる。Process 9: Arrange each component on the storage area around the parts placed in process 7 in the connectivity degree layer within each group, set flag 1 for the placed parts, and place the parts on the storage area. Store it in If one part spans multiple groups, 1
When placed in one group, the placed flags of other groups are also set to 1.
処理10・・・記憶域り上の全部品について配置したら
終了し、そうでなければ処理9へ戻る。Process 10: Ends when all parts on the storage area are placed; otherwise, returns to process 9.
処理11・・・部品配置情報を外部ファイルへ出力する
。Process 11: Output component placement information to an external file.
処理12・・・記憶域B上の概略配線経路を外部ファイ
ルへ出力する。Process 12: Output the approximate wiring route on storage area B to an external file.
以上の実行により第2図<c>の様な部品配置が完了す
る。By executing the above steps, the component arrangement as shown in FIG. 2 <c> is completed.
〔発明の効果〕
以上説明したように本発明は、配置上、軸となるNET
の概略配線経路を配線可能領域上に指定する手段と、概
略配線経路に接続結合度の高い部品を選び配置させる手
段と、配置結果と概略配線経路を外部へ出力する手段と
を有しているので、実装設計者は配置処理段階よりクリ
ティカルバスの配線制限条件を意図した配置設計ができ
るという効果がある。[Effects of the Invention] As explained above, the present invention provides
means for specifying a schematic wiring route on the routable area, means for selecting and arranging components with a high degree of connection on the schematic wiring route, and means for outputting the placement result and the schematic wiring route to the outside. Therefore, the implementation designer can carry out a layout design that takes into account the wiring restriction conditions of the critical bus from the layout processing stage.
第1図(a)及び(b)は本発明の一実施例の実行フロ
ーチャート、第2図は概略配線経路指定の例を示す図、
第3図及び第4図は第1図の記憶域C及び記憶域りの例
を示す図である。FIGS. 1(a) and (b) are execution flowcharts of an embodiment of the present invention, FIG. 2 is a diagram showing an example of general wiring route designation,
FIGS. 3 and 4 are diagrams showing examples of the storage area C and the storage area of FIG. 1.
Claims (1)
において、その部品間の論理接続情報を入力する入力手
段と、前記部品の配置上、軸となるNET(バス,クロ
ック等のクリティカルパス)の概略的な配線通路を配線
可能領域上に指定する指定手段と、前記入力手段により
入力された論理接続情報より、前記指定手段で指定され
たNETと接続する部品を抽出する抽出手段と、この抽
出手段で抽出された部品を前記指定手段で指定されたN
ETとの接続結合度の高い順に並べる第1の配置手段と
、この第1の配置手段で並べられた部品と接続する部品
をグループ化して接続結合度の順に並べる第2の配置手
段と、前記第1の配置手段で並べられた部品を前記指定
手段で指定されたNETの概略配線通路を参考に会話型
に配置処理させる第1の配置処理手段と、前記第2の配
置手段で並べられた部品を前記第1の配置処理手段によ
り処理された部品配置を参考に会話型に配置処理させる
第2の配置処理手段と、前記指定手段で指定されたNE
Tの概略配線通路を次の配線処理に引渡す手段とを含む
ことを特徴とする配置設計支援装置。In the component layout design of printed wiring boards and ceramic wiring boards, input means for inputting logical connection information between the components and a rough outline of the NET (critical path such as bus, clock, etc.) that is the axis in the layout of the components are provided. a specifying means for specifying a wiring path on a routeable area; an extracting means for extracting a component connected to the NET specified by the specifying means from the logical connection information input by the input means; The specified part is specified by the specified means.
a first arrangement means for arranging the parts in order of the degree of connection with the ET; a second arrangement means for grouping the parts connected to the parts arranged by the first arrangement means and arranging them in order of the degree of connection; A first placement processing means that interactively places the parts arranged by the first placement means with reference to the general wiring path of the NET specified by the specification means, and the second placement means arranges the parts. a second placement processing means that interactively places the parts with reference to the component placement processed by the first placement processing means; and a NE specified by the specification means.
1. A layout design support device comprising: means for passing the rough wiring path of T to the next wiring process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1030285A JPH02207377A (en) | 1989-02-08 | 1989-02-08 | Arrangement design supporting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1030285A JPH02207377A (en) | 1989-02-08 | 1989-02-08 | Arrangement design supporting device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02207377A true JPH02207377A (en) | 1990-08-17 |
Family
ID=12299448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1030285A Pending JPH02207377A (en) | 1989-02-08 | 1989-02-08 | Arrangement design supporting device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02207377A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008059078A (en) * | 2006-08-29 | 2008-03-13 | Renesas Technology Corp | Manufacturing method of semiconductor device |
JP2021039479A (en) * | 2019-09-02 | 2021-03-11 | 東芝三菱電機産業システム株式会社 | Apparatus and method for plant engineering assistance |
-
1989
- 1989-02-08 JP JP1030285A patent/JPH02207377A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008059078A (en) * | 2006-08-29 | 2008-03-13 | Renesas Technology Corp | Manufacturing method of semiconductor device |
JP2021039479A (en) * | 2019-09-02 | 2021-03-11 | 東芝三菱電機産業システム株式会社 | Apparatus and method for plant engineering assistance |
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