JPH02206122A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02206122A JPH02206122A JP2698189A JP2698189A JPH02206122A JP H02206122 A JPH02206122 A JP H02206122A JP 2698189 A JP2698189 A JP 2698189A JP 2698189 A JP2698189 A JP 2698189A JP H02206122 A JPH02206122 A JP H02206122A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- alloy
- conductive layer
- semiconductor element
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 26
- 239000000956 alloy Substances 0.000 claims abstract description 26
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 77
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、信頼性の高い配線構造を有する半導体装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a highly reliable wiring structure.
半導体装置の配線を形成する導電層は、一般にＡＩ２合
金が用いられている。このへβ合金は電気抵抗が低いこ
と、シリコン基板へのオーミック性が良いこと、酸化珪
素膜との付着力が強いこと、加工しやすいこと、Ａｕワ
イヤのボンディング性が良いこと等の長所がある。Generally, an AI2 alloy is used for a conductive layer forming wiring of a semiconductor device. This beta alloy has the advantages of low electrical resistance, good ohmic properties to silicon substrates, strong adhesion to silicon oxide films, ease of processing, and good bonding properties with Au wires. .
ところが、へｌ原子は自己拡散しやすいためにエレクト
ロマイグレーション不良が生じやすい。However, since hel atoms tend to self-diffuse, electromigration failures tend to occur.
また、プラズマ窒化珪素膜等のような強い圧縮応力を有
した膜がバンシベーション膜として用いられると、応力
を緩和するようにＢ原子あるいは空孔が移動したり集積
してＡ４合金の断線が生じるという問題がある。とくに
、配線の微細化が進むとこれらの信頼性の問題が顕著に
なる。Furthermore, when a film with strong compressive stress such as a plasma silicon nitride film is used as a bancivation film, B atoms or vacancies move or accumulate to relieve the stress, resulting in disconnection of the A4 alloy. There is a problem. In particular, as wiring becomes finer, these reliability problems become more prominent.
そこで、近年、半導体装置の配線を形成する導電層の材
料としてＡｊ２合金に代わり、Ｃｕを用いた導電層が注
目されつつある。このＣｕは、電気抵抗が低くく、Ａ１
合金に比べて自己拡散係数が小さく、前記信頼性の問題
が生じにくいため、微細配線の材料として最もを望な金
属であると考えられる。Therefore, in recent years, a conductive layer using Cu, instead of the Aj2 alloy, has been attracting attention as a material for a conductive layer forming wiring of a semiconductor device. This Cu has low electrical resistance, and A1
Since it has a smaller self-diffusion coefficient than alloys and is less likely to cause the aforementioned reliability problems, it is considered to be the most desirable metal as a material for fine wiring.
このＣｕの導電層を用いた従来技術の一例を第２図に示
す。図は簡明化のため、配線−半導体基板すなわちここ
では導電層とシリコン基板のコンタクト部分を示し、半
導体基板上のトランジスタ領域等の各構造は従来と変わ
らないものとする。An example of a conventional technique using this Cu conductive layer is shown in FIG. For the sake of simplicity, the figure shows a contact portion between wiring and a semiconductor substrate, that is, a conductive layer and a silicon substrate here, and each structure such as a transistor region on the semiconductor substrate is assumed to be unchanged from the conventional one.
第２図に示すように、ｐ型シリコン基板１上にｎ型拡散
層２が設けられ、ｐ型シリコン基板１上の回路素子（図
示せず）を覆うように酸化珪素膜３からなる層間絶縁膜
が形成され、ｎ型拡散層２の上の酸化珪素膜３にコンタ
ク［窓８が設けられた半導体素子１０を存し、その半導
体素子１０の酸化珪素膜３上に形成されたＣｕ導電層６
がコンタクト窓８においてｎ型拡散層２と接触した構造
となっている。As shown in FIG. 2, an n-type diffusion layer 2 is provided on a p-type silicon substrate 1, and an interlayer insulation layer made of a silicon oxide film 3 covers circuit elements (not shown) on the p-type silicon substrate 1. A Cu conductive layer is formed on the silicon oxide film 3 on the n-type diffusion layer 2. 6
is in contact with the n-type diffusion layer 2 at the contact window 8 .
しかしながら、この半導体装置ば、Ｃｕ導電層６と酸化
珪素膜３の密着力が弱く、製造工程中にＣｕ導電層６が
剥離するという問題があった。However, this semiconductor device has a problem in that the adhesion between the Cu conductive layer 6 and the silicon oxide film 3 is weak, and the Cu conductive layer 6 peels off during the manufacturing process.
また、製造工程中の熱処理によってＣｕｉ電層６のＣｕ
原子がｎ型拡散層２に設けたコンタクト部分からｐ型シ
リコン基板１中へ拡散してｐ型シリコン基板１上に設け
た回路素子の特性を劣化させるという問題があった。Also, due to the heat treatment during the manufacturing process, the Cu of the Cui conductive layer 6
There has been a problem in that atoms diffuse into the p-type silicon substrate 1 from the contact portion provided in the n-type diffusion layer 2 and deteriorate the characteristics of circuit elements provided on the p-type silicon substrate 1.
さらに、第２図には示していないが、Ｃｕ導電層にする
と、ｆンディ〉・グパノド部もＣｕ膜によって形成され
ることとなるため、Ａｕワイヤの結合性が劣るという問
題があった。。Further, although not shown in FIG. 2, if a Cu conductive layer is used, the bonding property of the Au wire is poor because the fnd and gupanodic portions are also formed of a Cu film. .
したがって、この発明の目的は、配線を形成する導電層
の製造工程中のｊｉｌｌ離および回路素子の特性の劣化
を防止し 篩ワイヤの結合性を良好にすることが了・き
る半導体装置を提供することである。Therefore, an object of the present invention is to provide a semiconductor device that can prevent jill separation during the manufacturing process of a conductive layer forming wiring and deterioration of characteristics of circuit elements, and improve the bonding properties of sieve wires. That's true.
１課題を解決４−るための手段〕
この発明の半導体装置は、半導体素子に設けた導電層が
、下層から、Ｔｉ層りシ＜はＴｉを主成分とする合金層
、ＴｉＮ層もしくはＴｉＮを主成分とする合金層、Ｃｕ
層もしくはＣｕを主成分とする合金層、Ａ１２層もしく
はＡｊ２を主成分とする合金層の順に積層された四層膜
からなることを特徴とするものである。Means for Solving Problems 1 and 4] In the semiconductor device of the present invention, the conductive layer provided on the semiconductor element is formed of a Ti layer, an alloy layer mainly composed of Ti, a TiN layer, or a TiN layer from the bottom. Alloy layer mainly composed of Cu
It is characterized by being composed of a four-layer film in which an alloy layer containing Cu as a main component, and an A12 layer or an alloy layer containing Aj2 as a main component are laminated in this order.
この発明の半導体装置番こよれば、Ｔｉ層もしくはＴｉ
を主成分とする合金層は半導体素子の酸化珪素膜との密
着性がよ＜、Ｔｉｌ’ＷもしくはＴｉを主成分とする合
金層およびＴｉＮ層もしくはＴｉＮを主成分とする合金
層は半導体素子のシリコン基板へのＣｕ原子の拡散を抑
制し、またＡ１層もしくはＡρを主成分とする合金層は
Ａｕワイヤの結合性がよい。このため、配線を形成する
導電層の製造工程中の剥離および回路素子の特性の劣化
を防止でき、かつＡｕワイヤの結合性を良好にすること
ができる。According to the semiconductor device number of this invention, a Ti layer or a Ti layer
The alloy layer mainly composed of Til'W or Ti has good adhesion to the silicon oxide film of the semiconductor element, and the alloy layer mainly composed of Til'W or Ti and the TiN layer or the alloy layer mainly composed of TiN have good adhesion to the silicon oxide film of the semiconductor element. The diffusion of Cu atoms into the silicon substrate is suppressed, and the A1 layer or the alloy layer containing Aρ as a main component has good bonding properties with Au wires. Therefore, it is possible to prevent peeling of the conductive layer forming the wiring during the manufacturing process and deterioration of the characteristics of the circuit element, and it is possible to improve the bondability of the Au wire.
この発明の一実施例を第１図に基づいて説明する。図で
は第２図に対応して配線−半導体基板すなわちここでは
導電層とシリコン基板のコンタクト部分のみを示してい
る。すなわち、この半導体装置は、ｐ型シリコン基板１
上にｎ型拡散層２が設けられ、ｐ型シリコン基板ｌ上の
回路素子（図示せず）を覆うように酸化珪素膜３からな
る層間絶縁膜が形成され、ｎ型拡散層２の上の酸化珪素
膜３にコンタクト窓８が設けられた半導体素子１０を有
する。この半導体素子１０の酸化珪素膜３およびコンタ
クト窓８の上に、下層から厚さ０，０５μｍの７４層４
、厚さ０．１５ｚ！ｍのＴｉＮ層５．厚さ ０．６μｍ
のＣｕ層６．厚さ０．１０μのｉ層７の順に積層された
導電層９が形成されている。An embodiment of the present invention will be described based on FIG. Corresponding to FIG. 2, the figure only shows the contact portion between the wiring and the semiconductor substrate, that is, the conductive layer and the silicon substrate here. That is, this semiconductor device has a p-type silicon substrate 1
An n-type diffusion layer 2 is provided on top of the n-type diffusion layer 2, and an interlayer insulating film made of a silicon oxide film 3 is formed to cover circuit elements (not shown) on the p-type silicon substrate l. A semiconductor element 10 is provided in which a contact window 8 is provided in a silicon oxide film 3. On the silicon oxide film 3 and contact window 8 of this semiconductor element 10, 74 layers 4 with a thickness of 0.05 μm are formed from the bottom layer.
, thickness 0.15z! m TiN layer5. Thickness: 0.6μm
Cu layer 6. A conductive layer 9 is formed in which an i-layer 7 having a thickness of 0.10 μm is laminated in this order.
この半導体装置によれば、導電層９の下層が酸化珪素膜
３との付着力が強い１１層４であるため、導電層９の配
線が製造工程中に剥離するという問題を防止できる。ま
た、Ｃｕ層６の下にはＴｉＮ層５と７４層４が設けられ
ており、これらがＣｕ層６からＣｕ原子がｐ型シリコン
基板１へ拡散するのを防止するため回路素子の特性の劣
化は生じない。また、Ｃｕ層６の上部にはＡ１２層７が
設けられているため、Ａｕワイヤの結合性が良好である
。According to this semiconductor device, since the lower layer of the conductive layer 9 is the 11 layer 4 having strong adhesion to the silicon oxide film 3, it is possible to prevent the problem of the wiring of the conductive layer 9 peeling off during the manufacturing process. Further, a TiN layer 5 and a 74 layer 4 are provided under the Cu layer 6, and these layers prevent Cu atoms from diffusing from the Cu layer 6 to the p-type silicon substrate 1, thereby degrading the characteristics of the circuit element. does not occur. Moreover, since the A12 layer 7 is provided on the top of the Cu layer 6, the bondability of the Au wire is good.
なお、７４層４．ＴｉＮ層５．へβ層７の各膜厚はそれ
ぞれ７４層４が０．０１〜０．１０ μｍ 、 Ｔｉ
ＮＦｉ１５が０．０５〜０．２０μｍ 、 Ａｆｆ層
７が０．０５〜０．２０ ｐ ｍの範囲の場合に前記効
果を有効に達成することができる。In addition, 74 layers 4. TiN layer5. The respective film thicknesses of the β layer 7 are 0.01 to 0.10 μm for the 74 layers 4, and Ti
The above effect can be effectively achieved when the NFi 15 has a thickness of 0.05 to 0.20 μm and the Aff layer 7 has a thickness of 0.05 to 0.20 pm.
また、前記実施例は、１１層、 ＴｉＮ層、Ａ４層層、
Ｃｕｊｉを用いたが、いずれの層もそれらを主成分と
する合金層であっても、その性質上前記と同様の効果を
期待することができる。Further, in the above example, 11 layers, a TiN layer, an A4 layer,
Although Cuji was used, even if any of the layers is an alloy layer containing Cuji as a main component, the same effects as described above can be expected due to their properties.
この発明の半導体装置は、Ｔ】層もしくはＴｉを主成分
とする合金層により半導体素子の酸化珪素膜との密着性
を向上でき、Ｔｉ層もしくはＴ＋を主成分とする合金層
およびＴｉＮ層もし７くはＴｉＮを主成分とする合金層
により半導体素子のシリコン基板へのＣｕ原子の拡散を
抑制でき、またへ４層もしくはＡ４を主成分とする合金
層によりＡｕワイヤの結合性を改善することができる。In the semiconductor device of the present invention, the adhesion to the silicon oxide film of the semiconductor element can be improved by the T] layer or the alloy layer mainly composed of Ti, and if the Ti layer or the alloy layer mainly composed of T+ and the TiN layer are In particular, the alloy layer mainly composed of TiN can suppress the diffusion of Cu atoms into the silicon substrate of the semiconductor element, and the bonding property of the Au wire can be improved by using the Ti4 layer or the alloy layer mainly composed of A4. can.
したがって、配線を形成する導電層の製造工程中の剥離
および回路素子の特性の劣化を防止でき、かつＡｕワイ
ヤの結合性を良好にすることができるという効果がある
。Therefore, it is possible to prevent peeling of the conductive layer forming the wiring during the manufacturing process and deterioration of the characteristics of the circuit element, and it is possible to improve the bondability of the Au wire.
第１図はこの発明の一実施例の半導体装置のコンタクト
部分を示す断面図、第２図は従来例の半導体装置のコン
タクト部分を示す断面図である。
４＝４ｉ層、５−ＴｉＮ層、６−Ｃｕ層、７−Ａ７１層
、９・・・導電層、１０・・・半導体素子■FIG. 1 is a sectional view showing a contact portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a contact portion of a conventional semiconductor device. 4=4i layer, 5-TiN layer, 6-Cu layer, 7-A71 layer, 9...conductive layer, 10...semiconductor element ■
Claims (1)
はＴｉを主成分とする合金層、ＴｉＮ層もしくはＴｉＮ
を主成分とする合金層、Ｃｕ層もしくはＣｕを主成分と
する合金層、Ａｌ層もしくはＡｌを主成分とする合金層
の順に積層された四層膜からなることを特徴とする半導
体装置。The conductive layer provided on the semiconductor element is, from the bottom layer, a Ti layer, an alloy layer mainly composed of Ti, a TiN layer, or a TiN layer.
1. A semiconductor device comprising a four-layer film laminated in this order: an alloy layer containing as a main component, a Cu layer or an alloy layer containing Cu as a main component, and an Al layer or an alloy layer containing Al as a main component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2698189A JPH02206122A (en) | 1989-02-06 | 1989-02-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2698189A JPH02206122A (en) | 1989-02-06 | 1989-02-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02206122A true JPH02206122A (en) | 1990-08-15 |
Family
ID=12208336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2698189A Pending JPH02206122A (en) | 1989-02-06 | 1989-02-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02206122A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430258A (en) * | 1991-10-09 | 1995-07-04 | Sony Corporation | Copper interconnection structure and method of preparing same |
| US5547901A (en) * | 1994-05-24 | 1996-08-20 | Lg Semicon Co., Ltd. | Method for forming a copper metal wiring with aluminum containing oxidation barrier |
| US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
-
1989
- 1989-02-06 JP JP2698189A patent/JPH02206122A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430258A (en) * | 1991-10-09 | 1995-07-04 | Sony Corporation | Copper interconnection structure and method of preparing same |
| US5747360A (en) * | 1993-09-17 | 1998-05-05 | Applied Materials, Inc. | Method of metalizing a semiconductor wafer |
| US5904562A (en) * | 1993-09-17 | 1999-05-18 | Applied Materials, Inc. | Method of metallizing a semiconductor wafer |
| US5547901A (en) * | 1994-05-24 | 1996-08-20 | Lg Semicon Co., Ltd. | Method for forming a copper metal wiring with aluminum containing oxidation barrier |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5798301A (en) | Method of manufacturing metal interconnect structure for an integrated circuit with improved electromigration reliability | |
| JPH0760852B2 (en) | Method and apparatus for forming copper alloy conductive plug | |
| JPH0547760A (en) | Semiconductor integrated circuit device and its manufacture and sputtering target for the manufacture | |
| US4022931A (en) | Process for making semiconductor device | |
| JP3106493B2 (en) | Semiconductor device | |
| JPH02206122A (en) | Semiconductor device | |
| JPH02206123A (en) | Semiconductor device | |
| JPH06236878A (en) | Metal wiring | |
| JPH10284437A (en) | Method for forming metal interconnection layer of semiconductor device | |
| JPH06196526A (en) | Manufacture of semiconductor device | |
| JPH0263169A (en) | Semiconductor device | |
| JP3368629B2 (en) | Semiconductor device | |
| JP3394155B2 (en) | Metal thin film forming method | |
| JP2945010B2 (en) | Semiconductor device | |
| JPH0263168A (en) | Semiconductor device | |
| JP3823826B2 (en) | Manufacturing method of semiconductor device | |
| KR100415095B1 (en) | Method for manufacturing semiconductor device | |
| JPH03250627A (en) | Semiconductor device and manufacture thereof | |
| JPH03262125A (en) | Semiconductor device | |
| JPH01268150A (en) | Semiconductor device | |
| JPH04162531A (en) | Manufacture of semiconductor device | |
| KR100203303B1 (en) | Method of forming metal interconnection of semiconductor device | |
| JPH03175636A (en) | Semiconductor integrated circuit | |
| JPH04186729A (en) | Semiconductor device | |
| JPH0524672B2 (en) |