JPH02203620A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02203620A JPH02203620A JP1024561A JP2456189A JPH02203620A JP H02203620 A JPH02203620 A JP H02203620A JP 1024561 A JP1024561 A JP 1024561A JP 2456189 A JP2456189 A JP 2456189A JP H02203620 A JPH02203620 A JP H02203620A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- integrated circuit
- low
- power supply
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 101100102861 Homo sapiens VTI1B gene Proteins 0.000 description 1
- 102100023018 Vesicle transport through interaction with t-SNAREs homolog 1B Human genes 0.000 description 1
- 101150078795 Vti1a gene Proteins 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 101150049867 vti1 gene Proteins 0.000 description 1
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、動作電源電圧以下の低電圧印加状態におい
て、集積回路の出力端子を高電位ＶＯＯ又は低電圧ＶＳ
Ｓ側に接地させる出力ドライバー及びプリバッファ回路
を存する半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a method for connecting an output terminal of an integrated circuit to a high potential VOO or a low voltage VS in a low voltage application state below the operating power supply voltage.
The present invention relates to a semiconductor integrated circuit device including an output driver and a pre-buffer circuit that are grounded on the S side.
この発明は、半導体集積回路の製造工程において、出力
ドライバーの前段のバンファのシュレッ二ホールド電圧
のｖ、８（以下、ＶＴＨとかく。）を同一チップ内の同
型及び相反する型のトランジスタのＶＴＮより高いもの
に設定することにより動作電源電圧以下の低電圧印加状
態において、集積回路の出力端子を高電位■。、又は低
電位ＶＳＳ側に接地させることができるようにしたもの
である。In the manufacturing process of a semiconductor integrated circuit, this invention sets the threshold voltage v,8 (hereinafter referred to as VTH) of a bumper in the preceding stage of an output driver to be higher than the VTN of transistors of the same type and opposite type in the same chip. By setting the output terminal of the integrated circuit to a high potential when a low voltage below the operating power supply voltage is applied. , or can be grounded to the low potential VSS side.
従来、第２図に示すように分周回路りを出力させるため
にプリバッファＡと出力ドライバーＢとの間に抵抗Ｃを
挿入し、プリバッファＡのゲート電位に依存せず出力ド
ライバーＢのゲート電位を高電位Ｖｌｌｌｌ側に寄らせ
、動作電源電圧以下の低電圧印加状態において、集積回
路の出力を低電位ＶＳＳ側に接地させる回路が知られて
いた。Conventionally, as shown in Fig. 2, a resistor C is inserted between a pre-buffer A and an output driver B in order to output a frequency dividing circuit, and the gate potential of the output driver B is independent of the gate potential of the pre-buffer A. A circuit is known in which the potential is shifted to the high potential Vllll side, and the output of the integrated circuit is grounded to the low potential VSS when a low voltage lower than the operating power supply voltage is applied.
しかし、従来の技術の出力ドライバーＢとプリバッファ
Ａとの間に抵抗Ｃを挿入する方法は、動作電源電圧が高
くなるという欠点があった。この発明は、従来のこのよ
うな欠点を解決するために、動作電源電圧は、差はど高
くならず、動作電源電圧以下の低電圧印加状態において
、集積回路の出力端子を高電位■。又は低電位■３．側
に接地させることを目的としている。However, the conventional method of inserting a resistor C between the output driver B and the pre-buffer A has the disadvantage that the operating power supply voltage becomes high. In order to solve these conventional drawbacks, the present invention has been developed by applying a low voltage applied to the output terminal of an integrated circuit to a high potential (1) without increasing the operating power supply voltage by any significant difference. Or low potential■3. The purpose is to ground it to the side.
上記課題を解決するために、この発明は！Ｊ積回路の製
造工程において、出力ドライバーの前段のバッファの片
側のＶｔＨを同一チップ内の同型及び相反する型のトラ
ンジスタのＶＴＨより高いものにするようにした。In order to solve the above problems, this invention! In the manufacturing process of the J product circuit, the VtH of one side of the buffer at the front stage of the output driver is set to be higher than the VTH of transistors of the same type and opposite type in the same chip.
出力ドライバーの前段のバッファの片側のＶ、□を同一
チップ内の同型及び相反する型のトランジスタのＶＴＨ
よりも、高いＶＴＩ１を作製することにより、出力ドラ
イバーのゲート電位を高電位■。又は低電位ＶＳＳ側に
寄らせることにより、動作電源電圧以下の低電圧印加状
態において、集積回路の出力端子を高電位ＶＯＯ又は低
電位ＶＳＳ側に接地させることができる。V on one side of the buffer in front of the output driver, □ is the VTH of the same type and opposite type transistors in the same chip.
By creating a higher VTI1, the gate potential of the output driver is set to a higher potential. Alternatively, by bringing the output terminal closer to the low potential VSS side, the output terminal of the integrated circuit can be grounded to the high potential VOO or the low potential VSS side when a low voltage lower than the operating power supply voltage is applied.
〔実施例〕
この発明を第１図に示す回路ブロック図を基にして説明
する。[Example] The present invention will be explained based on the circuit block diagram shown in FIG.
第１図において、分周回路４を出力させるためにＮＭＯ
３２は、同一チップ内の同型トランジスタと同一の■□
８を利用し、ＰＭＯ３１は、同一チップ内の同型及び相
反するトランジスタのＶＡＮより高いｖｔｎのものを半
導体製造工程で作製する。In FIG. 1, in order to output the frequency divider circuit 4, the NMO
32 is the same type transistor in the same chip.
8, the PMO 31 is manufactured in a semiconductor manufacturing process with a vtn higher than the VAN of the same type and opposite transistors in the same chip.
動作電源電圧以下の低電圧印加状態においては、ＮＭＯ
３２とＰＭＯ３Ｉの両方とも、テーリング特性になって
いるが、ＮＭＯ３２に比べＰＭＯ３ｌＯ方がリークしな
いような高いＶＶ、ｌになっているので、ＰＭＯ３Ｉと
ＮＭＯ３２のゲート電位が高電圧Ｖ、側、低電圧ＶＳＳ
側に寄らず、出力ドライバーのグー１−電位はＶ。側に
寄っており、出力を低電位ＶＳＳ側に接地させることが
できる。動作電源電圧は、ＰＭＯ３ＩのＶＴＩ（を高く
したことにより、動作電源電圧は若干上昇するだけです
む。In a low voltage application state below the operating power supply voltage, NMO
Both PMO32 and PMO3I have tailing characteristics, but compared to NMO32, PMO31O has a higher VV and l to prevent leakage, so the gate potentials of PMO3I and NMO32 are on the high voltage V side and low voltage side. VSS
Without going to the side, the output driver's goo 1-potential is V. The output can be grounded to the low potential VSS side. By increasing the VTI of PMO3I, the operating power supply voltage only needs to rise slightly.
また、ＮＭＯ３２とＰＭＯ３Ｉを取り替えても、同様な
原理により、実施することができる。更に、分周回路４
の代わりにデコーダやエンコーダ等のデジタル回路に取
り替えても、同様な原理により実施することができる。Further, even if NMO32 and PMO3I are replaced, the same principle can be used. Furthermore, the frequency dividing circuit 4
Even if a digital circuit such as a decoder or an encoder is used instead, the same principle can be used.
以上説明したように、この発明は、若干動作電源電圧は
上昇するが、動作電源電圧以下の低電圧印加状態におい
て、集積回路の出力端子を高電位ＶＩＩＤ又は低電圧Ｖ
３Ｓ側に接地させる効果がある。As explained above, in the present invention, the output terminal of the integrated circuit is connected to the high potential VIID or the low voltage V in a low voltage application state below the operating power supply voltage, although the operating power supply voltage increases slightly.
This has the effect of grounding the 3S side.
第１図は本発明の動作確定回路のブロック図、第２図は
従来の動作確定回路のブロック図である。
１・・・ＰＭＯ３）ランジスタ
２・・・ＮＭＯ３）ランジスタ
３・・・出力ドライバー
４・・・分周回路
Ａ・・・出力ドライバー前段のドライバーＢ・・・出力
ドライバー
Ｃ・・・プリアップ抵抗
Ｄ・・・分周回路
以上
出願人 セイコー電子工業株式会社
代理人 弁理士 林 敬 之 助FIG. 1 is a block diagram of an operation determining circuit according to the present invention, and FIG. 2 is a block diagram of a conventional operation determining circuit. 1... PMO 3) Transistor 2... NMO 3) Transistor 3... Output driver 4... Frequency divider circuit A... Driver in front of output driver B... Output driver C... Pre-up resistor D ...For frequency dividing circuits and above Applicant: Seiko Electronic Industries Co., Ltd. Representative Patent attorney: Keinosuke Hayashi
Claims (1)
の出力端子を高電位又は低電位側に接地させる出力ドラ
イバー及びプリバッファ回路を有する半導体集積回路装
置。A semiconductor integrated circuit device having an output driver and a pre-buffer circuit that ground an output terminal of an integrated circuit to a high potential or a low potential side when a low voltage lower than an operating power supply voltage is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1024561A JPH02203620A (en) | 1989-02-02 | 1989-02-02 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1024561A JPH02203620A (en) | 1989-02-02 | 1989-02-02 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02203620A true JPH02203620A (en) | 1990-08-13 |
Family
ID=12141572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1024561A Pending JPH02203620A (en) | 1989-02-02 | 1989-02-02 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02203620A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6653693B1 (en) * | 1997-11-11 | 2003-11-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device |
-
1989
- 1989-02-02 JP JP1024561A patent/JPH02203620A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6653693B1 (en) * | 1997-11-11 | 2003-11-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device |
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