JPH02198166A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02198166A JPH02198166A JP1613289A JP1613289A JPH02198166A JP H02198166 A JPH02198166 A JP H02198166A JP 1613289 A JP1613289 A JP 1613289A JP 1613289 A JP1613289 A JP 1613289A JP H02198166 A JPH02198166 A JP H02198166A
- Authority
- JP
- Japan
- Prior art keywords
- region
- well region
- type
- semiconductor
- buried layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 description 26
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 230000010354 integration Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置に関し、特に、ｎチャネ
ルＭＩＳＦＥＴとｐチャネルＭＩＳＦＥＴを備えた半導
体集積回路装置に適用して有効な技術に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with an n-channel MISFET and a p-channel MISFET. be.
近年、半導体集積回路装置は、ｎｐｎ型バイポーラトラ
ンジスタと、ｐチャネルＭＩＳＦＥＴと、ｎチャネルＭ
ＩＳＦＥＴとで構成されるようになってきている。バイ
ポーラトランジスタがｎｐｎ型であるため、半導体基板
はｐ−型が用いられる。In recent years, semiconductor integrated circuit devices include npn-type bipolar transistors, p-channel MISFETs, and n-channel MISFETs.
It has come to be composed of ISFET. Since the bipolar transistor is an npn type, a p-type semiconductor substrate is used.
そして、前記ｐチャネルＭＩＳＦＥＴは、前記ｐ−型半
導体基板のｎ型ウェル領域に、ｎチャネルＭＩ ５ＦＥ
Ｔはｐ型ウェル領域に設けられる。また、ｐ型半導体領
域の下にはｐ゛型半導体領域（埋め込み層）が設けられ
、この下が半導体基板のｐ−型領域となっている。同様
に、前１！ｉｌ！ｎ型ウエル領域の下にはｎ゛型半導体
領域（埋め込み層）が設けられ。The p-channel MISFET includes an n-channel MISFET in an n-type well region of the p-type semiconductor substrate.
T is provided in the p-type well region. Further, a p-type semiconductor region (buried layer) is provided below the p-type semiconductor region, and the area below this is the p-type region of the semiconductor substrate. Similarly, previous 1! Il! An n' type semiconductor region (buried layer) is provided below the n type well region.
この下がｐ−型領域となっている。前記ｐ型ウェル領域
には接地電位Ｖｓｓを印加し、またｎ型ウエ層領域には
電源電位Ｖ ｃ ｃまたはそれ以下の電位（−１Ｖ〜−
３Ｖ）を印加して定電位にすることによって、それらの
表面のＭＩＳＦＥＴの動作の安定化を図る。ここで、前
記接地電位Ｖｓｓおよび電源電位ｖｃｃの給電方法であ
るが、前記ｐ型ウェル領域にはｐ−型半導体基板からｐ
゛型埋込み層を介して接地電位Ｖｓｓを給電することが
できるが、ｎ型ウェル領域にはｐ“型半導体基板から電
源電位Ｖ ｃ ｃを給電することがでない。そこで、ｐ
チャネルＭＩＳＦＥＴの周囲をざ型半導体領域で囲み、
これに半導体基板上の電源電位Ｖｃｃの配線（アルミニ
ウム膜）を接続するようにしている。Below this is a p-type region. A ground potential Vss is applied to the p-type well region, and a power supply potential Vcc or a lower potential (-1V to -
By applying 3V) to make the potential constant, the operation of the MISFETs on those surfaces is stabilized. Here, regarding the power supply method of the ground potential Vss and the power supply potential Vcc, the p-type well region is supplied with p-type from the p-type semiconductor substrate.
Although the ground potential Vss can be supplied through the ゛-type buried layer, it is not possible to supply the power supply potential Vcc from the p''-type semiconductor substrate to the n-type well region.
Surrounding the channel MISFET with a square-shaped semiconductor region,
A wiring (aluminum film) for power supply potential Vcc on the semiconductor substrate is connected to this.
このｎ゛型半導体領域は、ｎチャネルＭＩＳＦＥＴのソ
ース、ドレインを成すｎ゛型半導体領域と同一工程で形
成するため、深さの浅いものである。This n'-type semiconductor region is formed in the same process as the n'-type semiconductor regions forming the source and drain of the n-channel MISFET, and therefore has a shallow depth.
上述したようなバイポーラ−０ＭＯ８は、例えば、特願
昭６１−６５６９６号に記載されている。Bipolar-0MO8 as described above is described, for example, in Japanese Patent Application No. 61-65696.
本発明者は、前記ｎ型ウェル領域への電源電位Ｖｃｃの
給電方法について検討した結果１次の問題点を見出した
。The inventor of the present invention discovered the first problem as a result of studying the method of supplying the power supply potential Vcc to the n-type well region.
すなわち、前記ｎウェルの抵抗値は非常に高く、シート
抵抗で８００Ω／口程度である。このため。That is, the resistance value of the n-well is very high, and the sheet resistance is about 800Ω/hole. For this reason.
前記ｎウェル領域の表面にｐチャネルＭＩＳＦＥＴを囲
んで設けられるｎ′″型半導体領域の一辺の長さを５０
〜６０μｍ以上に長くしてしまうと、ｐチャネルＭＩＳ
ＦＥＴの動作に伴うｎ型ウェル領域の電位変動を抑える
ことが難しくなる。言い換えれば、ｎ−型ウェル領域の
ｐチャネルＭＩ Ｓ ＦＥＴの周りの電位が変動し易く
なる。ｎ型ウェルの電位が変動すると、ｐチャネルＭＩ
５ＦＥＴのドレインであるｐ・型半導体領域と、ｎ型
ウェル領域と、このｎ型ウェル領域に隣接しているｐ型
ウェル領域と、このｐ型ウェル領域の設けられているｎ
チャネルＭＩ ５ＦＥＴのドレイン領域であるざ型半導
体領域との間でラッチアップが起るという問題があった
。このラッチアップを防止するためには前記ｎ型ウェル
領域に電源電位を給電するためのｎ゛型半導体領域の一
辺を５０〜６０μｍ以下に短くすればよいのだか、そう
すると前記ｎ゛型半導体領域に要する領域が多くなり、
半導体集積回路装置の集積度が落ちていまうという問題
があった。The length of one side of the n''' type semiconductor region provided surrounding the p channel MISFET on the surface of the n well region is 50.
If the length is longer than ~60 μm, p-channel MIS
It becomes difficult to suppress potential fluctuations in the n-type well region due to the operation of the FET. In other words, the potential around the p-channel MISFET in the n-type well region tends to fluctuate. When the potential of the n-well changes, the p-channel MI
A p-type semiconductor region which is the drain of the 5FET, an n-type well region, a p-type well region adjacent to this n-type well region, and an n-type semiconductor region where this p-type well region is provided.
There was a problem in that latch-up occurred between the channel MI 5FET and the drain region of the square-shaped semiconductor region. In order to prevent this latch-up, is it sufficient to shorten one side of the n-type semiconductor region for supplying the power supply potential to the n-type well region to 50 to 60 μm or less? More space is required,
There has been a problem that the degree of integration of semiconductor integrated circuit devices is decreasing.
本発明の目的は、半導体集積回路装置の電気的信頼性を
向上し、また集積度を向上することにある。An object of the present invention is to improve the electrical reliability of a semiconductor integrated circuit device and also to improve the degree of integration.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体基板の主面にウェル領域を設け、該ウ
ェル領域にＭＩＳＦＥＴを設け、前記半導体基板の前記
ウェル領域の下に該ウェル領域より不純物濃度の高い埋
め込み層を設けた半導体集積回路装置において、前記ウ
ェル領域の前記Ｍ工５ＦＥＴと異る部分にその表面から
前記埋め込み層まで達する深さの深い定電位給電用半導
体領域を設けたものである。That is, in a semiconductor integrated circuit device, a well region is provided on the main surface of a semiconductor substrate, a MISFET is provided in the well region, and a buried layer having an impurity concentration higher than that of the well region is provided below the well region of the semiconductor substrate. A constant potential power supply semiconductor region having a deep depth reaching from the surface of the well region to the buried layer is provided in a portion of the well region that is different from the M-type 5FET.
上述した手段によれば、前記定電位給電用半導体領域か
ら抵抗値の低い埋め込み層に定電位が給電され、この埋
め込み層から前記ウェル領域全体に定電位が給電される
ので、前記ウェル領域の電位変動を抑性して半導体集積
回路装置の電気的信頼性を向上することができる。また
、前記定電位給電用半導体領域を数１００μｍごとに設
ければウェル領域の電位を充分定電位に保つことができ
るので、半導体集積回路装置の集積度を向上できる。According to the above-described means, a constant potential is supplied from the constant potential power supply semiconductor region to the buried layer having a low resistance value, and a constant potential is supplied from this buried layer to the entire well region, so that the potential of the well region is The electrical reliability of the semiconductor integrated circuit device can be improved by suppressing fluctuations. Furthermore, if the semiconductor regions for constant potential power supply are provided every several hundred micrometers, the potential of the well region can be kept sufficiently constant, so that the degree of integration of the semiconductor integrated circuit device can be improved.
以下、本発明の実施例■の半導体集積回路装置を図面を
用いて説明する。A semiconductor integrated circuit device according to Embodiment 2 of the present invention will be described below with reference to the drawings.
第１図は、本発明の半導体集積回路装置のｐチャネルＭ
ＩＳＦＥＴが設けられているｎ型ウェル領域の平面図、
第２図は、第１図に示した半導体集積回路装置の■−■
切断線における断面図である。FIG. 1 shows the p-channel M of the semiconductor integrated circuit device of the present invention.
A plan view of the n-type well region where the ISFET is provided, FIG. 2 is a plan view of the semiconductor integrated circuit device shown in FIG. 1.
FIG. 3 is a cross-sectional view taken along a cutting line.
なお、第１図は、半導体基板上の配線やｐチャネルＭＩ
ＳＦＥＴの構成を分り易くするため、層間絶縁膜を図示
していない。Note that FIG. 1 shows wiring on a semiconductor substrate and p-channel MI
In order to make the configuration of the SFET easier to understand, the interlayer insulating film is not shown.
第１図及び第２図において、１は単結晶シリコンからな
る半導体基板であり、１〜２μｍ程度の深さの所にｎ４
型埋め込み層２及びｐ゛型埋込み層４が設けられている
。これら埋め込み層２，４の下はｐ−型領域となってい
る。またｎ゛型埋込み層２の上はｎ−型ウェル領域３で
あり、ブ型埋め込み層４の上はｐ°型ウェル領域５であ
る。ｎ−型ウェル領域３に、薄い酸化シリコン膜（ゲー
ト絶縁膜）８と、ゲート電極（例えば多結晶シリコン膜
）９と、ｐ゛゛半導体領域１０とでＰチャネルＭＩＳＦ
ＥＴを構成している。７は酸化シリコン膜からなるフィ
ールド絶縁膜である。ｎ°型ウェル領域３にはその表面
からｎ４型埋め込み層２まで達する深さの深い定電位給
電用半導体領域（ざ型）６を設けている。ｎ゛型埋込み
層２はｎ−型ウェル領域３の下面の全面に設けられてい
る。また、定電位給電用半導体領域６はｐチャネルＭＩ
ＳＦＥＴを囲んで設けられている。ｎ°梨型定電位給電
半導体領域６及びｎ４型埋め込み層２の不純物濃度は、
ｎ−型ウェル領域３のそれより遥かに高く、抵抗値は非
常に小さくなっている。例えば、ｎ・型埋め込み層２の
シート抵抗は９０Ω／口程度である。１１は例えばＣＶ
Ｄによる酸化シリコン膜からなる層間絶縁膜である。１
２は層間絶縁膜１１を選択的に除去して形成した接続孔
である。 １３Ａ 、 １３Ｂ 、 １３Ｇ 、 １３
Ｄ 。In FIGS. 1 and 2, 1 is a semiconductor substrate made of single crystal silicon, and an n4
A type buried layer 2 and a p-type buried layer 4 are provided. Below these buried layers 2 and 4 is a p-type region. Further, above the n-type buried layer 2 is an n-type well region 3, and above the double-type buried layer 4 is a p-type well region 5. A P-channel MISF is formed by forming a thin silicon oxide film (gate insulating film) 8, a gate electrode (for example, a polycrystalline silicon film) 9, and a p' semiconductor region 10 in the n-type well region 3.
It constitutes ET. 7 is a field insulating film made of a silicon oxide film. The n° type well region 3 is provided with a deep constant potential power supply semiconductor region (shaped) 6 extending from the surface thereof to the n4 type buried layer 2 . The n-type buried layer 2 is provided on the entire lower surface of the n-type well region 3. Further, the constant potential power supply semiconductor region 6 is a p-channel MI
It is provided surrounding the SFET. The impurity concentration of the n° pear-shaped constant potential power supply semiconductor region 6 and the n4 type buried layer 2 is as follows:
The resistance value is much higher than that of the n-type well region 3, and the resistance value is very small. For example, the sheet resistance of the n-type buried layer 2 is about 90Ω/hole. 11 is, for example, CV
This is an interlayer insulating film made of a silicon oxide film made of D. 1
Reference numeral 2 denotes a connection hole formed by selectively removing the interlayer insulating film 11. 13A, 13B, 13G, 13
D.
１３Ｅ、１３Ｆは、アルミニウム膜からなる配線であり
、特に配線１３Ｆは電源電位Ｖｃｃ例えば５ｖを給電す
る配線である。この配線１３Ｆは、接続孔１２を通して
ｎ゛型型置電位給電用半導体領域６接続している。前記
ｎ゛梨型定電位給電半導体領域６は、前記配線１３Ｆと
ざ型埋め込み層２の間を接続するものである。ｐ−型半
導体領域５には、半導体基板（ｐ−領域）１からｐ゛型
埋込み層４を介して接地電位Ｖｓｓ例えばＯｖが印加さ
れる。13E and 13F are wirings made of an aluminum film, and in particular, the wiring 13F is a wiring for feeding a power supply potential Vcc, for example, 5V. This wiring 13F is connected to the n-type potential power supply semiconductor region 6 through the connection hole 12. The pear-shaped constant potential power supply semiconductor region 6 connects the wiring 13F and the pear-shaped buried layer 2. A ground potential Vss, for example Ov, is applied to the p-type semiconductor region 5 from the semiconductor substrate (p-region) 1 via the p'-type buried layer 4.
前記のように、ｎ゛型埋込み層２のシート抵抗が小さい
ため、ｐチャネルＭＩＳＦＥＴを囲んでいるｎ゛型型置
電位給電用半導体領域６一辺が数１００μｍ程度であっ
ても、ｎ−型ウェル領域３の電位を電源電位Ｖ ｃ ｃ
に固定しておくことができる。As mentioned above, since the sheet resistance of the n-type buried layer 2 is small, even if the side of the n-type potential power supply semiconductor region 6 surrounding the p-channel MISFET is about several hundred μm, the n-type well The potential of region 3 is set to the power supply potential V c c
It can be kept fixed.
前記第１図及び第２図に示した半導体基板１の前記ｎ−
型ウェル領域３と異る部分には第３１図に示すようなｎ
ｐｎ型バイポーラトランジスタが構成されている。The n− of the semiconductor substrate 1 shown in FIGS. 1 and 2
In the part different from the type well region 3, as shown in FIG.
A pn type bipolar transistor is configured.
第３図は、第１図及び第２図に示した半導体集積回路装
置と同一の半導体基板に構成されたバイポーラトランジ
スタの断面図である。FIG. 3 is a sectional view of a bipolar transistor constructed on the same semiconductor substrate as the semiconductor integrated circuit device shown in FIGS. 1 and 2.
第３図において、１４はｐ型ベース領域、１５はざ型エ
ミッタ領域である。ｎ−型ウェル領域３がコレクタ領域
となる。６はｎ′″型コレクチ引き出し領域である。こ
のｎ゛型コレクタ引き出し領域６と同一工程で、第１図
及び第２図に示したｎ゛型型置電位給電用半導体領域６
形成している。 １３Ｇ 、 １３Ｈ。In FIG. 3, 14 is a p-type base region, and 15 is a diagonal emitter region. The n-type well region 3 becomes a collector region. Reference numeral 6 denotes an n''' type collector lead-out region. In the same process as this n' type collector lead-out region 6, the n' type ground potential power supply semiconductor region 6 shown in FIGS. 1 and 2 is formed.
is forming. 13G, 13H.
１３Ｔはそれぞれアルミニウム膜からなる信号配線であ
る。13T are signal wirings each made of an aluminum film.
第４図は、本発明の実施例■の半導体集積回路装置のｐ
チャネルＭＩＳＦＥＴ及びｎチャネルＭＩＳＦＥＴが設
けられている領域の平面図である。FIG. 4 shows the p of the semiconductor integrated circuit device according to the embodiment
FIG. 3 is a plan view of a region where a channel MISFET and an n-channel MISFET are provided.
なお、第４図は、ＰチャネルＭＩＳＦＥＴ及びｎチャネ
ルＭＩＳＦＥＴに接続する信号配線を示していない。Note that FIG. 4 does not show signal wiring connected to the P-channel MISFET and the n-channel MISFET.
第４図において、ＱｐはｐチャネルＭＩＳＦＥＴ、Ｑｎ
はｎチャネルＭＩＳＦＥＴである。ｐチャネルＭＩＳＦ
ＥＴは、ゲート電極９と、ソース。In FIG. 4, Qp is a p-channel MISFET, Qn
is an n-channel MISFET. p-channel MISF
ET is a gate electrode 9 and a source.
ドレイン領域となるｐ°型半導体領域１６とゲート絶縁
膜（第２図参照）８とで構成されている。It is composed of a p° type semiconductor region 16 serving as a drain region and a gate insulating film (see FIG. 2) 8.
本実施例■の半導体集積回路装置は、第４図に示したよ
うに、ｎ°梨型定電位給電半導体領域６をｎ−型ウェル
領域３の両側部に延在させて設けている。ｎ゛型型置電
位給電用半導体領域６、第４図におけるＸ方向のみ設け
られており、−点鎖線で示したようなＹ方向に延在する
ｎ・型定電位給電用半導体領域６は設けていない。ｐチ
ャネルＭＩＳＦＥＴＱｐは、前記ｎ−型ウェル領域３に
設けられた２つのｎ゛型型置電位給電用半導体領域６間
に配置される。As shown in FIG. 4, the semiconductor integrated circuit device of the present embodiment (2) has n° pear-shaped constant potential power supply semiconductor regions 6 extending on both sides of the n − type well region 3. The n-type constant potential power supply semiconductor region 6 is provided only in the X direction in FIG. Not yet. The p-channel MISFET Qp is arranged between two n-type potential power supply semiconductor regions 6 provided in the n-type well region 3.
ｐチャネルＭＩＳＦＥＴのソース、ドレイン領域である
ざ型半導体領域１０とｎ−型ウェル領域３との間には接
合容量があり、この容量を介してｎ−型ウェル領域３が
ｐ゛゛半導体領域１０に接続されている（いわゆる容量
カップリング）。このため、ｐチャネルＭＩＳＦＥＴの
動作時には、ｎ−型ウェル領域３にノイズが発生するが
、ｎ４型埋め込み層２にｎ゛型型置電位給電用半導体領
域６接続し、またｎ・型定電位給電用半導体領域６に電
源電位Ｖｃｃの配線（図示していない）が接続されるた
め、前記ｎ“型ウェル領域３に発生するノイズを非常に
小さくできる。There is a junction capacitance between the p-type semiconductor region 10, which is the source and drain region of the p-channel MISFET, and the n-type well region 3, and the n-type well region 3 is connected to the p゛゛ semiconductor region 10 via this capacitance. connected (so-called capacitive coupling). Therefore, during operation of the p-channel MISFET, noise is generated in the n-type well region 3, but the n-type constant potential power supply semiconductor region 6 is connected to the n4-type buried layer 2, and the n-type constant potential power supply semiconductor region 6 is connected to the n4-type buried layer 2. Since a wiring (not shown) for the power supply potential Vcc is connected to the semiconductor region 6, the noise generated in the n'' type well region 3 can be made very small.
ここで、第５図に、第４図に示されたｎ−型ウェル領域
３のカップリングノイズ特性を示す。Here, FIG. 5 shows the coupling noise characteristics of the n-type well region 3 shown in FIG. 4.
第５図は、ｎ−型ウェル領域３に１００μｍの間隔で２
つのｎ゛型型置電位給電用半導体領域６平行に設け、そ
れらの間にｐ４型型半体領域（ｐ”型半導体領域１０に
当る）を設け、そして、前記ｎ゛現型定電位給電半導体
領域６に電位７ｖを印加した状態で、前記ｐ゛゛半導体
領域に印加する電圧を７ｖからＯｖに変化させたときに
ｎ−型ウェル領域３に発生するカップリングノイズを解
析した（このデータは実測ではありません）ものである
。カップリングノイズが０．７ｖ以上の領域が、ラッチ
アップの発生する確率が非常に高いラッチアップ危険領
域である。In FIG. 5, two
Two n゛ type constant potential power supply semiconductor regions 6 are provided in parallel, a p4 type half region (corresponding to the p'' type semiconductor region 10) is provided between them, and the n゛ current constant potential power supply semiconductor The coupling noise generated in the n-type well region 3 was analyzed when the voltage applied to the P゛゛ semiconductor region was changed from 7V to Ov with a potential of 7V applied to the region 6 (this data is based on actual measurements). The area where the coupling noise is 0.7V or more is the latch-up danger area where the probability of latch-up occurring is extremely high.
第５図に示したように、Ｙ方向のｎ・型定電位給電用半
導体領域６（第４図の一点鎖線で示されたもの）の間隔
が、２５０μｍ程度まではｎ°型ウェル領域３に発生す
るカップリングノイズの電位がしだいに大きくなるが、
２５０μｍ以上では増加が止まり、０．３Ｖ程度で一定
となる。すなわち、−点鎖線で示したようなＹ方向のｎ
゛型型置電位給電用半導体領域６設けずとも、Ｘ方向に
平行に延在するｎ・型定電位給電用半導体領域６があれ
ば、ｎ°型ウェル領域３のカップリングノイズを良好に
抑えることができる。このことから、Ｙ方向のｎ゛型型
置電位給電用半導体領域６要する領域が不要となる。As shown in FIG. 5, if the distance between the n-type constant potential power supply semiconductor regions 6 (indicated by the dashed line in FIG. 4) in the Y direction is about 250 μm, the n°-type well region 3 The potential of the coupling noise generated gradually increases,
At 250 μm or more, the increase stops and becomes constant at about 0.3V. In other words, n in the Y direction as shown by the -dotted chain line
Even if the ゛ type constant potential power supply semiconductor region 6 is not provided, if there is an n type constant potential power supply semiconductor region 6 extending parallel to the X direction, the coupling noise of the n° type well region 3 can be suppressed well. be able to. Therefore, the area required for the n-type potential power supply semiconductor region 6 in the Y direction becomes unnecessary.
以上の説明から分るように、半導体基板１の主面にウェ
ル領域３を設け、該ウェル領域３にＭＩＳＦＥＴを設け
、前記半導体基板１の前記ウェル領域３の下に前ウェル
領域３より不純物濃度の高い埋め込み層２を設けた半導
体集積回路装置において、前記ウェル領域３の前記ＭＩ
ＳＦＥＴと異る部分にその表面から前記埋め込み層まで
達する深さの深い定電位給電用半導体領域６゛を設けた
ことより、前記定電位給電用半導体領域６から抵抗値の
低い埋め込み層２に定電位が給電され、この埋め込み層
２から前記ウェル領域３全体に定電位（Ｖｃｃ）が給電
されるので、前記ウェル領域３の電位変動を伸性して半
導体集積回路装置の電気的信頼性を向上することができ
る。また、前記定電位給電用半導体領域６を数１００μ
ｍごとに設ければウェル領域３の電位を充分定電位に保
つことができるので、定電位給電用半導体領域６の領域
が小さくなり半導体集積回路装置の集積度を向上できる
。As can be seen from the above description, a well region 3 is provided on the main surface of the semiconductor substrate 1, a MISFET is provided in the well region 3, and an impurity concentration higher than that of the previous well region 3 is provided below the well region 3 of the semiconductor substrate 1. In a semiconductor integrated circuit device provided with a buried layer 2 having a high
By providing a deep constant potential power supply semiconductor region 6' extending from the surface of the SFET to the buried layer in a portion different from the SFET, it is possible to connect the constant potential power supply semiconductor region 6 to the buried layer 2 having a low resistance value. Since a constant potential (Vcc) is supplied from this buried layer 2 to the entire well region 3, potential fluctuations in the well region 3 are stretched and the electrical reliability of the semiconductor integrated circuit device is improved. can do. In addition, the semiconductor region 6 for constant potential power supply is several hundred microns thick.
If the well region 3 is provided every m, the potential of the well region 3 can be kept sufficiently constant, so that the area of the constant potential power supply semiconductor region 6 can be reduced, and the degree of integration of the semiconductor integrated circuit device can be improved.
以上、本発明を実施例にもとづき具体的に説明したが１
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
は言うまでもない。The present invention has been specifically described above based on examples, but 1.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
半導体集積回路装置の電気的信頼性を向上し、また集積
度を向上することができる。The electrical reliability of the semiconductor integrated circuit device can be improved, and the degree of integration can also be improved.
第１図は、本発明の半導体集積回路装置のｐチャネルＭ
ＩＳＦＥＴが設けられているｎ型ウェル領域の平面図、
第２図は、第１図に示した半導体集積回路装置の■−■
切断線における断面図、
第３図は、第１図及び第２図に示した半導体集積回路装
置と同一の半導体基板に構成されたバイポーラトランジ
スタの断面図、
第４図は、本発明の実施例■の半導体集積回路装置のｐ
チャネルＭＩＳＦＥＴ及びｎチャネルＭＩＳＦＥＴが設
けられている領域の平面図第５図は、第４図に示された
ｎ−型ウエル領域３のカップリングノイズ特性を示した
グラフである。
１・・・半導体基板、２，４・・・埋め込み層、３，５
・・・ウェル領域、６・・・定電位給電用半導体領域、
１０・・・ｐ゛型ソースドレイン領域、１４・・・ｐ型
ベース領域。
１５・・・ｎ３型エミツタ領域、１６・・・ｎ◆型ソー
スドレイン領域。FIG. 1 shows the p-channel M of the semiconductor integrated circuit device of the present invention.
A plan view of the n-type well region where the ISFET is provided, FIG. 2 is a plan view of the semiconductor integrated circuit device shown in FIG. 1.
3 is a sectional view of a bipolar transistor configured on the same semiconductor substrate as the semiconductor integrated circuit device shown in FIGS. 1 and 2; FIG. 4 is an embodiment of the present invention; FIG. ■ p of semiconductor integrated circuit device
FIG. 5, which is a plan view of the region where the channel MISFET and the n-channel MISFET are provided, is a graph showing the coupling noise characteristics of the n-type well region 3 shown in FIG. 4. 1... Semiconductor substrate, 2, 4... Buried layer, 3, 5
... Well region, 6... Semiconductor region for constant potential power supply,
10...p type source/drain region, 14...p type base region. 15...n3 type emitter region, 16...n◆ type source/drain region.
Claims (1)
域にＭＩＳＦＥＴを設け、前記半導体基板の前記ウェル
領域の下に該ウェル領域より不純物濃度の高い埋め込み
層を設けた半導体集積回路装置において、前記ウェル領
域の前記ＭＩＳＦＥＴと異る部分にその表面から前記埋
め込み層まで達する深さの深い定電位給電用半導体領域
を設けたことを特徴とする半導体集積回路装置。 ２、前記定電位給電用半導体領域は、前記半導体基板の
前記ウェル領域と異る領域に設けられているｎｐｎバイ
ポーラトランジスタのコレクタ引き出し層と同じ工程で
形成したものであることを特徴とする特許請求の範囲第
１項記載の半導体集積回路装置。[Claims] 1. A well region is provided on the main surface of a semiconductor substrate, a MISFET is provided in the well region, and a buried layer having a higher impurity concentration than the well region is provided below the well region of the semiconductor substrate. A semiconductor integrated circuit device, characterized in that a constant potential power supply semiconductor region having a deep depth reaching from the surface of the well region to the buried layer is provided in a portion of the well region that is different from the MISFET. 2. A patent claim characterized in that the constant potential power supply semiconductor region is formed in the same process as a collector lead-out layer of an NPN bipolar transistor provided in a region different from the well region of the semiconductor substrate. The semiconductor integrated circuit device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1613289A JPH02198166A (en) | 1989-01-27 | 1989-01-27 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1613289A JPH02198166A (en) | 1989-01-27 | 1989-01-27 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02198166A true JPH02198166A (en) | 1990-08-06 |
Family
ID=11907967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1613289A Pending JPH02198166A (en) | 1989-01-27 | 1989-01-27 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02198166A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06204411A (en) * | 1993-01-06 | 1994-07-22 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor device and manufacture thereof |
-
1989
- 1989-01-27 JP JP1613289A patent/JPH02198166A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06204411A (en) * | 1993-01-06 | 1994-07-22 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor device and manufacture thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6828638B2 (en) | Decoupling capacitors for thin gate oxides | |
| US7777294B2 (en) | Semiconductor device including a high-breakdown voltage MOS transistor | |
| KR920003676B1 (en) | Semiconductor device | |
| JP2001352077A (en) | Soi field effect transistor | |
| KR20040081055A (en) | Semiconductor device | |
| JP4864344B2 (en) | Semiconductor device | |
| US4893164A (en) | Complementary semiconductor device having high switching speed and latchup-free capability | |
| JP5079974B2 (en) | Semiconductor device | |
| EP0037103B1 (en) | Semiconductor device | |
| JPH02198166A (en) | Semiconductor integrated circuit device | |
| JP2825038B2 (en) | Semiconductor device | |
| JPH08162539A (en) | Data output buffer | |
| JP2555890B2 (en) | Input protection device for semiconductor integrated circuit | |
| JP4787554B2 (en) | I / O circuit device | |
| KR100308074B1 (en) | Integrated circuit | |
| KR100332473B1 (en) | Semiconductor device and device isolation method using it | |
| JPH02214164A (en) | Mosfet with input protection circuit | |
| JPH01273346A (en) | Semiconductor device | |
| JPH09191054A (en) | Cmos transistor | |
| JPS62211945A (en) | Semiconductor device | |
| JP2585633B2 (en) | Semiconductor device | |
| JPH04239763A (en) | Output buffer | |
| JPH04359473A (en) | Insulation gate type field effect transistor | |
| JPS61208863A (en) | Cmos semiconductor device | |
| JPH0548015A (en) | Semiconductor device |