JPH02196222A - Production of active matrix substrate - Google Patents
Production of active matrix substrateInfo
- Publication number
- JPH02196222A JPH02196222A JP1015402A JP1540289A JPH02196222A JP H02196222 A JPH02196222 A JP H02196222A JP 1015402 A JP1015402 A JP 1015402A JP 1540289 A JP1540289 A JP 1540289A JP H02196222 A JPH02196222 A JP H02196222A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- layer
- substrate
- photoresist
- active matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 74
- 239000011159 matrix material Substances 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 55
- 239000012212 insulator Substances 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000012780 transparent material Substances 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 abstract description 17
- 238000002161 passivation Methods 0.000 abstract description 14
- 238000000059 patterning Methods 0.000 abstract description 6
- 230000007423 decrease Effects 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 11
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 239000010409 thin film Substances 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ZVNPWFOVUDMGRP-UHFFFAOYSA-N 4-methylaminophenol sulfate Chemical compound OS(O)(=O)=O.CNC1=CC=C(O)C=C1.CNC1=CC=C(O)C=C1 ZVNPWFOVUDMGRP-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 206010011732 Cyst Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 244000171726 Scotch broom Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、映像表示用液晶テレビやコンピコ、−夕端末
用デイスプレイ等で用いられる表示装置などに用いられ
るアクティブマトリクス基板の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing an active matrix substrate used in display devices used in liquid crystal televisions for video display, displays for computer terminals, etc.
従来の技術
近年、表示装置への応用を中心としで、透光性基板」二
に薄膜トランジスタ（以下ＴＰＴと略称する）を形成す
るアクティブマトリクス基板の開発が活発である。この
様なアクティブマトリクス基板の構成を第４図を用いて
説明する。ｌは透光性基板（図示せず）」二に形成した
多結晶シリコン或は非晶質シリコンを一構成要素とする
ＴＦＴ、２はＴＦＴ １のドレイン電極に電気的に接続
した透明電極と、カラーフィルターを形成する透光性基
板上の透明な対向電極との間に液晶を注入した液晶表示
体である。この液晶表示体２は映像表示領域３の各画素
と対応する位置に設置されており、液晶による静電容気
以外に、補助容量としてアクティブマトリクス基板に形
成される容量が付加されることもある。４はＴＦＴ １
のゲート電極に接続したゲート配線、５はＴＦＴ １の
ソース電極に接続したソース配線である。2. Description of the Related Art In recent years, active matrix substrates in which thin film transistors (hereinafter abbreviated as TPT) are formed on a transparent substrate have been actively developed mainly for application to display devices. The structure of such an active matrix substrate will be explained using FIG. 4. 1 is a TFT whose constituent element is polycrystalline silicon or amorphous silicon formed on a transparent substrate (not shown); 2 is a transparent electrode electrically connected to the drain electrode of TFT 1; This is a liquid crystal display in which liquid crystal is injected between a transparent counter electrode on a light-transmitting substrate that forms a color filter. This liquid crystal display body 2 is installed at a position corresponding to each pixel in the image display area 3, and in addition to the electrostatic capacitance provided by the liquid crystal, a capacitance formed on an active matrix substrate may be added as an auxiliary capacitance. 4 is TFT 1
A gate wiring 5 is connected to the gate electrode of the TFT 1, and a source wiring 5 is connected to the source electrode of the TFT 1.
上記のようなアクティブマトリクス基板の一構成要素で
あるＴＰＴの構成の一例を第５図を用いて以下に説明す
る。第５図（ａ）は−個の逆スタガ構造を有するＴＰＴ
の平面図であり、第５図（ｂ）は第５図（ａ）のＡ−Ｂ
線断面図である。An example of the structure of TPT, which is one component of the above active matrix substrate, will be described below with reference to FIG. Figure 5(a) shows a TPT with - inverted staggered structure.
FIG. 5(b) is a plan view taken along A-B in FIG. 5(a).
FIG.
６はガラスよりなる透光性基板であり、７はゲート電極
である。９，１０．１１は各々ゲート絶縁体層、第１の
半導体層、パッシベイション層である。８はゲート電極
７と絵素電極１７との接続を防止し、またゲート絶縁体
層９と絵素電極１７との密着性を向上させるための酸化
シリコン層である。１５及び１６は、各々ドレイン電極
及びソース電極である。１２は第１の半導体層ｌＯとド
レイン電極１５及びソース電極１６とのオーミック接触
を取るための第２の半導体層である。なお、この例では
絵素電極１７はゲート絶縁体Ｎ９の下に形成したが、絵
素電極１７は半導体層を島状に形成した後にドレイン電
極１５及びソース電極１６と同時に一体化して形成する
場合もある。6 is a transparent substrate made of glass, and 7 is a gate electrode. 9, 10, and 11 are a gate insulator layer, a first semiconductor layer, and a passivation layer, respectively. 8 is a silicon oxide layer for preventing the connection between the gate electrode 7 and the picture element electrode 17 and for improving the adhesion between the gate insulator layer 9 and the picture element electrode 17. 15 and 16 are a drain electrode and a source electrode, respectively. Reference numeral 12 denotes a second semiconductor layer for making ohmic contact between the first semiconductor layer IO and the drain electrode 15 and source electrode 16. In this example, the picture element electrode 17 is formed under the gate insulator N9, but the picture element electrode 17 may be formed simultaneously with the drain electrode 15 and the source electrode 16 after forming the semiconductor layer into an island shape. There is also.
このようなアクティブマトリクス基板を用いた表示装置
を第６図を用いて以下に説明する。対向透明電極１８を
′ｍ弄した対向基板１９とＬ記アク：ｉ−イブマトリク
ス基板との間には、ねじれ配向処理を１．／た’Ｉ’Ｎ
（ツイストネマティック）液晶２゜が封入され、さらに
二つの透光性基板の一方の面には、各々偏光板が貼られ
表示装置となる。A display device using such an active matrix substrate will be described below with reference to FIG. A twist alignment treatment is applied between the counter substrate 19 on which the counter transparent electrode 18 is twisted and the L matrix substrate. /ta'I'N
(Twisted nematic) liquid crystal 2° is sealed, and a polarizing plate is pasted on one side of each of the two translucent substrates to form a display device.
発明が解決しようとする課題
Ｆ−記のようなアクティブマトリクス基板を製造するに
は、５〜６枚のフォトリソグラフィイエ程を必要とし、
各を程ごとにマスクを用意することが必要となる。表示
装置用アクティブマトリクス基板の製造には、微細加工
が求められるため半導体プロセス用のものと同レベルの
性能を有する露光機や位置合わせ機構等の１４帯設備が
用いられる。Problem to be Solved by the Invention F - To manufacture an active matrix substrate as described above, 5 to 6 photolithography steps are required,
It is necessary to prepare a mask for each procedure. The manufacture of active matrix substrates for display devices requires microfabrication, so 14-zone equipment such as exposure machines and alignment mechanisms, which have the same level of performance as those for semiconductor processing, is used.
従っ−Ｃ、マスクを使用するフォトリソグラフィイエ程
の回数が多いほど、高性能かつ高価な露光機を使用する
回数が増えるため、アクティブマトリクス基板のコスト
が高くなる。また、フォトリソグラフィイエ程の回数が
多いほど、アライメントミスなどフォトリソグラフィイ
エ程に伴う不良が発生し歩留まりも低下する。さらにア
クティブマトリクス基板の主要構成要素であるＴＰＴを
露光機の性能に伴うマスク合わせ精度に基づき設計する
場合、フォトマスクを多く使うほど素子サイズが大きく
なる傾向があり、間口率（有効表示領域の割合）の減少
を招きアクティブマトリクス基板の高密度化への障害と
なっていたり、或は、画素間の特性ばらつきを大きくす
る原因となっていた。Therefore, the more times a mask is used in photolithography, the more times a high-performance and expensive exposure machine is used, which increases the cost of the active matrix substrate. Furthermore, the more times the photolithography process is performed, the more defects associated with the photolithography process, such as alignment errors, occur and the yield decreases. Furthermore, when designing TPT, which is a main component of an active matrix substrate, based on the mask alignment accuracy associated with the performance of the exposure machine, the element size tends to increase as more photomasks are used. ), which becomes an impediment to increasing the density of the active matrix substrate, or causes an increase in variations in characteristics between pixels.
本発明は上記課題に鑑み、マスクの精密な位置合わせを
必要とするフォトリソグラフィイエ程を削減して、より
安価なアクティブマトリクス基板の製造方法を提供し、
また、素子サイズを小さくし、アクティブマトリクス基
板の高密度化あるいは性能を向上する製造方法を提供す
ることを特徴とする。In view of the above problems, the present invention provides a method of manufacturing an active matrix substrate at a lower cost by reducing the number of photolithography steps that require precise alignment of masks.
Another feature of the present invention is to provide a manufacturing method that reduces the element size and increases the density or performance of an active matrix substrate.
課題を解決するための手段
本発明は、透光性基板上に、前記基板表面の特定領域を
覆う不透光性材料からなるゲート電極と、前記基板表面
の露出面及びゲート電極を覆う第１の絶縁体層と、前記
第１の絶縁体層上の特定領域を覆う半導体層と、前記半
導体層上の特定領域を覆う第２の絶縁体層（パッシベイ
ション層）と、前記半導体層のソース電極及びドレイン
電極とを順次形成するアクティブマトリクス基板の製造
方法において、前記第２の絶縁体層を形成する工程が、
前記第１の絶縁体層上に半導体層と第２の絶縁体層を被
着する工程と、前記第２の絶縁体層上にポジ型フォトレ
ジストを塗着する工程と、前記基板裏面から光照射する
工程と、前記フォトレジストを現像する工程と、前記現
像されたフォトレジストを用いて前記第２の絶縁体層を
食刻する工程とからなることを特徴とすることである。Means for Solving the Problems The present invention provides a gate electrode made of a non-transparent material that covers a specific area of the surface of the substrate, and a first gate electrode that covers the exposed surface of the substrate surface and the gate electrode. an insulator layer, a semiconductor layer covering a specific region on the first insulator layer, a second insulator layer (passivation layer) covering a specific region on the semiconductor layer, and a semiconductor layer covering a specific region on the semiconductor layer; In the method for manufacturing an active matrix substrate in which a source electrode and a drain electrode are sequentially formed, the step of forming the second insulator layer comprises:
A step of depositing a semiconductor layer and a second insulator layer on the first insulator layer, a step of coating a positive photoresist on the second insulator layer, and a step of applying light from the back side of the substrate. The method is characterized by comprising the steps of irradiating the photoresist, developing the photoresist, and etching the second insulator layer using the developed photoresist.
あるいは、透光性基板上に、前記基板表面の特定領域を
覆う不透光性材料からなるゲート電極と、前記基板表面
の露出面及びゲート電極を覆う第１の絶縁体層と、前記
第１の絶縁体層上の特定領域を覆う半導体層と、前記半
導体層のソース電極及びドレイン電極とを順次形成する
アクティブマトリクス基板の製造方法において、前記半
導体層を形成する工程が、前記第１の絶縁体層上に半導
体層を被着する工程と、前記半導体層上にポジ型フォト
レジストを塗着する工程と、前記基板裏面から光照射す
る工程と、前記フォトレジストを現像する工程と、前記
現像されたフォトレジストの無い領域の前記半導体層に
キャリア発生源となる元素を注入する工程と前記半導体
層を食刻する工程からなることを特徴とすることである
。Alternatively, a gate electrode made of a non-transparent material that covers a specific region of the substrate surface, a first insulator layer that covers the exposed surface of the substrate surface and the gate electrode, and a first In the method for manufacturing an active matrix substrate, the step of forming the semiconductor layer includes sequentially forming a semiconductor layer covering a specific region on the first insulating layer, and a source electrode and a drain electrode of the semiconductor layer. a step of depositing a semiconductor layer on the body layer; a step of applying a positive photoresist on the semiconductor layer; a step of irradiating light from the back side of the substrate; a step of developing the photoresist; and a step of developing the photoresist. The present invention is characterized in that it comprises a step of implanting an element serving as a carrier generation source into the semiconductor layer in a region where there is no photoresist, and a step of etching the semiconductor layer.
作用
本発明は上述の方法により、ゲート電極をフォトマスク
の代わりとしたフォトリソグラフィが可能となり、第２
の絶縁体層（パッシベイション層）や半導体層を形成す
る際に、位置合わせ機能等の不要な、より安価な露光機
を使用することができ、さらにはフォトリソグラフィ工
程の回数を削減することも可能となり、アクティブマト
リクス基板の低コスト化及び高歩留まり化を図ることが
できる。またＴＰＴの小型化も可能となり高開口率ある
いは高密度のアクティブマトリクス基板の実現や性能の
向上を図ることができる。Function The present invention enables photolithography using the gate electrode as a photomask by the method described above, and the second
When forming insulator layers (passivation layers) and semiconductor layers, a cheaper exposure machine that does not require alignment functions can be used, and the number of photolithography steps can be reduced. This also makes it possible to reduce the cost and increase the yield of the active matrix substrate. Further, it is possible to downsize the TPT, and it is possible to realize an active matrix substrate with a high aperture ratio or high density, and to improve performance.
実施例
以下、本発明の実施例を図面を参照して説明す実施例１
第１図は、本発明の第１の実施例を工程を追って図示し
たものである。第５図と同一目的で同様の構成のものに
は同一符号を記している。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. Example 1 FIG. 1 shows a first example of the present invention step by step. Components having the same purpose and structure as in FIG. 5 are designated by the same reference numerals.
透光性基板６上に、導電体薄膜であるＣ「をスパッタリ
ング法により被着し、所望のパターニングを施してゲー
ト電極７とする（第１図（ａ））。A conductive thin film C' is deposited on the transparent substrate 6 by sputtering and patterned in a desired manner to form the gate electrode 7 (FIG. 1(a)).
プラズマＣＶＤ法により、ゲート絶縁体層（第１の絶縁
体層：膜厚４００ｎｍの窒化シリコン）９、第１の半導
体層（膜厚５０ｎｍの非晶質シリコン）１０及びパッシ
ベイション層（第２の絶縁体層；膜厚９０ｎｍの窒化シ
リコン）Ｉｆを順次−様に被着する（第１図（ｂ））。A gate insulator layer (first insulator layer: silicon nitride with a thickness of 400 nm) 9, a first semiconductor layer (amorphous silicon with a thickness of 50 nm) 10, and a passivation layer (second (FIG. 1(b)).
この後ポジ型フォトレジスト２１を塗着し、レジストを
プリベーク後、ゲート電極７をマスクとして透光性基板
６の裏面より紫外光２２を照射する（第１図（ｃ））、
上記基板を現像すると、ゲート電極７に対応する部分以
外のレジストは除去される（第１図（ｄ）；実際にはゲ
ート電極の幅よりも極僅かな量２３だけレジストのパタ
ーンが細くできあがる）。このレジストをエツチングマ
スクとしてパッシベイション層１１を食刻する（第１図
（ｅ））。この後レジストを除去した後、第２の半導体
７５（膜厚２Ｏｎｍの不純物として燐を含んだ非晶質シ
リコン）１２を被着する（第１図（ｆ））。この徒弟１
と第２の半導体層を所望の形状にパターン形成グを施し
た後、透明導電膜（ＩＴＯ）よりなる＃膜を被着し、バ
ターニングして、ドレイン電極１５とソース電極ｉ６及
び絵素電極１７を形成する。さらに透明導電膜に覆われ
Ｃいない部分の第２の半導体層をエツチング液で除去し
てアクティブマトリクス基板が完成するく第１図（ｇ）
）。After that, a positive photoresist 21 is applied, and after prebaking the resist, ultraviolet light 22 is irradiated from the back surface of the transparent substrate 6 using the gate electrode 7 as a mask (FIG. 1(c)).
When the above substrate is developed, the resist other than the portion corresponding to the gate electrode 7 is removed (FIG. 1(d); in reality, the resist pattern is made thinner by an extremely small amount 23 than the width of the gate electrode). . The passivation layer 11 is etched using this resist as an etching mask (FIG. 1(e)). After removing the resist, a second semiconductor 75 (amorphous silicon containing phosphorus as an impurity with a thickness of 2 Onm) 12 is deposited (FIG. 1(f)). This apprentice 1
After patterning the second semiconductor layer into a desired shape, a # film made of a transparent conductive film (ITO) is deposited and patterned to form the drain electrode 15, source electrode i6, and pixel electrode. form 17. Furthermore, the portions of the second semiconductor layer covered with the transparent conductive film that are not covered by C are removed using an etching solution to complete the active matrix substrate (Figure 1 (g)).
).
以−Ｌ本実施例に示したように、パッシベイション層１
１をパターン形成する際に、ゲート電極７をマスクとし
てフォトリソグラフィ法を行なうことにより、位置合わ
せ機構等の不用な安価な露光機を使用することができ、
またフォトリソグラフィの回数を削減することが可能と
なる。またＴＰＴの小型化も可能となり高開口率あるい
は高密度のアクティブマトリクス基板の実現や性能の向
（。As shown in this example, the passivation layer 1
When patterning 1, by performing photolithography using the gate electrode 7 as a mask, it is possible to use an inexpensive exposure machine that does not require an alignment mechanism, etc.
Furthermore, the number of photolithography operations can be reduced. It also becomes possible to miniaturize the TPT, realizing active matrix substrates with high aperture ratios or high density, and improving performance.
を図ることができる。can be achieved.
実施例２
第２図は、本発明の第２の実施例を工程を追って図示し
たものである。第１図と同一［１的で同様の構成のもの
には同一符号を記している。Embodiment 2 FIG. 2 shows a second embodiment of the present invention step by step. Same as FIG. 1 [Identical and similar configurations are denoted by the same reference numerals.
透光性基板６」−に、導電体薄膜であるＣ「をスパッタ
リング法により被着し、所望のバターニングを施Ｉ）て
ゲート電極７とする（第２図（ａ））−プラズマＣＶＤ
法により、グー１縁体層（第１の絶縁体層：膜厚４０
Ｏｎｒｎの窒化シリコン）９、半導体層（膜厚５０口ｍ
の非晶質シリコン）１０□及びパッシベイション層を順
次−様に被着する（第２図（ｂ））。この後ポジ型フォ
トレジスト２１を塗表し、レジストをプリベーク後、ゲ
ート電極７をマスクとして透光性基板６の裏面より紫外
光２２を照射する（第２図（Ｃ））。上記基板を現像す
ると、ゲート電Ｖｆｉ７に対応する部分以外の１ノジス
トは除去される（第２図（ｄ）；実際にはゲト電極の幅
よりも極僅かな量２：（だけレジストのパターンが細く
できあがる）、、この１ノジストをマスクとしてフォト
１ノジストの無い領域の半導体層にキャリア発生源とな
る元素を注入する（第２図（ｅ）：プラズマドーピング
法、またはイオン注入法を使用）。この後基板にベーキ
ングを行い被着面積を増加したフォトレジスト２１ａを
用いて半導体層を食刻する（第２図（ｆ）；このとき食
刻された半導体層の両わきにドーピングされた領域１０
ｂが残る。もちろんこの工程用に新たにフォトｌ／シス
トを形成しなおしてもよい）。この後レジストを除去１
ノた後、透明導電膜（ＩＴＯ）よりなる薄膜を被着し、
バターニングして、ドレイン電極１５とソース電極１６
及び絵素電極１７を形成する。さらにバターニングされ
た透明導電膜に覆われていない部分のドーピングされた
半導体層をエツチング液で除去してアクティブマトリク
ス基板が完成する（第２図（ｇ））。A conductive thin film C is deposited on a transparent substrate 6 by sputtering and subjected to desired patterning to form a gate electrode 7 (FIG. 2(a)) by plasma CVD.
By the method, the Goo 1 edge layer (first insulator layer: film thickness 40
Onrn silicon nitride) 9, semiconductor layer (film thickness 50 m)
10 □ of amorphous silicon) and a passivation layer are sequentially deposited (FIG. 2(b)). Thereafter, a positive photoresist 21 is applied, and after prebaking the resist, ultraviolet light 22 is irradiated from the back surface of the transparent substrate 6 using the gate electrode 7 as a mask (FIG. 2(C)). When the above substrate is developed, one part of the resist other than the part corresponding to the gate electrode Vfi7 is removed (Fig. 2(d); in reality, the resist pattern is removed by an extremely small amount 2:() than the width of the gate electrode. Using this Nodist as a mask, an element to be a carrier generation source is implanted into the semiconductor layer in the area where there is no Photonist (FIG. 2(e): Plasma doping or ion implantation is used). After that, the semiconductor layer is etched using a photoresist 21a whose adhesion area has been increased by baking the substrate (FIG. 2(f); at this time, doped regions 10 are formed on both sides of the etched semiconductor layer.
b remains. Of course, a new photol/cyst may be formed for this step). After this, remove the resist 1
After that, a thin film made of transparent conductive film (ITO) is applied,
After patterning, drain electrode 15 and source electrode 16
and a picture element electrode 17 is formed. Furthermore, the portions of the doped semiconductor layer that are not covered by the patterned transparent conductive film are removed using an etching solution to complete the active matrix substrate (FIG. 2(g)).
以上本実施例に示したように、半導体層にキャリア発生
源となる元素を注入する際に、ゲート電極７をマスクと
してフォトリソグラフィ法を行なうことｔ−７より、イ
☆置合わ０機構等の不用な安価な露光ｔｌを使用ずろこ
とがτき、またフォトリソグラフィの回数を削減するこ
とが可能となる。また従来と比較して製膜回数も削減さ
れる。またＴ ＰＴの小型化も可能となり高開口率ある
いは高密度のアクティブマトリクス基板の実現や性能の
向」二を図ることができる。As described above in this embodiment, when injecting an element that becomes a carrier generation source into the semiconductor layer, photolithography is performed using the gate electrode 7 as a mask. Unnecessary and inexpensive exposure tl can be postponed, and the number of photolithography operations can be reduced. Furthermore, the number of times the film is formed can be reduced compared to the conventional method. Furthermore, it is possible to downsize the TPT, and it is possible to realize an active matrix substrate with a high aperture ratio or high density, and to improve performance.
実施例３
第２（図は、本発明の第３の実施例を工程を追って図示
したものである。Embodiment 3 Second Embodiment (The figures are step-by-step illustrations of the third embodiment of the present invention.
本実施例は第１の実施例と途中まで同一工程を用いてお
り、最初の共通部分の工程の説明は省略する。第１の実
施例の第１図（ｄ）のまでの工程を行なった基板に対し
、フォトｌ／シスト２１をエツチングマスクとしてパッ
シベイション［１１ａを食刻する（第３図（ｅ））、
この際等方性のウェットエツチングでエツチングを行
なってオーバーエツチングを行なう。この後フォトレジ
スト２１をマスクとしてフォトレジストの無い領域の半
導体層にキャリア発生源となる元素を注入する（第３図
（ｆ）；プラズマドーピング法を使用する。）。この後
基板にベーキングを行いパターニングされたパッシベー
ション層１１ｂより被着面積が大きくなっているフォト
レジスト２１ｂを用いて第１の半導体層を食刻する（第
３図（ｇ）；このとき異方性のエツチング手段であるド
ライエツチングを用いている。パッシベイション層をオ
ーバーエツチングした事もあり、食刻された第１の半導
体層の両わきにはドーピングされた領域１０ｂが確実に
残る）。この後レジストを除去した後、透明導電膜（Ｉ
ＴＯ）よりなる薄膜を被着し、パターニングして、ドレ
イン電極１５とソース電極１６及び絵素電極１７を形成
する。さらにパターニングされた透明導電膜に覆われて
いない部分のドーピングされた半導体層をエツチング液
で除去してアクティブマトリクス基板が完成する（第３
図（ｈ））以上本実施例に示したように、パッシベイシ
ョン層１１をパターン形成する際と、半導体層にキャリ
ア発生源となる元素を注入する際に、ゲート電極７をマ
スクとしてフォトリソグラフィ法を行なうことにより、
位置合わせ機構等の不用な安価な露光機を使用すること
ができ、またフォトリソグラフィの回数を削減すること
が可能となる。また従来と比較して製膜回数も削減され
る。またＴＰＴの小型化も可能となり高間口率あるいは
高密度のアクティブマトリクス基板の実現や性能の向丘
を図ることができる。This embodiment uses the same steps as the first embodiment up to the middle, and a description of the steps of the first common portion will be omitted. The substrate subjected to the steps up to FIG. 1(d) of the first embodiment is subjected to passivation [etching 11a (FIG. 3(e)) using the photol/sist 21 as an etching mask.
At this time, over-etching is performed by isotropic wet etching. Thereafter, using the photoresist 21 as a mask, an element to be a carrier generation source is implanted into the semiconductor layer in the area where there is no photoresist (FIG. 3(f); plasma doping is used). After that, the substrate is baked and the first semiconductor layer is etched using a photoresist 21b whose adhesion area is larger than that of the patterned passivation layer 11b (FIG. 3(g); at this time, the anisotropic (Dry etching, which is the etching method used in this example, is used.Due to over-etching the passivation layer, doped regions 10b are definitely left on both sides of the etched first semiconductor layer). After removing the resist, the transparent conductive film (I
A thin film made of TO) is deposited and patterned to form a drain electrode 15, a source electrode 16, and a picture element electrode 17. Further, the portions of the doped semiconductor layer that are not covered by the patterned transparent conductive film are removed using an etching solution to complete the active matrix substrate (third
Figure (h)) As shown in this embodiment, photolithography is performed using the gate electrode 7 as a mask when patterning the passivation layer 11 and when implanting an element that becomes a carrier generation source into the semiconductor layer. By doing the law,
An inexpensive exposure machine that does not require an alignment mechanism or the like can be used, and the number of photolithography operations can be reduced. Furthermore, the number of times the film is formed can be reduced compared to the conventional method. Furthermore, it becomes possible to downsize the TPT, thereby making it possible to realize an active matrix substrate with a high frontage ratio or high density, and to improve performance.
なお、以上の実施例１から実施例３では、絵素電極とド
レイン電極を同時に形成しているが、別々に形成しても
よい。In addition, in the above-mentioned Examples 1 to 3, the picture element electrode and the drain electrode are formed at the same time, but they may be formed separately.
また以上の実施例１から実施例３では、ゲート電極材料
としてＣｒを用いたがＴＰＴのゲート電極材料として使
用できる非透光性の導電性材料であれば使用し得る。ま
た、ゲート絶縁体層、パッシベーション層の材料として
は窒化シリコンの他、酸化シリコン、金属酸化物などの
透光性の絶縁体が用いれる。また第１、第２の半導体層
としては非晶質シリコンを用いたが、必要なＴＰＴ特性
を得ることができ、ある程度の紫外光を透過する半導体
材料であれば問題はなく、たとえば多結晶シリコンや再
結晶化したシリコンを用いることもできる。さらに、絵
素電極の材料としては、Ｉ ｎ ＯＫ ？Ｓ ｎ ＯＸ
あるいはこれらの混成組成の透光性導電材料（Ｉ Ｔｏ
）が使用できる。またソース電極とドレイン電極を絵素
電極と別々に形成する場合には、様々な導電性材料（Ａ
Ｉ、 Ｍｏ、Ｎｉ等の金属やそのシリサイド等）がソー
ス電極とドレイン電極材として使用し得る。Moreover, in the above Examples 1 to 3, Cr was used as the gate electrode material, but any non-transparent conductive material that can be used as the gate electrode material of TPT may be used. Furthermore, as the material for the gate insulator layer and the passivation layer, in addition to silicon nitride, a light-transmitting insulator such as silicon oxide or metal oxide is used. Although amorphous silicon was used as the first and second semiconductor layers, there is no problem with any semiconductor material that can obtain the necessary TPT characteristics and transmit a certain amount of ultraviolet light, such as polycrystalline silicon. It is also possible to use recrystallized silicon. Furthermore, as a material for the picture element electrode, In OK? S n OX
Alternatively, a translucent conductive material with a hybrid composition of these (I To
) can be used. In addition, when forming the source electrode and drain electrode separately from the pixel electrode, various conductive materials (A
Metals such as I, Mo, Ni, and their silicides) can be used as the source and drain electrode materials.
発明の効果
本発明のアクティブマトリクス基板の製造方法によれば
、ゲート電極をマスクとしてフォトリソグラフィ法を行
なうことにより、位置合わせ機構等の不用な安価な露光
機を使用することができ、またフォトリソグラフィの回
数を削減することが可能となり、あるいは製膜回数の削
減も可能となり、アクティブマトリクス型液晶表示装置
において最大の課題であるコストの低減を図ることがで
きる。またＴＰＴの小型化も可能となり高開口率あるい
は高密度のアクティブマトリクス基板の実現や性能の向
上を図ることができる。Effects of the Invention According to the method for manufacturing an active matrix substrate of the present invention, by performing photolithography using the gate electrode as a mask, it is possible to use an inexpensive exposure machine that does not require an alignment mechanism, etc. It becomes possible to reduce the number of times of . Further, it is possible to downsize the TPT, and it is possible to realize an active matrix substrate with a high aperture ratio or high density, and to improve performance.
第１図から第３図までは各々本発明の第１から第３の実
施例におけるアクティブマトリクス基板の製造方法を示
す工程図、第４図はアクティブマトリクス基板を用いた
液晶表示体の要部回路図、第５図は従来の製造方法で作
られたアクティブマトリクス基板を構成する薄膜トラン
ジスイタの平面図及びそのＡ−Ｂ線の断面図、第６図は
従来の製造方法で作られたアクティブマトリクス基板を
使った液晶表示装置の断面図である。
６・・・透光性基板、７・・・ゲート電極、１０・・・
第１の半導体層、１１・・・パッシベイション層、１２
・・・第２の半導体層、２１ポジ型フオトレジスト。
代理人の氏名 弁理士 粟野重孝 はか１名箒
図
７ケートｖ：、ネジ。
第
図
嘉
図
’７ｓｉ”−ト臀゛号
６造ｆ：、性ｌ！、板
第
図
０−Ｏ−◇
＋ 廿
〈〉２２鷲外光
第
図
Ｓソース配側泉
Ｊ吹銹ホ預壜1 to 3 are process diagrams showing the method for manufacturing an active matrix substrate in the first to third embodiments of the present invention, and FIG. 4 is a main circuit of a liquid crystal display using an active matrix substrate. 5 is a plan view of a thin film transistor constituting an active matrix substrate made by a conventional manufacturing method and a cross-sectional view taken along line A-B, and FIG. 6 is an active matrix made by a conventional manufacturing method. 1 is a cross-sectional view of a liquid crystal display device using a substrate. 6... Transparent substrate, 7... Gate electrode, 10...
First semiconductor layer, 11... Passivation layer, 12
...Second semiconductor layer, 21 positive type photoresist. Name of agent: Patent attorney Shigetaka Awano Haka 1 person Broom Figure 7 Kate v:, Neji. Diagram Kazu '7si'-To 〇゛No. 6 f:, Sex l!, Board No. 0-O-◇ + 廿〈〉22 Eagle outside light Diagram S Source side Izumi J blowing Seriho deposit bottle
Claims (6)
不透光性材料からなるゲート電極と、前記基板表面の露
出面及びゲート電極を覆う第１の絶縁体層と、前記第１
の絶縁体層上の特定領域を覆う半導体層と、前記半導体
層上の特定領域を覆う第２の絶縁体層と、前記半導体層
のソース電極及びドレイン電極とを順次形成するアクテ
ィブマトリクス基板の製造方法において、前記第２の絶
縁体層を形成する工程が、前記第１の絶縁体層上に半導
体層と第２の絶縁体層を被着する工程と、前記第２の絶
縁体層上にポジ型フォトレジストを塗着する工程と、前
記基板裏面から光照射する工程と、前記フォトレジスト
を現像する工程と、前記現像されたフォトレジストを用
いて前記第２の絶縁体層を食刻する工程とを含むことを
特徴とするアクティブマトリクス基板の製造方法。(1) A gate electrode made of a non-transparent material that covers a specific region of the substrate surface, a first insulator layer that covers the exposed surface of the substrate surface and the gate electrode, and a first insulator layer that covers the exposed surface of the substrate surface and the gate electrode; 1
manufacturing an active matrix substrate in which a semiconductor layer covering a specific area on an insulator layer, a second insulator layer covering a specific area on the semiconductor layer, and a source electrode and a drain electrode of the semiconductor layer are sequentially formed. In the method, the step of forming the second insulator layer includes the step of depositing a semiconductor layer and a second insulator layer on the first insulator layer, and the step of depositing a semiconductor layer and a second insulator layer on the first insulator layer. a step of applying a positive photoresist, a step of irradiating light from the back side of the substrate, a step of developing the photoresist, and etching the second insulating layer using the developed photoresist. A method of manufacturing an active matrix substrate, comprising the steps of:
を被着した基板にベーキングを行い、前記食刻された第
２の絶縁体層の面積より被着面積が大きい状態の前記フ
ォトレジストを用いて前記半導体層食刻する工程を加え
てなることを特徴とする請求項１記載のアクティブマト
リクス基板の製造方法。(2) After etching the second insulator layer, the substrate on which the photoresist is deposited is baked, and the photoresist layer is coated on the substrate in a state where the deposited area is larger than the area of the etched second insulator layer. 2. The method of manufacturing an active matrix substrate according to claim 1, further comprising the step of etching the semiconductor layer using a photoresist.
ーエッチングを行って食刻することを特徴とする請求項
２記載のアクティブマトリクス基板の製造方法。(3) The method for manufacturing an active matrix substrate according to claim 2, wherein the second insulating layer is etched by over-etching using an isotropic etching means.
を特徴とする請求項２記載のアクティブマトリクス基板
の製造方法。(4) The method for manufacturing an active matrix substrate according to claim 2, characterized in that the semiconductor layer is etched by an anisotropic etching means.
不透光性材料からなるゲート電極と、前記基板表面の露
出面及びゲート電極を覆う第１の絶縁体層と、前記第１
の絶縁体層上の特定領域を覆う半導体層と、前記半導体
層のソース電極及びドレイン電極とを順次形成するアク
ティブマトリクス基板の製造方法において、前記半導体
層を形成する工程が、前記第１の絶縁体層上に半導体層
を被着する工程と、前記半導体層上にポジ型フォトレジ
ストを塗着する工程と、前記基板裏面から光照射する工
程と、前記フォトレジストを現像する工程と、前記現像
されたフォトレジストの無い領域の前記半導体層にキャ
リア発生源となる元素を注入する工程と前記半導体層を
食刻する工程を含むアクティブマトリクス基板の製造方
法。(5) A gate electrode made of a non-transparent material that covers a specific region of the substrate surface, a first insulating layer that covers the exposed surface of the substrate surface and the gate electrode, and a first insulating layer that covers the exposed surface of the substrate surface and the gate electrode; 1
In the method for manufacturing an active matrix substrate, the step of forming the semiconductor layer includes sequentially forming a semiconductor layer covering a specific region on the first insulating layer, and a source electrode and a drain electrode of the semiconductor layer. a step of depositing a semiconductor layer on the body layer; a step of applying a positive photoresist on the semiconductor layer; a step of irradiating light from the back side of the substrate; a step of developing the photoresist; and a step of developing the photoresist. A method for manufacturing an active matrix substrate, comprising the steps of: implanting an element that serves as a carrier generation source into the semiconductor layer in a region where there is no photoresist; and etching the semiconductor layer.
工程の後、前記フォトレジストを被着した基板にベーキ
ングを行い、被着面積を増加した前記フォトレジストを
用いて前記半導体層を食刻する工程を加えてなる請求項
５記載のアクティブマトリクス基板の製造方法。(6) After the step of implanting an element that becomes a carrier generation source into the semiconductor layer, the substrate on which the photoresist is adhered is baked, and the semiconductor layer is etched using the photoresist with an increased adhesion area. 6. The method of manufacturing an active matrix substrate according to claim 5, further comprising the step of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1540289A JP2678044B2 (en) | 1989-01-25 | 1989-01-25 | Active matrix substrate manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1540289A JP2678044B2 (en) | 1989-01-25 | 1989-01-25 | Active matrix substrate manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02196222A true JPH02196222A (en) | 1990-08-02 |
| JP2678044B2 JP2678044B2 (en) | 1997-11-17 |
Family
ID=11887737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1540289A Expired - Fee Related JP2678044B2 (en) | 1989-01-25 | 1989-01-25 | Active matrix substrate manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2678044B2 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04233512A (en) * | 1990-12-28 | 1992-08-21 | Sharp Corp | Production of active matrix substrate |
| JPH04247433A (en) * | 1991-02-01 | 1992-09-03 | Sharp Corp | Production of active matrix substrate |
| JPH0836192A (en) * | 1994-07-21 | 1996-02-06 | Nec Corp | Active matrix substrate and its production |
| KR100223158B1 (en) * | 1996-06-07 | 1999-10-15 | 구자홍 | Active matrix substrate and its manufacturing method |
| US6071374A (en) * | 1996-06-26 | 2000-06-06 | Lg Electronics Inc. | Apparatus for etching glass substrate |
| US6197209B1 (en) | 1995-10-27 | 2001-03-06 | Lg. Philips Lcd Co., Ltd. | Method of fabricating a substrate |
| US6228211B1 (en) | 1998-09-08 | 2001-05-08 | Lg. Philips Lcd Co., Ltd. | Apparatus for etching a glass substrate |
| US6558776B1 (en) | 1998-10-22 | 2003-05-06 | Lg.Philips Lcd Co., Ltd. | Glass substrate for liquid crystal display device |
| KR100338428B1 (en) * | 1993-05-28 | 2003-05-17 | 다이니폰 인사츠 가부시키가이샤 | Method for forming substrate having light-shielding layer, substrate having ligh-shielding layer, counterelectrode substrate for thin film transistor (tft) array substrate for black and white display, and liquid crystal device for black and white display |
| US6887746B2 (en) | 1992-03-25 | 2005-05-03 | Semiconductor Energy Lab | Insulated gate field effect transistor and method for forming the same |
| US6955840B2 (en) | 1997-10-20 | 2005-10-18 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device having thin glass substrate on which protective layer formed and method of making the same |
| US8043466B1 (en) | 1997-03-21 | 2011-10-25 | Lg Display Co., Ltd | Etching apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62171160A (en) * | 1986-01-22 | 1987-07-28 | Sharp Corp | Thin film transistor |
-
1989
- 1989-01-25 JP JP1540289A patent/JP2678044B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62171160A (en) * | 1986-01-22 | 1987-07-28 | Sharp Corp | Thin film transistor |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04233512A (en) * | 1990-12-28 | 1992-08-21 | Sharp Corp | Production of active matrix substrate |
| JPH04247433A (en) * | 1991-02-01 | 1992-09-03 | Sharp Corp | Production of active matrix substrate |
| US6887746B2 (en) | 1992-03-25 | 2005-05-03 | Semiconductor Energy Lab | Insulated gate field effect transistor and method for forming the same |
| KR100338428B1 (en) * | 1993-05-28 | 2003-05-17 | 다이니폰 인사츠 가부시키가이샤 | Method for forming substrate having light-shielding layer, substrate having ligh-shielding layer, counterelectrode substrate for thin film transistor (tft) array substrate for black and white display, and liquid crystal device for black and white display |
| JPH0836192A (en) * | 1994-07-21 | 1996-02-06 | Nec Corp | Active matrix substrate and its production |
| US6197209B1 (en) | 1995-10-27 | 2001-03-06 | Lg. Philips Lcd Co., Ltd. | Method of fabricating a substrate |
| KR100223158B1 (en) * | 1996-06-07 | 1999-10-15 | 구자홍 | Active matrix substrate and its manufacturing method |
| US6071374A (en) * | 1996-06-26 | 2000-06-06 | Lg Electronics Inc. | Apparatus for etching glass substrate |
| US8043466B1 (en) | 1997-03-21 | 2011-10-25 | Lg Display Co., Ltd | Etching apparatus |
| US6955840B2 (en) | 1997-10-20 | 2005-10-18 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display device having thin glass substrate on which protective layer formed and method of making the same |
| US6228211B1 (en) | 1998-09-08 | 2001-05-08 | Lg. Philips Lcd Co., Ltd. | Apparatus for etching a glass substrate |
| US6558776B1 (en) | 1998-10-22 | 2003-05-06 | Lg.Philips Lcd Co., Ltd. | Glass substrate for liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2678044B2 (en) | 1997-11-17 |
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