JPH0216724A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0216724A JPH0216724A JP16661288A JP16661288A JPH0216724A JP H0216724 A JPH0216724 A JP H0216724A JP 16661288 A JP16661288 A JP 16661288A JP 16661288 A JP16661288 A JP 16661288A JP H0216724 A JPH0216724 A JP H0216724A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- aluminum
- nitride film
- substrate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 22
- 230000001681 protective effect Effects 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 abstract description 26
- 238000000034 method Methods 0.000 abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 24
- 229910052710 silicon Inorganic materials 0.000 abstract description 24
- 239000010703 silicon Substances 0.000 abstract description 24
- 230000008646 thermal stress Effects 0.000 abstract description 9
- 239000000126 substance Substances 0.000 abstract description 3
- 238000007669 thermal treatment Methods 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000003708 ampul Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum ions Chemical class 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、金属アルミニウムを拡散不純物源として半導
体基体に２層あるいはｐ゛層などのアルミニウム不純物
添加領域を形成する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device in which an aluminum impurity doped region such as a double layer or a p layer is formed in a semiconductor substrate using metal aluminum as a diffused impurity source.
半導体基板にｐ形の不純物添加領域を形成する場合、周
期律表のｍｂ族元素、特にほう素、ガリウム、アルミニ
ウムなどが使用される。この中でアルミニウムはシリコ
ン中での拡散係数が大きく、深い拡散層を容易に形成で
きるため、高耐圧素子に対する不純物濃度分布の要求を
満足する元素といえる。When forming a p-type impurity doped region in a semiconductor substrate, elements of the MB group of the periodic table, particularly boron, gallium, aluminum, etc., are used. Among these, aluminum has a large diffusion coefficient in silicon and can easily form a deep diffusion layer, so it can be said to be an element that satisfies the requirements for impurity concentration distribution for high voltage devices.
アルミニウム拡散法としては、閉管法、開管法。Aluminum diffusion methods include closed tube method and open tube method.
イオン注入法などが一般に知られている。閉管法は、シ
リコン基体と金属アルミニウムを透明石英管の中におき
、その石英管内を真空にしたのち溶封してアンプル状に
したものを電気炉に挿入し、所定の温度で所定の時間熱
処理する方法である。Ion implantation methods are generally known. In the closed tube method, a silicon substrate and metal aluminum are placed in a transparent quartz tube, the inside of the quartz tube is evacuated, the ampule is sealed, and the ampoule is inserted into an electric furnace, where it is heat-treated at a specified temperature for a specified period of time. This is the way to do it.
また、開管法は、酸化アルミニウムからなる円板とシリ
コン基体とを、例えば数ｎ間隔で交互に並べ、アルゴン
ガス中や水素ガス雰囲気中で熱処理する方法である。こ
れに対してイオン注入法は、アルミニウムイオンを加速
してシリコン基体に打込み、堆積層を形成したのち、所
定の温度で所定の時間熱処理する方法である。Further, the open tube method is a method in which disks made of aluminum oxide and silicon substrates are arranged alternately, for example, at intervals of several nanometers, and are heat-treated in an argon gas or hydrogen gas atmosphere. On the other hand, the ion implantation method is a method in which aluminum ions are accelerated and implanted into a silicon substrate to form a deposited layer, and then heat-treated at a predetermined temperature for a predetermined time.
（発明が解決しようとする課題〕
閉管法、開管法ともにシリコン基体の直径が３インチ以
上の大口径になると、問題が生じてくる。(Problems to be Solved by the Invention) In both the closed tube method and the open tube method, problems arise when the diameter of the silicon substrate becomes large, such as 3 inches or more.
すなわち、閉管法では、真空封止した石英管が熱処理中
につぶれてくるという問題があり、また開管法では、シ
リコン基体内のアルミニウム濃度ばらつきが大きくなる
という問題がある。一方、イオン注入法では、シリコン
基体の大きさは問題にならない、ところが、例えば表面
濃度１〜ｌ０ＸＩＯ１′原子／−のｐ形不純物添加領域
を形成しようとすると、ｌ〜ｌ０ＸＩＯ”原子／−のド
ーズ量を必要とするように、高ドーズ量のイオン注入を
必要とする。高ドーズ量でのイオン注入は、シリコン基
体に非晶質層を形成し、その非晶質層がその後の熱処理
の際結晶化する際、打込まれたアルミニウムが追い出さ
れて、いわゆるアウト・ディフユージッンが増大するた
め、それを補うためにさらに高ドーズ量のイオン注入が
必要とするという悪循環が生じる。That is, in the closed tube method, there is a problem in that the vacuum-sealed quartz tube collapses during heat treatment, and in the open tube method, there is a problem in that the aluminum concentration within the silicon substrate increases. On the other hand, in the ion implantation method, the size of the silicon substrate does not matter. However, when trying to form a p-type impurity doped region with a surface concentration of 1 to 10XIO" atoms/-, for example, the dose of 1 to 10XIO" atoms/- High-dose ion implantation forms an amorphous layer in the silicon substrate, and the amorphous layer is removed during subsequent heat treatment. During crystallization, the implanted aluminum is expelled and so-called out-diffusion increases, creating a vicious cycle in which a higher dose of ion implantation is required to compensate for this.
本発明の課題は、上記の諸問題に対処して大口径の半導
体基体にも所定の表面濃度のアルミニウム不純物添加領
域を容易に形成できる半導体装置の製造方法を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can address the above-mentioned problems and easily form an aluminum impurity doped region with a predetermined surface concentration even in a large diameter semiconductor substrate.
上記の課題の解決のために、本発明の方法は、半導体基
体中にアルミニウム不純物添加領域を形成する際に、半
導体基体表面にスパッタリング法によりアルミニウムを
堆積し、アルミニウムを堆積した半導体基体表面に酸化
膜、窒化膜および酸化膜を５００℃以下の温度で順次積
層してなる保護膜で形成したのち、熱処理をしてアルミ
ニウムを半導体基体内に拡散させるものとする。In order to solve the above problems, the method of the present invention, when forming an aluminum impurity doped region in a semiconductor substrate, deposits aluminum on the surface of the semiconductor substrate by a sputtering method, and oxidizes the surface of the semiconductor substrate on which aluminum is deposited. After forming a protective film in which a film, a nitride film, and an oxide film are sequentially laminated at a temperature of 500° C. or lower, heat treatment is performed to diffuse aluminum into the semiconductor substrate.
スパッタリングによりＭを半導体基体上に堆積させるた
め、基体中に非晶質が形成されない、また、Ｍを堆積し
た半導体基体表面を窒化膜で覆ってＭを基体中に拡散さ
せる際のアウトディフユージッンを防ぐ、この窒化膜と
半導体基体との間の酸化膜はその両者の熱膨張係数の差
による熱応力の発生を防ぐと共に、拡散工程終了後化学
的な方法で保護膜を除去するのを容易にする。しかし窒
化膜と酸化膜との間にも熱膨張係数の差があり、第二の
酸化膜で窒化膜をはさむことによりこの熱膨張係数の差
を補償して熱応力の発生を防ぐ、なお、酸化膜、窒化膜
を５００℃以下で成膜することにより、成膜時のＭのア
ウトディフユージッンや熱応力の発生も防止する。Since M is deposited on the semiconductor substrate by sputtering, no amorphous material is formed in the substrate, and the surface of the semiconductor substrate on which M is deposited is covered with a nitride film to prevent out-diffusion when M is diffused into the substrate. This oxide film between the nitride film and the semiconductor substrate prevents thermal stress from occurring due to the difference in thermal expansion coefficient between the two, and also prevents the protective film from being removed by chemical methods after the diffusion process is completed. make it easier. However, there is also a difference in thermal expansion coefficient between the nitride film and the oxide film, and by sandwiching the nitride film with a second oxide film, this difference in thermal expansion coefficient can be compensated for and the generation of thermal stress can be prevented. By forming the oxide film and nitride film at a temperature of 500° C. or lower, out-diffusion of M and generation of thermal stress during film formation are also prevented.
以下、図を引用して本発明の実施例について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａｌ〜（ｄ）はその工程を示し、先ずシリコン
基体１の上にアルミニウム層２を堆積する（図ａＬ第２
図はＭを堆積するための装置の概要を示す、この装置は
、真空容器ｌｌ内に対向配置され、いずれもＭからなる
電極２１．２２ 、電極２１．２２に接続されるグロー
放電用直流電源１２、電極２２上に置かれるシリコン基
体ｌを加熱するためのヒータ１３に接続される電源１４
．グロー放電時の容器内圧力を調整するための真空バル
ブ１５を介して接続される真空排気系１６、容器内圧力
測定のための真空計１７ならびにガス圧力と流量を調整
するための調整回路１Ｂを介して接続される不活性ガス
ボンベ１９を備えている。Ａ７製電極２１を所定の位置
に配置し、シリコン基体１を対向ｕｇ電極２２上に載置
したのち、真空排気系１６を用いて真空容器１１を約Ｉ
Ｘ １０−’Ｔｏｒｒにする。そのあと、真空パルプ１
５を絞り、真空排気系１６の排気速度を下げると同時に
、例えばアルゴンをガスボンベ１９から調整回路１８を
通して導入し、電源１２により電極２１．２２間に直流
電圧を印加してグロー放電を発生させると、電極２１．
２２のり原子がＡｒイオンによりたたき出され、ｔ％２
１上のシリコン基体１の上に堆積し、Ａ１７１２を形成
する。FIGS. 1(a-1d) show the process. First, an aluminum layer 2 is deposited on a silicon substrate 1 (see FIG.
The figure shows an outline of an apparatus for depositing M. This apparatus consists of electrodes 21.22, both made of M, and a glow discharge DC power supply connected to the electrodes 21.22, which are arranged facing each other in a vacuum container II. 12, a power source 14 connected to a heater 13 for heating the silicon substrate l placed on the electrode 22;
．． A vacuum exhaust system 16 connected via a vacuum valve 15 for adjusting the pressure inside the container during glow discharge, a vacuum gauge 17 for measuring the pressure inside the container, and an adjustment circuit 1B for adjusting the gas pressure and flow rate. It is equipped with an inert gas cylinder 19 connected through the inert gas cylinder 19. After arranging the A7 electrode 21 at a predetermined position and placing the silicon substrate 1 on the opposing UG electrode 22, the vacuum container 11 is heated to about I using the vacuum evacuation system 16.
Set to X 10-'Torr. After that, vacuum pulp 1
5 to reduce the evacuation speed of the evacuation system 16, for example, argon is introduced from the gas cylinder 19 through the adjustment circuit 18, and a DC voltage is applied between the electrodes 21 and 22 by the power source 12 to generate a glow discharge. , electrode 21.
22 glue atoms are knocked out by Ar ions, t%2
1 to form A1712.
次に、１層２を堆積したシリコン基体１の表面に０．１
−の厚さの酸化膜３を形成する （図ｂ）、この酸化膜
３は、Ｍ拡散後基体上の保護膜を化学的な方法で容易に
除去せしめるためのものであり、例えば５ｉｎｓと０８
とを用い、３００〜４００℃の基板温度で行う常圧ＣＶ
Ｄ法により低温で形成される。Next, 0.1
Form an oxide film 3 with a thickness of - (Figure b), this oxide film 3 is for easily removing the protective film on the substrate by a chemical method after M diffusion, for example, 5ins and 08mm thick.
Atmospheric pressure CV performed at a substrate temperature of 300 to 400°C using
Formed at low temperature by method D.
次いで、酸化膜３の上に、Ｍのアウトディフユージッン
を防ぐための０．０８−の厚さの窒化膜４を形成する
（図ｃ）、この窒化膜は、例えばＳＩＨ，とＮＨ３混合
ガスを高周波放電中で分解させ、４５０℃以下の低温で
基体上に堆積させるプラズマＣＶＤ法のような低温生成
法により形成される。この窒化膜４により、Ｍのアウト
デイフュージョンを防ぐのであるが、窒化膜中のＭの固
溶度は非常に大きく、窒化膜が厚いほど、拡散のための
熱処理中にアウトデイフュージョンにより窒化膜中に固
溶されるｕｌは多くなる。このため窒化膜４はなるべく
薄い方が良い、ただし、窒化膜４の厚さがシリコン基体
表面内でばらつきを生じていると、シリコン基体３内の
アルミニウム拡散量が部分的に変化するので、窒化膜４
は、シリコン基体面内で均等の厚さでかつ薄く形成する
必要がある。Next, on the oxide film 3, a nitride film 4 with a thickness of 0.08- is formed to prevent out-diffusion of M.
(FIG. c), this nitride film is formed by a low-temperature production method such as a plasma CVD method in which, for example, a mixed gas of SIH and NH3 is decomposed in a high-frequency discharge and deposited on a substrate at a low temperature of 450° C. or lower. This nitride film 4 prevents out-diffusion of M, but the solid solubility of M in the nitride film is very high, and the thicker the nitride film, the more likely it is that out-diffusion occurs during the heat treatment for diffusion. The amount of ul dissolved in the solid solution increases. Therefore, it is better to make the nitride film 4 as thin as possible. However, if the thickness of the nitride film 4 varies within the silicon substrate surface, the amount of aluminum diffused within the silicon substrate 3 will partially change. membrane 4
must be formed thin and uniformly thick within the plane of the silicon substrate.
さらに、窒化１１１４の上に０．１−の厚さの酸化膜５
が形成されており （図ｄ）、シリコンと窒化膜の熱膨
張係数の相違による熱応力の発生を抑えている。この酸
化膜５の形成は、深い拡散層を形成するために熱処理温
度が高い場合には上述の熱応力は十分には抑えられず、
酸化［３と窒化膜４の間に熱応力が発生し、窒化膜４に
亀裂が入ることへの対策である。すなわち、窒化膜４を
酸化膜３および酸化膜５によりはさむことで熱応力の発
生を極力抑える構造としている。この酸化膜５の形成も
、例えば５ｉＨａとＯｌとを用い、３００〜４００℃の
基板温度で行う常圧ＣＶＤ法によって低温で実施し５、
酸化膜５の厚さは、酸化膜３の厚さと同等なのが窒化膜
４に亀裂を発生させないために有効である。Further, on the nitride 1114, an oxide film 5 with a thickness of 0.1-
is formed (Figure d), suppressing the occurrence of thermal stress due to the difference in thermal expansion coefficient between silicon and nitride film. In the formation of this oxide film 5, when the heat treatment temperature is high to form a deep diffusion layer, the above-mentioned thermal stress cannot be sufficiently suppressed.
This is a measure to prevent cracks from occurring in the nitride film 4 due to generation of thermal stress between the oxidation film 3 and the nitride film 4. That is, by sandwiching the nitride film 4 between the oxide film 3 and the oxide film 5, the structure is such that the generation of thermal stress is suppressed as much as possible. The formation of this oxide film 5 is also carried out at a low temperature by atmospheric pressure CVD using, for example, 5iHa and Ol at a substrate temperature of 300 to 400°C.
It is effective for the thickness of the oxide film 5 to be equal to the thickness of the oxide film 3 in order to prevent cracks from occurring in the nitride film 4.
なお、酸化膜３．５．窒化膜４のいずれも低温で形成し
ているが、これは５００℃を超えると早くもＭのアウト
デイフュージョンが生じるためであり、また熱膨張計数
差による熱応力も大きくなるからである。Note that the oxide film 3.5. Both of the nitride films 4 are formed at a low temperature, because out-diffusion of M occurs as soon as the temperature exceeds 500° C., and thermal stress due to the difference in thermal expansion coefficient also increases.
第３図に第２図の装置を用いてＭ層２を堆積した段階で
のｕ１度プロファイルを二次イオン質量分析針（ＳＩＭ
Ｓ）で測定した結果で示す、グロー放電時の直流電源の
極性を、電極２１側は負、電極２２側は正にした状態で
、スパッタリングを行った。その他の条件は下記の通り
である。Figure 3 shows the u1 degree profile at the stage of depositing M layer 2 using the apparatus shown in Figure 2 using a secondary ion mass spectrometry needle (SIM).
Sputtering was performed while the polarity of the DC power supply during glow discharge was negative on the electrode 21 side and positive on the electrode 22 side, as shown in the results measured in S). Other conditions are as follows.
シリコン基体二〇型、比抵抗１００〜２００Ω・値シリ
コン基体温度：２００℃
グロー放電時の圧カニ ０．１４Ｔｏｒｒ （アルゴン
）放電ハ’７− ： Ｄ Ｃ８００Ｖ 、 ０．６ｍ
Ａ／ ｃＡこのように酸化膜３．窒化膜４．酸化膜５で
保護されたＭ堆積層２からＭをシリコン基体１内に拡散
させるために下記の条件の熱処理を行う。Silicon substrate type 20, specific resistance 100-200 Ω・value Silicon substrate temperature: 200℃ Pressure crab during glow discharge 0.14 Torr (Argon) discharge 7-: DC800V, 0.6m
A/ cA In this way, the oxide film 3. Nitride film 4. In order to diffuse M from the M deposited layer 2 protected by the oxide film 5 into the silicon substrate 1, heat treatment is performed under the following conditions.
温度： １２５０℃
時間：１６時間
熱処理雰囲気： 窒素
第４図は熱処理後のシリコン基体１中のｋｌ ｔ１度プ
ロファイルを拡がり抵抗測定法で測定した結果を示し、
上記条件で表面濃度３Ｘ１０”原子／ｃｄ。Temperature: 1250°C Time: 16 hours Heat treatment atmosphere: Nitrogen Figure 4 shows the results of measuring the kl t1 degree profile in the silicon substrate 1 after heat treatment using the spread resistance measurement method.
Surface concentration 3×10” atoms/cd under the above conditions.
拡散深さ６０−のｐ形拡散領域の得られることがわかる
。It can be seen that a p-type diffusion region with a diffusion depth of 60 - is obtained.
Ｍのイオン注入においても、注入後アニールを行うこと
によりｐ形拡散領域を形成することは可能であるが、イ
オン注入時に生ずる非晶質層の影響のため、保護膜のみ
で完全にアウトデイフュージョンをなくすのは難しい、
イオン注入で上記のｐ形拡散領域を形成するためには、
ｌＸｌ０”−以上のドーズ量が必要で、電気的活性化率
が約３０〜５０％程度なのに対し、本発明による方法で
はりの堆積をスパッタリングで行うため、非晶質層が生
せず、保護膜により完全にアウトデイフュージョンが防
げる。Even in the case of M ion implantation, it is possible to form a p-type diffusion region by performing annealing after implantation, but due to the influence of the amorphous layer produced during ion implantation, it is not possible to completely out-diffusion with only a protective film. It is difficult to eliminate
In order to form the above p-type diffusion region by ion implantation,
In contrast, the method of the present invention deposits the beam by sputtering, so no amorphous layer is formed and the protective The membrane completely prevents out-day fusion.
本発明によれば、半導体基体のｐ形不純物添加領域を形
成するためにＭを用いる場合に、基体上にスパッタリン
グでＭを堆積させ、アウトデイフュージョンを防ぐ窒化
膜の両面を酸化膜ではさんだ保ｆｌｌＷ！４で覆ったの
ちに熱処理して所定の深さまでＭを拡散させる。これに
よりイオン注入法と異なり非晶質層が生じないため、Ｍ
堆積量を増しての拡散熱処理の際のアウトデイフュージ
ョンを完全に防止し、深い拡散層も形成することができ
る。According to the present invention, when M is used to form a p-type impurity doped region of a semiconductor substrate, M is deposited on the substrate by sputtering, and both sides of a nitride film are sandwiched between oxide films to prevent out-diffusion. fllW! 4 and then heat-treated to diffuse M to a predetermined depth. Unlike ion implantation, this method does not produce an amorphous layer, so M
Out-diffusion during diffusion heat treatment with increased deposition amount can be completely prevented and a deep diffusion layer can be formed.
またシリコン、窒化膜、酸化膜相互間の熱膨張係数の相
違による窒化膜の亀裂の発生もなく、アウトデイフュー
ジョン防止にむらがないため、基体表面内のｋｌ濃度の
ばらつきも生じない、しかも、従来のり不純物添加領域
形成法にくらべ、装置が簡単で安価で量産性に富むので
、不純物添加工程の大幅なコストダウンが可能になった
。また、大口径半導体基板に対する適用にも極めてを効
である。In addition, there is no cracking in the nitride film due to differences in thermal expansion coefficients between silicon, nitride film, and oxide film, and out-diffusion prevention is uniform, so there is no variation in Kl concentration within the substrate surface. Compared to the conventional method of forming impurity-doped regions using glue, the equipment is simpler, cheaper, and easier to mass-produce, making it possible to significantly reduce the cost of the impurity-doping process. It is also extremely effective for application to large-diameter semiconductor substrates.
第１図は本発明の一実施例のり拡散熱処理以前の工程を
順次示す断面図、第２図は本発明の一実施例に用いるＭ
スパッタリング装置の構成断面図、第３図は本発明によ
りＭをスパッタリングしたシリコン基体表面のり堆積層
の濃度分布図第４図は本発明の一実施例により形成され
たｐ形拡散領域のに１濃度分布図である。
１：シリコン基体、２；Ｍ堆積層、３．５：酸化膜、４
：窒化膜、１１：真空容器、２１．２２ＦＡＪ製第２図
第１図
ジ、！？（Ａ）
第３図
運さ （μｍ）
第４図Fig. 1 is a sectional view sequentially showing the steps before glue diffusion heat treatment according to an embodiment of the present invention, and Fig. 2 is a cross-sectional view of a M used in an embodiment of the present invention.
FIG. 3 is a cross-sectional view of the structure of the sputtering apparatus, and FIG. 4 is a concentration distribution diagram of a glue deposited layer on the surface of a silicon substrate sputtered with M according to the present invention. FIG. It is a distribution map. 1: Silicon base, 2: M deposited layer, 3.5: Oxide film, 4
: Nitride film, 11: Vacuum container, 21.22 FAJ Figure 2 Figure 1 Ji,! ? (A) Figure 3 Length (μm) Figure 4
Claims (1)
成する際に、スパッタリング法によりアルミニウムを堆
積し、アルミニウムを堆積した半導体基体表面に、酸化
膜、窒化膜および酸化膜を５００℃以下の温度で順次積
層してなる保護膜を形成したのち、熱処理をしてアルミ
ニウムを半導体基体内に拡散させることを特徴とする半
導体装置の製造方法。(1) When forming an aluminum impurity doped region in a semiconductor substrate, aluminum is deposited by sputtering, and an oxide film, a nitride film, and an oxide film are sequentially formed on the surface of the semiconductor substrate on which aluminum is deposited at a temperature of 500°C or less. 1. A method of manufacturing a semiconductor device, which comprises forming a laminated protective film and then performing heat treatment to diffuse aluminum into a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16661288A JPH0216724A (en) | 1988-07-04 | 1988-07-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16661288A JPH0216724A (en) | 1988-07-04 | 1988-07-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0216724A true JPH0216724A (en) | 1990-01-19 |
Family
ID=15834537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16661288A Pending JPH0216724A (en) | 1988-07-04 | 1988-07-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0216724A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012023363A (en) * | 2010-06-17 | 2012-02-02 | Imec | Method for forming doped region in semiconductor layer of substrate and use of such method |
-
1988
- 1988-07-04 JP JP16661288A patent/JPH0216724A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012023363A (en) * | 2010-06-17 | 2012-02-02 | Imec | Method for forming doped region in semiconductor layer of substrate and use of such method |
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