JPH02163972A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPH02163972A JPH02163972A JP31782988A JP31782988A JPH02163972A JP H02163972 A JPH02163972 A JP H02163972A JP 31782988 A JP31782988 A JP 31782988A JP 31782988 A JP31782988 A JP 31782988A JP H02163972 A JPH02163972 A JP H02163972A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- amorphous silicon
- insulating film
- film transistor
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 17
- 239000010408 film Substances 0.000 claims abstract description 44
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 10
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 20
- 229910052710 silicon Inorganic materials 0.000 abstract description 18
- 239000010703 silicon Substances 0.000 abstract description 18
- 230000000694 effects Effects 0.000 abstract description 7
- 239000007864 aqueous solution Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VSCWAEJMTAWNJL-UHFFFAOYSA-K aluminium trichloride Chemical compound Cl[Al](Cl)Cl VSCWAEJMTAWNJL-UHFFFAOYSA-K 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007062 hydrolysis Effects 0.000 description 1
- 238000006460 hydrolysis reaction Methods 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は非晶質シリコンを用いた逆スタガード構造薄膜
ｎチャネルトランジスタの構造に関し、特にバックチャ
ネル効果による不安定性が無く、高信頼性が得られる非
晶質シリコン薄膜トランジスタに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of an inverted staggered thin film n-channel transistor using amorphous silicon, and in particular, it is free from instability due to back channel effects and has high reliability. The present invention relates to an amorphous silicon thin film transistor.
従来の逆スタガードｎチャネル非晶質シリコンＴＰＴの
構造の一例を第３図に示す。ガラス基板１０上にＮ ｉ
Ｃｒ等のゲート電極２０を設け、その上にシリコン酸
化膜、シリコン窒化膜等のゲート絶縁膜３０を設け、さ
らに非晶質真性半導体シリコン４０を設け、ソース及び
ドレイン部にはｎ型不純物を高濃度に添加したｎ＋層を
設ける。さらにｎ＋層からはＣｉ、Ａｆｌ等でソース電
極６０及びドレイン電極７０を設けた構造が一般的構造
である。An example of the structure of a conventional inverted staggered n-channel amorphous silicon TPT is shown in FIG. Ni on the glass substrate 10
A gate electrode 20 made of Cr or the like is provided, a gate insulating film 30 such as a silicon oxide film or a silicon nitride film is provided thereon, an amorphous intrinsic semiconductor silicon 40 is provided, and the source and drain portions are highly doped with n-type impurities. Provide a doped n+ layer. Furthermore, a general structure is such that a source electrode 60 and a drain electrode 70 are provided from the n+ layer using Ci, Afl, or the like.
上述した、従来構造の逆スタガード非晶質シリコンＴＰ
Ｔは第３図に示すようにソース電極６０とドレイン電極
７０との間にチャネル背面のシリコン部９０が最上表面
に位置している。この結果、チャネル背面のシリコン部
９０は非晶質真性半導体シリコン表面５０１が露出した
構造となる。そのため該表面は外部からの汚染、イオン
等の影響を受けｎ型化しやすく、その結果チャネル背面
のシリコン部９０にも望ましくないチャネルが形成され
ＴＰＴ ＯＦＦ時のリーク電流を増加させたり、ＴＰ
Ｔ特性の不安定性をもたらすという欠点を有していた。The above-mentioned inverted staggered amorphous silicon TP with conventional structure
As shown in FIG. 3, a silicon portion 90 on the back side of the channel is located at the uppermost surface between the source electrode 60 and the drain electrode 70. As a result, the silicon portion 90 on the back side of the channel has a structure in which the amorphous intrinsic semiconductor silicon surface 501 is exposed. Therefore, the surface is easily influenced by external contamination, ions, etc. and becomes n-type, and as a result, an undesirable channel is also formed in the silicon portion 90 on the back side of the channel, increasing the leakage current when the TPT is turned off, and
This has the disadvantage of causing instability of the T characteristic.
なお、この解決策の一例としてチャネル背面のシリコン
部９０上に保護絶縁膜としてシリコン酸化膜やシリコン
窒化膜を数千人形成し、汚染、イオンを防止し安定化を
計ることが考えられる。しかし、一般にこれらの絶縁膜
を形成すると絶縁膜中の固定電荷や、界面準位の発生の
ためシリコン表面はｎ型となり、ＴＰＴのリーク電流の
増加を完全に防ぐことは出来なかった。As an example of this solution, it is conceivable to form several thousand silicon oxide films or silicon nitride films as a protective insulating film on the silicon portion 90 on the back side of the channel to prevent contamination and ions and to stabilize the device. However, in general, when these insulating films are formed, the silicon surface becomes n-type due to fixed charges in the insulating film and generation of interface states, and it has not been possible to completely prevent an increase in leakage current of TPT.
本発明によれば、絶縁基板上にゲート電極。 According to the invention, a gate electrode is formed on an insulating substrate.
ゲート絶縁膜、非晶質シリコン膜、ソース及びドレイン
電極の順に設けられた逆スタガード非晶質シリコンＴＰ
Ｔにおいて、ソース電極とドレイン電極間のチャネル背
面部の非晶質シリコン上に３００Å以下の絶縁膜を有し
、非晶質シリコン内部表面に、該絶縁膜成長時に形成さ
れたＰ型層を有している薄膜トランジスタを得る。Inverted staggered amorphous silicon TP with gate insulating film, amorphous silicon film, source and drain electrodes provided in this order
In T, an insulating film of 300 Å or less is formed on the amorphous silicon at the back of the channel between the source electrode and the drain electrode, and a P-type layer formed during the growth of the insulating film is formed on the inner surface of the amorphous silicon. Obtain a thin film transistor with
以下、本発明について図面を用いて説明する。 Hereinafter, the present invention will be explained using the drawings.
第１図は本発明の一実施例を示すＴＰＴの模式的な縦断
面図である。本図において、チャネル背面部の非晶質シ
リコン半導体４００表面上には過酸化水素水溶液に浸す
ことにより形成した３００Å以下のシリコン酸化膜８０
を形成する。又、このシリコン酸化膜８０を形成するこ
とによりシリコン４０の表面にはＰ型層５１が形成され
ることがわかった。FIG. 1 is a schematic vertical sectional view of a TPT showing an embodiment of the present invention. In this figure, a silicon oxide film 80 with a thickness of 300 Å or less is formed on the surface of an amorphous silicon semiconductor 400 at the back side of the channel by immersing it in a hydrogen peroxide aqueous solution.
form. It has also been found that by forming this silicon oxide film 80, a P-type layer 51 is formed on the surface of silicon 40.
過酸化水素水溶液により形成されるシリコン酸化膜８０
の厚さは、水溶液の温度５時間にもよるが室温では３０
０人程度がリミットである。シリコン４０の内部表面に
誘起される電荷密度は１０口〜１．０”／ｃｎｔで信頼
性上安定である。Silicon oxide film 80 formed from hydrogen peroxide aqueous solution
The thickness depends on the temperature of the aqueous solution for 5 hours, but at room temperature it is 30
The limit is about 0 people. The charge density induced on the internal surface of the silicon 40 is 10 to 1.0''/cnt, which is stable in terms of reliability.
第２図は本発明の他の実施例を示すＴＰＴの模式的な縦
断面図である。本図においては、チャネル背面部の非晶
質シリコン半導体４０上には塩化アルミニウムの加水分
解によりプラズマＣＶＤ法により形成したアルミナ膜８
１を３００Å以下形成した。又、このアルミナ膜８１を
形成することによりシリコン４００表面にはＰ型層５２
が形成されることがわかった。アルミナ膜８１の形成に
よりシリコン４０の内部表面に誘起される正電荷密度は
ｌ Ｏ””−１０”／ｃｎｌで信頼性上も安定である。FIG. 2 is a schematic vertical sectional view of a TPT showing another embodiment of the present invention. In this figure, an alumina film 8 formed by plasma CVD using hydrolysis of aluminum chloride is formed on the amorphous silicon semiconductor 40 at the back side of the channel.
1 was formed to a thickness of 300 Å or less. Also, by forming this alumina film 81, a P-type layer 52 is formed on the surface of the silicon 400.
was found to be formed. The positive charge density induced on the internal surface of the silicon 40 by the formation of the alumina film 81 is l O""-10"/cnl, which is stable in terms of reliability.
アルミナ膜８１は３００Å以上厚くしても正電荷密度は
大きく変わらない。工程の時間短縮。Even if the alumina film 81 is thickened by 300 Å or more, the positive charge density does not change significantly. Reduce process time.
厚くすることによる歪、クラック等の短所を考えると３
００Å以下で充分である。Considering the disadvantages such as distortion and cracks due to thickening, 3.
00 Å or less is sufficient.
以上説明したように、本発明は３００Å以下の絶縁膜を
チャネル背面部の非晶質シリコン半導体上に形成し、し
かも該絶縁膜形成時にシリコン内部表面にＰ型層を形成
する。このＰ型層の形成によりチャネル背面部がｎ型化
し、チャネルが形成され、いわゆるバックチャネル効果
によるＴＰＴのリーク電流の増大、特性の増大を抑える
効果がある。絶縁膜の形成はシリコン内部表面にＰ型層
を形成するためであり、この為には３００Å以下で充分
であり厚くするとかえって歪、クラック等のデメリット
が生じる。As described above, in the present invention, an insulating film of 300 Å or less is formed on the amorphous silicon semiconductor at the back surface of the channel, and a P-type layer is formed on the inner surface of the silicon when forming the insulating film. By forming this P-type layer, the back surface of the channel becomes n-type and a channel is formed, which has the effect of suppressing an increase in leakage current and an increase in characteristics of the TPT due to the so-called back channel effect. The purpose of forming the insulating film is to form a P-type layer on the internal surface of the silicon, and for this purpose, a thickness of 300 Å or less is sufficient; if it is made thicker, disadvantages such as distortion and cracks will occur.
第４図は本発明の効果を示すための、信頼性試験前後の
ＴＰＴ特性である。初期ＴＰＴ特性９１は従来品と本発
明品で大差ない。しかし、信頼性試験後のＴＰＴ特性９
２．９３は従来構造９２ではゲート電極Ｖ。が負方向に
シフトし、又リーク電流も大きい、一方、本発明ＴＰＴ
９３では特性は極めて安定である。FIG. 4 shows TPT characteristics before and after a reliability test to demonstrate the effects of the present invention. The initial TPT characteristics 91 are not much different between the conventional product and the product of the present invention. However, TPT characteristics 9 after reliability testing
2.93 is the gate electrode V in the conventional structure 92. is shifted in the negative direction, and the leakage current is also large. On the other hand, the TPT of the present invention
93, the characteristics are extremely stable.
以上、３００Å以下の絶縁膜で表面をＰ型化する効果に
ついて説明した。加うるに、チャネル掘り込みにチャネ
ル掘り込みによる凹部を埋めるため、あるいは外部から
の汚染イオンをより完全に防ぐ為、リン珪酸ガラス膜、
シリコン酸化膜、シリコン窒化膜等をプラズマＣＶＤ法
等で３００Å以上成長し、保護絶縁膜を二層構造にでき
ることはいうまでもない。The effect of making the surface P-type with an insulating film of 300 Å or less has been described above. In addition, a phosphosilicate glass film,
It goes without saying that the protective insulating film can be formed into a two-layer structure by growing a silicon oxide film, a silicon nitride film, etc. to a thickness of 300 Å or more by plasma CVD or the like.
リコン、５０・・・・・・高濃度ｎ型不純物添加シリコ
ン、６０・・・・・・ソース電極、７０・・・・・・ド
レイン電極、８０・・・・・・シリコン酸化膜、９０・
・・・・・チャネル背面シリコン部、５１．５２・・・
・・−Ｐ型シリコン層、８１・・・・・・アルミナ膜、
９工・・・・・・初期ＴＦＴ特性、９２・・・・・・従
来構造ＴＰＴの信頼性試験後特性、９３・・・・・・本
発明ＴＰＴの信頼性試験後特性。Silicon, 50...High concentration n-type impurity doped silicon, 60...Source electrode, 70...Drain electrode, 80...Silicon oxide film, 90...
...Channel backside silicon part, 51.52...
...-P-type silicon layer, 81... alumina film,
9th grade: Initial TFT characteristics, 92: Characteristics after reliability test of conventional structure TPT, 93: Characteristics after reliability test of TPT of the present invention.
代理人 弁理士 内 原 晋Agent Patent Attorney Susumu Uchihara
第１図は本発明の一実施例を示す薄膜トランジスタの断
面図、第２図は本発明の他の実施例を示す薄膜トランジ
スタの断面図、第３図は従来の薄膜トランジスタの断面
図、第４図は従来及び本発明の薄膜トランジスタの信頼
性試験前後の特性比較を示す図である。
１０・・・・・・ガラス基板、２０・・・・・・ゲート
電極、３０・・・・・・ゲート絶縁膜、４０・・・・・
・非晶質半導体シ拓 ノ ＩＤ
第３ 図
デθチイ、ネ、Ｌａ面シリコン部
第４図
第２ 図
千２ ケ二ト′電ソ玉（゛し′ジFIG. 1 is a cross-sectional view of a thin film transistor showing one embodiment of the present invention, FIG. 2 is a cross-sectional view of a thin film transistor showing another embodiment of the present invention, FIG. 3 is a cross-sectional view of a conventional thin film transistor, and FIG. FIG. 3 is a diagram showing a comparison of characteristics before and after a reliability test of a conventional thin film transistor and a thin film transistor of the present invention. 10... Glass substrate, 20... Gate electrode, 30... Gate insulating film, 40...
・Amorphous semiconductor technology ID Figure 3 De θchii, Ne, La plane silicon part Figure 4 Figure 2
Claims (3)
シリコン膜、ソース及びドレイン電極の順に設けられた
逆スタガード構造の薄膜トランジスタにおいて、ソース
電極とドレイン電極間のチャネル背面部の半導体層の表
面上に３００Å以下の絶縁膜を具備していることと、該
半導体層の表面に該絶縁膜と接して反対導電型層を具備
していることを特徴とする薄膜トランジスタ(1) In a thin film transistor with an inverted staggered structure in which a gate electrode, a gate insulating film, an amorphous silicon film, a source electrode, and a drain electrode are provided in this order on an insulating substrate, the semiconductor layer on the back side of the channel between the source electrode and the drain electrode is A thin film transistor comprising an insulating film with a thickness of 300 Å or less on a surface thereof, and a layer of an opposite conductivity type on the surface of the semiconductor layer in contact with the insulating film.
て、前記半導体層は非晶質シリコンであり、この非晶質
シリコンの表面上に過酸化水素水溶液に浸すことにより
形成した３００Å以下のシリコン酸化膜を具備している
ことを特徴とする薄膜トランジスタ(2) In the thin film transistor according to claim (1), the semiconductor layer is amorphous silicon, and a silicon oxide layer of 300 Å or less is formed on the surface of the amorphous silicon by immersing it in an aqueous hydrogen peroxide solution. A thin film transistor characterized by comprising a film.
て、前記半導体層は非晶質シリコンであり、この非晶質
シリコンの表面上にプラズマＣＶＤ法により形成した３
００Å以下のアルミナ膜を具備していることを特徴とす
る薄膜トランジスタ(3) In the thin film transistor according to claim (1), the semiconductor layer is amorphous silicon, and the semiconductor layer is formed by plasma CVD on the surface of the amorphous silicon.
A thin film transistor characterized by comprising an alumina film with a thickness of 00 Å or less
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63317829A JPH07114285B2 (en) | 1988-12-16 | 1988-12-16 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63317829A JPH07114285B2 (en) | 1988-12-16 | 1988-12-16 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02163972A true JPH02163972A (en) | 1990-06-25 |
| JPH07114285B2 JPH07114285B2 (en) | 1995-12-06 |
Family
ID=18092517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63317829A Expired - Lifetime JPH07114285B2 (en) | 1988-12-16 | 1988-12-16 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07114285B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561074A (en) * | 1994-04-22 | 1996-10-01 | Nec Corporation | Method for fabricating reverse-staggered thin-film transistor |
| US5739886A (en) * | 1993-12-20 | 1998-04-14 | Nec Corporation | Liquid crystal display with reverse staggered thin film transistors and opposite electrode, and fabrication method thereof |
| US5962896A (en) * | 1994-12-20 | 1999-10-05 | Sharp Kabushiki Kaisha | Thin film transistor including oxidized film by oxidation of the surface of a channel area semiconductor |
| US7320905B2 (en) | 1998-08-21 | 2008-01-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device provided with semiconductor circuit made of semiconductor element and method of fabricating the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63193568A (en) * | 1987-02-05 | 1988-08-10 | Mitsubishi Electric Corp | Thin film transistor |
-
1988
- 1988-12-16 JP JP63317829A patent/JPH07114285B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63193568A (en) * | 1987-02-05 | 1988-08-10 | Mitsubishi Electric Corp | Thin film transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5739886A (en) * | 1993-12-20 | 1998-04-14 | Nec Corporation | Liquid crystal display with reverse staggered thin film transistors and opposite electrode, and fabrication method thereof |
| US5561074A (en) * | 1994-04-22 | 1996-10-01 | Nec Corporation | Method for fabricating reverse-staggered thin-film transistor |
| US5962896A (en) * | 1994-12-20 | 1999-10-05 | Sharp Kabushiki Kaisha | Thin film transistor including oxidized film by oxidation of the surface of a channel area semiconductor |
| US7320905B2 (en) | 1998-08-21 | 2008-01-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device provided with semiconductor circuit made of semiconductor element and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07114285B2 (en) | 1995-12-06 |
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