JPH02159069A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02159069A JPH02159069A JP31476288A JP31476288A JPH02159069A JP H02159069 A JPH02159069 A JP H02159069A JP 31476288 A JP31476288 A JP 31476288A JP 31476288 A JP31476288 A JP 31476288A JP H02159069 A JPH02159069 A JP H02159069A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- oxide film
- type polysilicon
- type
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 125000001153 fluoro group Chemical group F* 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 13
- 125000004435 hydrogen atom Chemical group [H]* 0.000 abstract description 7
- 229910052731 fluorine Inorganic materials 0.000 abstract description 4
- 239000011737 fluorine Substances 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ボロンをドープしたＰ型ポリシリコンをゲー
ト電極とするＭＩＳ型半導体装置の製造方法に関し、と
くに高信頼化を図った製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing an MIS type semiconductor device using boron-doped P-type polysilicon as a gate electrode, and particularly relates to a manufacturing method that achieves high reliability. It is something.
〔従来の技術］
ＬＳＩの高密度化に伴うデバイス寸法の微細化により、
Ｎ型ポリシリコン電極ＭＯ８ＦＥＴより構成されるＣＭ
Ｏ８のしきい値制御は難しくなりつつある。ＣＭＯ８の
しきい値制御を容易にするため、Ｎ型ポリシリコンとは
Ｓｔ基板との仕事関数差の違うＰ型ポリシリコン電極を
用いることが提案されている。[Conventional technology] Due to the miniaturization of device dimensions due to the increase in the density of LSI,
CM composed of N-type polysilicon electrode MO8FET
O8 threshold control is becoming difficult. In order to facilitate threshold control of the CMO 8, it has been proposed to use a P-type polysilicon electrode that has a different work function from the N-type polysilicon electrode and the St substrate.
Ｐ型ポリシリコン電極ＭＯＳデバイスにおいては、電極
中のボロン原子ＣＢ）は水素原子（Ｈ）と結合しやすく
多量に水素を含む。このためＰ型ポリシリコン電極ＭＯ
８デバイスでは、その動作中にＳｉ／ＳｌＯ鵞界面にお
ける界面単位密度はデバイス中に含まれる水素との反応
により多量に増加するため、その信頼性はＮ型ポリシリ
コン電極ＭＯＳデバイスより低くなるという問題がある
。In a P-type polysilicon electrode MOS device, boron atoms (CB) in the electrode easily combine with hydrogen atoms (H) and contain a large amount of hydrogen. For this reason, the P-type polysilicon electrode MO
In the 8 device, during operation, the interfacial unit density at the Si/SlO interface increases by a large amount due to reaction with hydrogen contained in the device, so the reliability is lower than that of the N-type polysilicon electrode MOS device. There is.
本発明の目的は、従来の問題点を解決し、Ｐ型ポリシリ
コン電極を用いたＭＯＳデバイスにおける信頼性の向上
をはかることＫＴｏる。An object of the present invention is to solve the conventional problems and improve the reliability of a MOS device using a P-type polysilicon electrode.
本発明は上記目的を達成するため、半導体基板上に絶縁
膜を介して形成されたＰ型ポリシリコンより成るゲート
電極を有するＭＩＳ型半導体装置の製造方法において、
前記ゲート電極中にフッ素原子を導入する工程を含んで
なることを特徴とする。In order to achieve the above object, the present invention provides a method for manufacturing an MIS type semiconductor device having a gate electrode made of P-type polysilicon formed on a semiconductor substrate with an insulating film interposed therebetween.
The method is characterized in that it includes a step of introducing fluorine atoms into the gate electrode.
本発明は、ＭＯＳデバイスのＳ ｌ ／ Ｓ ｉ Ｏ！
界面ＩＦ−おける界面準位低下を、フッ素原子を電極
中に導入すること（以下Ｆ処理と略す）により行おうと
するものである。この方法によりポロン原子（Ｂ）と結
合する水素原子（Ｈ）は存在しないため、及びゲート酸
化膜中に含まれるフッ素原子が水素原子をトラップする
ため、水素原子による界面準位発生はないものと考えら
れる。またゲート酸化膜中に含まれるフッ素原子が水素
原子をトラップするため本発明のＦ処理により作製した
Ｐ型ポリシリコン電極ＭＯ８キャパシタと、従来のＨ！
処理により作製したＭＯＳキャパシタの信頼性評価を第
２図に示す。試験温度２５０℃、試験バイアス＋４ＭＶ
／ ｃｍである。同図かられかるようにＦ処理を行っ
たＰ型ポリシリコン電極ＭＯＳキャパシタの界面準位密
度１０２はＨ意処理により作製さルた従来のデバイスの
場合の界面準位密度１０１に比べて大幅に低下してお９
、Ｐ型ポリシリコン電極ＭＯＳデバイスの信頼性を向上
させることができる。The present invention provides S l/S i O! of MOS devices.
This method attempts to lower the interface state at the interface IF- by introducing fluorine atoms into the electrode (hereinafter abbreviated as F treatment). With this method, there is no hydrogen atom (H) bonding with the poron atom (B), and the fluorine atoms contained in the gate oxide film trap the hydrogen atom, so it is assumed that there will be no generation of interface states due to hydrogen atoms. Conceivable. In addition, since fluorine atoms contained in the gate oxide film trap hydrogen atoms, there are two types of P-type polysilicon electrode MO8 capacitors fabricated using the F process of the present invention, and the conventional H!
FIG. 2 shows the reliability evaluation of the MOS capacitor manufactured by the process. Test temperature 250℃, test bias +4MV
/ cm. As can be seen from the figure, the interface state density 102 of the P-type polysilicon electrode MOS capacitor subjected to the F treatment is significantly higher than the interface state density 101 of the conventional device fabricated by the H treatment. It's down to 9
, the reliability of P-type polysilicon electrode MOS devices can be improved.
以下図面にもとづき実施例について説明する。Examples will be described below based on the drawings.
本発明の実施例を第１図ａ乃至Ｃを用いて説明する。な
お実施例として簡単のためにＭＯＳキャパシタを例に取
り上げるが、これに限定されるものでなくＭＯＳＦＥＴ
でも同様の効果が期待できる。Embodiments of the present invention will be described using FIGS. 1A to 1C. In addition, as an example, a MOS capacitor will be taken as an example for the sake of simplicity, but the invention is not limited to this, and MOSFET
However, similar effects can be expected.
第１図ａに示すようにＳｉ基板２０１Ｐ型１００面上に
フィールド酸化膜２０２を３００ＯＡ及びゲート酸化膜
°２０３を７０＾形成する。次に第１図すに示すように
ポリシリコン２０４を３００ＯＡ堆積した後イオン注入
３０ ＫｅＶ＋ ６ Ｘ １０’ｔ／−を用いてポロン
及びフッ素を２：１の比で注入３０ ＫｅＶ、 ３ Ｘ
１０”／ ｄ Ｌ、、Ｎ。As shown in FIG. 1a, a field oxide film 202 with a thickness of 300 OA and a gate oxide film 203 with a thickness of 70^ are formed on a P type 100 surface of a Si substrate 201. Next, as shown in FIG. 1, after depositing polysilicon 204 at a density of 300 OA, poron and fluorine were implanted at a ratio of 2:1 using ion implantation of 30 KeV+ 6 X 10't/-.
10”/d L,,N.
中で２０分、８００〜９００℃の温度で熱処理を行う。A heat treatment is carried out at a temperature of 800 to 900° C. for 20 minutes in a container.
この場合の７ツ１素濃度は３Ｘ１０１”（１／、−１１
１）である。In this case, the concentration of seven elements is 3X101” (1/, -11
1).
ただし、ポロンとフッ素の比は２：１〜１０：１の範囲
であればよい。その後７１１１図Ｃに示すようにゲート
電極加工の後ＰＳＧ膜２０５の堆積、コンタクトホール
の形成、Ａｔ２０６の蒸着を行う。最後の熱処理は温度
４００℃でＮｓ雰囲気大気圧中で３０分行う。However, the ratio of poron to fluorine may be in the range of 2:1 to 10:1. Thereafter, as shown in FIG. 7111C, after processing the gate electrode, a PSG film 205 is deposited, a contact hole is formed, and At 206 is evaporated. The final heat treatment is performed at a temperature of 400° C. in an Ns atmosphere at atmospheric pressure for 30 minutes.
本実施例ではＰ型ポリシリコンへのフッ素原子の導入法
としてイオン注入法を用いた（第１図ｂ）が、これに限
定されるものではない。例えば、フッ素原子のイオン注
入法の代わりに最後の熱処理をフッ素雰囲気中で行うよ
うにしてもよい。In this embodiment, ion implantation was used as a method for introducing fluorine atoms into P-type polysilicon (FIG. 1b), but the present invention is not limited to this method. For example, instead of ion implantation of fluorine atoms, the final heat treatment may be performed in a fluorine atmosphere.
入する工程を含むことを特徴とするＦ処理を行うことに
よりＰ型ポリシリコン電極ＭＯＳデバイスの信頼性を向
上させることができる。The reliability of the P-type polysilicon electrode MOS device can be improved by performing the F process, which is characterized in that it includes a step of injecting.
第１図ａ乃至Ｃは本発明の実施例を示す工程断面図、第
２図はＰ型ポリシリコン電極ＭＯＳキャパシタの信頼性
試験の結果である。
１０１・・・従来のＨａ処理により作製した場合の界面
準位密度の変化、１０２・・・本発明のＦ処理にょシ作
製した場合の界面準位密度の変化、２０１・・・Ｓｉ基
板、２０２・・・フィールド酸化膜、２０３・・・ゲー
ト酸化膜、２０４・・・ポリシリコン、２０５・・・Ｐ
ＳＧ、２０６・・・Ａｔ
〔発明の効果〕
以上説明したように、本発明は半導体基板上に絶縁膜を
介して形成されたＰ型ポリシリコンより成るゲート電極
を有するＭＩＳ型半導体装置の製造方法において、ゲー
ト電極中にフッ素原子を導特許出願入 日本電信電話
株式会社1A to 1C are process cross-sectional views showing an embodiment of the present invention, and FIG. 2 shows the results of a reliability test of a P-type polysilicon electrode MOS capacitor. 101...Change in interface state density when fabricated by conventional Ha treatment, 102...Change in interface state density when fabricated by F treatment of the present invention, 201...Si substrate, 202 ...Field oxide film, 203...Gate oxide film, 204...Polysilicon, 205...P
SG, 206...At [Effects of the Invention] As explained above, the present invention provides a method for manufacturing an MIS type semiconductor device having a gate electrode made of P-type polysilicon formed on a semiconductor substrate with an insulating film interposed therebetween. Nippon Telegraph and Telephone Corporation filed a patent application for introducing fluorine atoms into the gate electrode.
Claims (1)
コンより成るゲート電極を有するＭＩＳ型半導体装置の
製造方法において、 前記ゲート電極中にフッ素原子を導入する工程を含んで
なることを特徴とする半導体装置の製造方法。[Claims] A method for manufacturing an MIS type semiconductor device having a gate electrode made of P-type polysilicon formed on a semiconductor substrate with an insulating film interposed therebetween, including the step of introducing fluorine atoms into the gate electrode. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314762A JP2626910B2 (en) | 1988-12-12 | 1988-12-12 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63314762A JP2626910B2 (en) | 1988-12-12 | 1988-12-12 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02159069A true JPH02159069A (en) | 1990-06-19 |
| JP2626910B2 JP2626910B2 (en) | 1997-07-02 |
Family
ID=18057278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63314762A Expired - Lifetime JP2626910B2 (en) | 1988-12-12 | 1988-12-12 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2626910B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04157765A (en) * | 1990-10-20 | 1992-05-29 | Nippon Telegr & Teleph Corp <Ntt> | Insulated gate type field effect transistor and manufacture thereof |
| US5523240A (en) * | 1990-05-29 | 1996-06-04 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor with a halogen doped blocking layer |
| JPH1140803A (en) * | 1997-07-15 | 1999-02-12 | Toshiba Corp | Semiconductor device and its manufacture |
| JPH11163345A (en) * | 1997-09-29 | 1999-06-18 | Matsushita Electron Corp | Manufacture of semiconductor device |
| US6277718B1 (en) | 1997-09-29 | 2001-08-21 | Fujitsu Limited | Semiconductor device and method for fabricating the same |
| US6482752B1 (en) * | 1993-10-26 | 2002-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Substrate processing apparatus and method and a manufacturing method of a thin film semiconductor device |
| WO2018216309A1 (en) * | 2017-05-22 | 2018-11-29 | シャープ株式会社 | Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035561A (en) * | 1983-08-08 | 1985-02-23 | Oki Electric Ind Co Ltd | Manufacture of n-well complementary type semiconductor device |
| JPS6233469A (en) * | 1985-08-06 | 1987-02-13 | Nec Corp | Mis field defect transistor |
| JPS62285470A (en) * | 1986-06-04 | 1987-12-11 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1988
- 1988-12-12 JP JP63314762A patent/JP2626910B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6035561A (en) * | 1983-08-08 | 1985-02-23 | Oki Electric Ind Co Ltd | Manufacture of n-well complementary type semiconductor device |
| JPS6233469A (en) * | 1985-08-06 | 1987-02-13 | Nec Corp | Mis field defect transistor |
| JPS62285470A (en) * | 1986-06-04 | 1987-12-11 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6607947B1 (en) | 1990-05-29 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device with fluorinated layer for blocking alkali ions |
| US5523240A (en) * | 1990-05-29 | 1996-06-04 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a thin film transistor with a halogen doped blocking layer |
| JPH04157765A (en) * | 1990-10-20 | 1992-05-29 | Nippon Telegr & Teleph Corp <Ntt> | Insulated gate type field effect transistor and manufacture thereof |
| US7691692B2 (en) | 1993-10-26 | 2010-04-06 | Semiconductor Energy Laboratory Co., Ltd. | Substrate processing apparatus and a manufacturing method of a thin film semiconductor device |
| US6482752B1 (en) * | 1993-10-26 | 2002-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Substrate processing apparatus and method and a manufacturing method of a thin film semiconductor device |
| US7271082B2 (en) | 1993-10-26 | 2007-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7452794B2 (en) | 1993-10-26 | 2008-11-18 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of a thin film semiconductor device |
| US8304350B2 (en) | 1993-10-26 | 2012-11-06 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| JPH1140803A (en) * | 1997-07-15 | 1999-02-12 | Toshiba Corp | Semiconductor device and its manufacture |
| US6277718B1 (en) | 1997-09-29 | 2001-08-21 | Fujitsu Limited | Semiconductor device and method for fabricating the same |
| JPH11163345A (en) * | 1997-09-29 | 1999-06-18 | Matsushita Electron Corp | Manufacture of semiconductor device |
| WO2018216309A1 (en) * | 2017-05-22 | 2018-11-29 | シャープ株式会社 | Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device |
| JPWO2018216309A1 (en) * | 2017-05-22 | 2020-02-27 | シャープ株式会社 | Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2626910B2 (en) | 1997-07-02 |
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