JPH0215697A - Surface packaging method - Google Patents
Surface packaging methodInfo
- Publication number
- JPH0215697A JPH0215697A JP63166122A JP16612288A JPH0215697A JP H0215697 A JPH0215697 A JP H0215697A JP 63166122 A JP63166122 A JP 63166122A JP 16612288 A JP16612288 A JP 16612288A JP H0215697 A JPH0215697 A JP H0215697A
- Authority
- JP
- Japan
- Prior art keywords
- component
- lead wires
- package
- chip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004806 packaging method and process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910000679 solder Inorganic materials 0.000 abstract description 13
- 238000005476 soldering Methods 0.000 abstract description 10
- 239000007767 bonding agent Substances 0.000 abstract 2
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ハイブリッド集積回路や、無機系及び有機系
材料の基板上に形成される回路を製作する際に用いる表
面実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to surface mounting methods used in the fabrication of hybrid integrated circuits and circuits formed on substrates of inorganic and organic materials.
従来の技術
最近、表面実装法は、軽薄短小の時代の要請に応えて、
ハイブリッドＩＣ及び一般の樹脂基板上に形成される回
路の実装などの分野で盛んに利用されるようになってき
た。この実装法は、たとえば電子技術１９８６年■ｏ’
−１２８，Ｎｏ、１４ の記載の構成によって知られ
ている。Conventional technology Recently, surface mounting method has been developed in response to the demands of the era of light, thin, short and small size.
It has become widely used in fields such as mounting hybrid ICs and circuits formed on general resin substrates. This implementation method is based on electronic technology 1986■o'
-128, No. 14, is known.
以下、第３図を参照して従来の表面実装法について説明
する。第３図は、両面実装に於ける基板、実装部材の断
面図に示すものである。図中、】０１は基板、１０２は
パターン、１０３はハンダ、１０４はチップ部品と呼ば
れるリード線のない受動部品、１０５は小型にパッケー
ジされ、短いリード線のついた半導体等の能動部品、ま
た１０６は接着剤であり両面を同時にハンダする時に下
側の部品が落下しないように固定する場合に用いるもの
である。The conventional surface mounting method will be explained below with reference to FIG. FIG. 3 is a cross-sectional view of the board and mounting member in double-sided mounting. In the figure, 01 is a substrate, 102 is a pattern, 103 is solder, 104 is a passive component without a lead wire called a chip component, 105 is an active component such as a semiconductor that is packaged into a small size and has a short lead wire, and 106 is an adhesive and is used to fix the lower parts to prevent them from falling when both sides are soldered at the same time.
両面型の表面実装された回路は以上のように構成されて
いる。The double-sided surface-mounted circuit is constructed as described above.
発明が解決しようとする課題
しかし、以上のような従来の構成では、回路の機能、性
能を向上させるだめに回路規模を大きくすれば、それに
従って基板も大きくする必要が′目じ、小型化の要望を
満足することが出来ないという課題があった。Problems to be Solved by the Invention However, with the conventional configuration as described above, if the circuit scale is increased in order to improve the function and performance of the circuit, the board must also be increased accordingly. There was a problem that it was not possible to satisfy the requests.
本発明は従来技術の以上のような課題を解決するもので
、回路規模を大きくしても、それに比例して、基板を大
きくする必要がなく、小型化の要望を（１１４足出来る
表面実装方法を提供することを目的とするものである。The present invention solves the above-mentioned problems of the conventional technology. Even if the circuit scale is increased, there is no need to increase the size of the board in proportion to the size of the circuit. The purpose is to provide the following.
課題を解決する／ζめの手段
本発明は、リード線をもつバクケージ状の部品を、ブー
ブ状の部品の上部に重ね、三次元的に実にすることによ
り、上記目的を達成するものである。The present invention achieves the above object by stacking a bag-shaped component having a lead wire on top of a boob-shaped component to form a three-dimensional structure.
作 用
本発明は、上記の構成とすることにより、テップ状の部
品を先ずハンダ付けし、その次にリード線をもつパッケ
ージ状の部品をマウントして、そのリード線を部分ハン
ダを行い三次元的に実装し、実装置ａｉ積を小型化する
ようにしたものである。Function: By having the above-described configuration, the present invention first solders a tip-shaped component, then mounts a package-shaped component having lead wires, and partially solders the lead wires to create a three-dimensional structure. It is designed to be implemented in a practical manner and to reduce the size of the actual device AI product.
実施例
以−下、図面を参照しながら本発明の１つの実施例につ
いて説明する。Embodiment Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の１つの実施例により製造された両面型
三次元表面実装回路の断面図である。FIG. 1 is a cross-sectional view of a double-sided three-dimensional surface mount circuit manufactured in accordance with one embodiment of the present invention.
図中１は、セラミック又は、樹脂から成る無機系又は、
有機系材料の基板、２は導電性材料から成るパターン、
３は）・ンダ、４はチップ）￥じ品、５はリード線７の
ついた半導体等のパッケージ部品、６は接着剤であって
テップ部品４、パッケージ部品５のハンダ付けを容易に
するために基板１とチップ部品４、パッケージ部品５を
固定するために用いられるものである。このようにチッ
プ部品４の上にリード線を持つパッケージ部品５を三次
元的に重ねることにより、実装面積を節約し、実装効率
を高めることができる。In the figure, 1 is an inorganic system made of ceramic or resin,
a substrate made of an organic material; 2 a pattern made of a conductive material;
3 is a chip), 4 is a chip), 5 is a package component such as a semiconductor with a lead wire 7, and 6 is an adhesive to facilitate soldering of the tip component 4 and the package component 5. It is used for fixing the substrate 1, chip components 4, and package components 5 to each other. By three-dimensionally stacking the package component 5 having lead wires on the chip component 4 in this way, the mounting area can be saved and the mounting efficiency can be increased.
第２図は、第１図での両面型三次元表面実装置【１路の
りフローソルダリングでの製造方法を示したものである
。プリント基板の裏面を一ト側にして、ハンダ付けする
ために裏面に実装されるチップ部品を固定する必要があ
る。そのために、先ず第２図（ｄ）に示すように裏面を
上側にして、チップ部品が装着される直下に接着剤６を
少量塗布する。FIG. 2 shows a manufacturing method for the double-sided three-dimensional surface-mounted device shown in FIG. 1 (one-way glue flow soldering). It is necessary to place the back side of the printed circuit board on one side and fix the chip components mounted on the back side for soldering. To do this, first, as shown in FIG. 2(d), with the back side facing up, a small amount of adhesive 6 is applied directly below where the chip component will be mounted.
又チップ部品が装着される直下のパターン２上に図のよ
うにソルダーペースト５０ を塗布する。次に第２図（
ｂ）に示すように、チップ部品・１を装着し、接着剤６
を紫外線硬化し、チップ部品４を固定する。次に第２図
（Ｃ）に示すように基板１の表面を上側に、チップ部品
４が装着される直下のパターン２上にソルダーペースト
５０ を塗布し２、チップ部品４を装着する。両［′ｆ
ｒＩに装着されたチップ部品４を第２図（ｄ）に示すよ
うにリフローソルダリング（赤外線、２３０℃、１分）
法等で加熱して、ソルダーペースト５０を溶融し、ハン
ダ付けする。Also, as shown in the figure, solder paste 50 is applied on the pattern 2 directly below where the chip component is to be mounted. Next, Figure 2 (
As shown in b), attach the chip part 1 and apply adhesive 6.
is cured with ultraviolet light to fix the chip component 4. Next, as shown in FIG. 2C, a solder paste 50 is applied onto the pattern 2 directly below where the chip component 4 is to be mounted, with the surface of the substrate 1 facing upward, and the chip component 4 is mounted thereon. both [′f
The chip component 4 mounted on the rI is subjected to reflow soldering (infrared rays, 230°C, 1 minute) as shown in FIG. 2(d).
The solder paste 50 is melted by heating using a method or the like and soldered.
次に、第２図（ｅ）に示すように基板１の裏面のリード
線を持つパッケージ部品が装着される直下の基板１上及
びチップ部品４上に接着剤６を塗布し、又、パッケージ
部品をリード線が装着される直下のパターン２上に、ソ
ルダーペースト５０を塗布する。次に第２図（「）に示
すようにパッケージ部品５をマウントし、接着剤を６を
硬化させ、パッケージ部品５を固定する。次に第２図（
ｇ）に示すように、先にハンダ付けされたテップ部品４
のハンダが溶融しないように、パッケージ部品５のリー
ド線のハンダ付は部品にのみ、レーザやパルスヒータ等
で１５０°Ｃ雰囲気加熱し、リード線７をハンダ付けす
る。次に表面ヘマウントされるパンケージ部品５につい
ても、裏面で行った工程と同様にして、接着剤６とソル
ダーペースト５０を塗布し、パッケージ部品５をマウン
トした後接着剤６を硬化し、パンケージ部品５を固定さ
せ、リード線７を部分ハンダして、第２図（ｈ）に示す
ようにして、両面型三次元表面実装回路を完成させる。Next, as shown in FIG. 2(e), an adhesive 6 is applied to the substrate 1 and the chip components 4 directly below where the package component with lead wires on the back side of the substrate 1 is mounted, and the package component Solder paste 50 is applied on the pattern 2 directly below where the lead wire is attached. Next, as shown in FIG. 2 (), mount the package component 5, cure the adhesive 6, and fix the package component 5. Next, as shown in FIG.
As shown in g), the tip part 4 soldered first
To prevent the solder from melting, the lead wires of the package component 5 are soldered only to the component by heating the component at 150.degree. C. with a laser, pulse heater, etc., and then soldering the lead wire 7. Next, for the pan cage component 5 to be mounted on the front surface, adhesive 6 and solder paste 50 are applied in the same manner as the process performed on the back surface, and after mounting the package component 5, the adhesive 6 is cured. are fixed, and the lead wires 7 are partially soldered to complete a double-sided three-dimensional surface mount circuit as shown in FIG. 2(h).
このように、チップ部品４の上にリード線７を持つパッ
ケージ部品５を三次元的に重ねることにより、実装面積
及び体積を節約し、実装効率を高めることができる。In this way, by three-dimensionally stacking the package component 5 having the lead wires 7 on the chip component 4, the mounting area and volume can be saved and the mounting efficiency can be increased.
なお、以上の説明では、リード線を持つパンケージ部品
を能動部品とした場合について説明［７たが、これは、
受動部品でもよく、又能動部品と受動部品との混成部品
でもよい。又テップ部品は受動商品としだが能動部品で
もよい。又、以上の説明では、ハンダ付けの方法をリフ
ローソルダリング法の場合について説明したが、ウェブ
ソルダリング及び他のハンダ付は方法でもよい。In addition, in the above explanation, we have explained the case where the pan cage part with the lead wire is used as the active part [7], but this is
It may be a passive component or a hybrid component of an active component and a passive component. In addition, the tip parts may be passive products, but they may also be active parts. Furthermore, in the above description, the soldering method was explained using a reflow soldering method, but web soldering and other soldering methods may be used.
発明の効果
以上のように本発明は、チップ状の部品をマウントしそ
の上に三次元的に、リード線を持つパッケージ部品をマ
ウントすることにより実装面積及び体積を節約でき、実
装効率を高めることができる。その結果、小型化が実現
できる。Effects of the Invention As described above, the present invention can save mounting area and volume and improve mounting efficiency by mounting a chip-shaped component and three-dimensionally mounting a package component with lead wires thereon. I can do it. As a result, miniaturization can be achieved.
第１図は本発明の１つの実施例における表面実装方法で
作られた表面実装回路の断面図、第２図（ａ） 、 （
１）） 、 （Ｃ） 、 （ｄ） 、 （ｅ） 、 （
ｆ） 、 （ｇ） 、 （ｈ）は、同実装方法を示す製
造工程図、第３図は従来の両面型表面実装回路の断面図
である。
ｌ・・基板、２・・パターン、３ ハンダ、４・・チッ
プ部品、５・・・パッケージ部品、６・・・接着剤、７
リード線。
代理人の氏名 弁理士 粟 野 重 孝 ほか１名図FIG. 1 is a cross-sectional view of a surface mount circuit made by a surface mount method in one embodiment of the present invention, and FIGS. 2(a), (
1)) , (C) , (d) , (e) , (
f), (g), and (h) are manufacturing process diagrams showing the same mounting method, and FIG. 3 is a cross-sectional view of a conventional double-sided surface mount circuit. l... Board, 2... Pattern, 3 Solder, 4... Chip parts, 5... Package parts, 6... Adhesive, 7
Lead. Name of agent: Patent attorney Shigetaka Awano and one other person
Claims (1)
前記チップ状部品の上から、リード線を有するパッケー
ジ部品をマウントすることを特徴とする表面実装方法。Chip-shaped parts are mounted two-dimensionally on the surface of the substrate,
A surface mounting method characterized in that a package component having lead wires is mounted from above the chip-shaped component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63166122A JPH0215697A (en) | 1988-07-04 | 1988-07-04 | Surface packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63166122A JPH0215697A (en) | 1988-07-04 | 1988-07-04 | Surface packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0215697A true JPH0215697A (en) | 1990-01-19 |
Family
ID=15825440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63166122A Pending JPH0215697A (en) | 1988-07-04 | 1988-07-04 | Surface packaging method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0215697A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100449626B1 (en) * | 2002-10-28 | 2004-09-22 | 삼성전기주식회사 | A power amplifier module assembly |
| JP2015035503A (en) * | 2013-08-09 | 2015-02-19 | 富士ゼロックス株式会社 | Printed circuit board, printed circuit board manufacturing method and printed circuit board design program |
-
1988
- 1988-07-04 JP JP63166122A patent/JPH0215697A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100449626B1 (en) * | 2002-10-28 | 2004-09-22 | 삼성전기주식회사 | A power amplifier module assembly |
| JP2015035503A (en) * | 2013-08-09 | 2015-02-19 | 富士ゼロックス株式会社 | Printed circuit board, printed circuit board manufacturing method and printed circuit board design program |
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