JPH02148764A - Analog master-slice ic - Google Patents
Analog master-slice icInfo
- Publication number
- JPH02148764A JPH02148764A JP63302101A JP30210188A JPH02148764A JP H02148764 A JPH02148764 A JP H02148764A JP 63302101 A JP63302101 A JP 63302101A JP 30210188 A JP30210188 A JP 30210188A JP H02148764 A JPH02148764 A JP H02148764A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- resist
- aluminum
- wirings
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000004544 sputter deposition Methods 0.000 claims abstract description 4
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 abstract description 6
- 238000005520 cutting process Methods 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000257465 Echinoidea Species 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明はアナグロマスタースライスＩＣの形成方法に関
するもので、リードタイムの短いセミカスタムＩＣの形
成に利用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for forming an analog master slice IC, and is used for forming a semi-custom IC with a short lead time.
（従来の技術）
本発明に係る従来技術としてアナグロマスタースライス
ＩＣ（富士通■、トムソン■製）があり、これらシュミ
レーションにより回路を決定しその後配線レイアウトを
作成するもので、その後アルミ配線をフォトマスクを作
成し、前処理のマスタースライスのウェハ上に露光する
、そしてアルミをリン酸等でエツチングし保護膜を形成
し、ポンディングパッドを孔明した後チップにダイシン
グで分割し、分割したチップをリードフレーム上又はセ
ラミックパッケージ上にダイボンドした後、銅線等でワ
イヤポンデイグを行い樹脂封止又はセラミックの蓋によ
る封止でＩＣを形成する方法である。(Prior Art) As a conventional technology related to the present invention, there is an analog master slice IC (manufactured by Fujitsu ■, Thomson ■), which determines the circuit through simulation and then creates the wiring layout. After creating and exposing the pre-processed master slice on the wafer, etching the aluminum with phosphoric acid to form a protective film, drilling the bonding pads, dividing into chips by dicing, and attaching the divided chips to the lead frame. This is a method of forming an IC by die bonding onto the top or ceramic package, then wire bonding with a copper wire or the like, and sealing with a resin or ceramic lid.
（発明が解決しようとする課題）
しかし前記ＩＣの形成方法は、ウニハエ程の通常の方法
であるためにコストは従来通り発生し、又チップ数もφ
４インチウェハで３×３Ｉｎ口のチップの場合約８００
個近くできる。(Problem to be solved by the invention) However, since the method for forming the IC is as usual as a sea urchin fly, the cost remains the same as before, and the number of chips is also φ
Approximately 800 for a 3 x 3 In hole chip on a 4 inch wafer
You can do almost as many.
しかしこの時点で特性が不良又は機能が不良の場合でも
、またフォトマスクから作成しなおす必要があり、リー
ドタイム、コストの面で非常にロスが発生し易いという
問題点がある。However, even if the characteristics or function are defective at this point, it is necessary to create a photomask again, which poses a problem in that it is very likely to cause losses in terms of lead time and cost.
本発明アナグロのマスタースライスＩＣにおいて、低コ
ストでかつ短期にチップを形成する方法を技術的課題と
するものである。In the analog master slice IC of the present invention, a technical problem is a method of forming a chip at low cost and in a short period of time.
（課題を解決するための手段）
前記課題を解決するために講じた技術的手段は次のよう
である。(Means for solving the problem) The technical means taken to solve the above problem are as follows.
マスタースライスＩＣにおいて、配線パターンをレジス
ト上にあらかじめ格子状に形成し、回路に合わせて格子
点等を部分露光後現像し、そのレジスト上にアルミ蒸着
又はスパッタを行いリフトオフにより配線を形成するか
、チップをパッケージ上に予め取り付けその後、回路に
合わせてアルミ配線パターンを形成する方法である。In a master slice IC, a wiring pattern is formed in advance on a resist in a lattice shape, lattice points, etc. are partially exposed and developed in accordance with the circuit, and aluminum evaporation or sputtering is performed on the resist and wiring is formed by lift-off, or In this method, a chip is mounted on a package in advance, and then an aluminum wiring pattern is formed to match the circuit.
（作用）
アルミ配線用の格子状のマスクパターンを露光したレジ
ストに組付、その後回路の決定した図面を基に格子点等
を部分露光し、リフトオフ法で蒸着した膜を配線として
形成する。(Function) A lattice-shaped mask pattern for aluminum wiring is attached to the exposed resist, and then lattice points, etc. are partially exposed based on the determined drawing of the circuit, and a film deposited by lift-off method is formed as wiring.
またシンターについてはパッケージ毎に酸化防止のため
、Ｎｚ ＋Ｈｚ、４５０℃程度で実施するものである。Furthermore, sintering is performed at about 450° C. at Nz +Hz to prevent oxidation for each package.
その後、ワイヤーボンディングを実施し、ポリイミド等
の樹脂の保護膜をつけ、蓋をし、即時ＩＣとして評価が
可能となるものである。もしこの時点で不具合が出た場
合でも、１チップ分のコストで再試作が可能となるもの
である。Thereafter, wire bonding is performed, a protective film of resin such as polyimide is applied, and a lid is placed, allowing immediate evaluation as an IC. If a problem occurs at this point, it is possible to reproduce the prototype at the cost of one chip.
（実施例） 以下実施例について説明する。(Example) Examples will be described below.
第１図に本実施例に比較した従来例のアナグロマスター
ＩＣの配線以降のフローを示し、第２図に本実施例のア
ナグロマスターＩＣの配線以降の工程フローを示す。FIG. 1 shows the process flow after wiring of the conventional analog master IC compared to this embodiment, and FIG. 2 shows the process flow after wiring of the analog master IC of this embodiment.
第３図の（イ）にアルミの格子パターンを示す。Figure 3 (a) shows the aluminum lattice pattern.
■はアナログＩＣチップで（ロ）は（イ）の拡大図で、
格子点等の部分露光をしめし、２は構成トランジスタで
あり、３は光照射されていないでレジストが除去される
部分で、４はスポット光φ１０μｍの照射で、レジスト
が硬化される部分で、５は光照射でレジストが硬化する
部分を示す。■ is an analog IC chip, (b) is an enlarged view of (a),
Partial exposure of lattice points, etc. is shown, 2 is a component transistor, 3 is a part where the resist is removed without being irradiated with light, 4 is a part where the resist is hardened by irradiation with a spot light of φ10 μm, and 5 indicates a portion where the resist is hardened by light irradiation.
第４図は紫外光のスポット照射を示し、６はセラミック
パッケージ、７はスポット光で、第５図はアルミ蒸着リ
フトオフ図で、８は基板、３はレジスト（硬化部）、１
０はアルミ膜である。Figure 4 shows spot irradiation with ultraviolet light, 6 is a ceramic package, 7 is a spot light, Figure 5 is a lift-off diagram of aluminum evaporation, 8 is a substrate, 3 is a resist (cured part), 1
0 is an aluminum film.
以下第２図のフローに基づいて本実施例の工程に説明す
る。The steps of this embodiment will be explained below based on the flow shown in FIG.
格子状のアルミ配線を予め、レジスト（０ＭＲ８５等）
に感光させたウェハをチップ切断し、セラミックパッケ
ージにグイポンドを行う。Apply resist (0MR85, etc.) to grid-shaped aluminum wiring in advance.
The exposed wafer is cut into chips and bonded to a ceramic package.
その後回路の決定したＩＣの配線レイアウトを配線の格
子及び隙間を切断することで成立するように配線削除パ
ターンを作成し、必要な場所にスポット径φ１０μｍ程
度の紫外光をスポット的に照射し、その部分のみレジス
トを除去する。After that, a wiring deletion pattern is created so that the IC wiring layout determined by the circuit is realized by cutting the wiring grid and gaps, and ultraviolet light with a spot diameter of about 10 μm is irradiated in spots at the required locations. Remove only part of the resist.
その後アルミを蒸着又はスパッタで膜付けする、リフト
オフ法により配線を形成する。Thereafter, wiring is formed by a lift-off method in which aluminum is deposited as a film by vapor deposition or sputtering.
その後Ｎｔ ＋）ｌ、の還元雰囲気中で、４５０℃程度
でシンターを行い、アルミとシリコンのオーミツトコン
タクトを形成する。Thereafter, sintering is performed at about 450° C. in a reducing atmosphere of Nt + )l to form an ohmic contact between aluminum and silicon.
そしてチップ電極とパッケージリードとワイヤボンディ
ングで接続し、ポリイミド等の樹脂で表面を保護し、蓋
によりパッケージソゲする。Then, the chip electrodes and package leads are connected by wire bonding, the surface is protected with resin such as polyimide, and the package is soldered with a lid.
これにより即時にセシカスタムｔＣの特性を評価できる
。又アナログＩＣの場合、電流を多（流す必要が生じる
が、格子の配線を並列に使用することで可能となるもの
である。This makes it possible to immediately evaluate the characteristics of Seshi Custom tC. Furthermore, in the case of an analog IC, it is necessary to pass a large amount of current, but this becomes possible by using grid wiring in parallel.
〔発明の効果〕
本発明は次の効果を有する。即ち、
変更の多い、又特性を一度の試作で作り込みにくいアナ
ログのマスタースライスｔＣの製法に於いて、本発明の
方法は低コストで短納期のチップの作製ができるもので
ある。[Effects of the Invention] The present invention has the following effects. That is, in the method of manufacturing an analog master slice TC, which is subject to many changes and whose characteristics are difficult to create in a single prototype, the method of the present invention can manufacture chips at low cost and in a short delivery time.
第１図は従来例の工程図、第２図は本実施例であるアナ
ログマスターｔＣの配線以降の工程フロー図、第３図の
（イ）は本実施例の格子状アルミパターンの図、（ロ）
は（イ）の要部の拡大図で格子点等の分露光の説明図、
第４図はセラミックパッケージのスポット照射の説明図
、第５図はアルミ蒸着のリフトオフ図である。
１・・・マスタースライス。
１０・・・アルミ膜。Fig. 1 is a process diagram of the conventional example, Fig. 2 is a process flow diagram after wiring of the analog master tC of this embodiment, and Fig. 3 (A) is a diagram of the lattice-shaped aluminum pattern of this embodiment. B)
is an enlarged view of the main part of (a), which is an explanatory diagram of the exposure of lattice points, etc.
FIG. 4 is an explanatory diagram of spot irradiation of a ceramic package, and FIG. 5 is a lift-off diagram of aluminum vapor deposition. 1... Master Slice. 10...Aluminum film.
Claims (2)
レジスト上にあらかじめ格子状に形成し、回路に合わせ
て格子点等を部分露後光現像し、そのレジスト上にアル
ミ蒸着又はスパッタを行いリフトオフにより配線を形成
する方法。(1) In a master slice IC, a wiring pattern is formed in a lattice shape on a resist in advance, the lattice points, etc. are partially exposed and photodeveloped in accordance with the circuit, aluminum evaporation or sputtering is performed on the resist, and the wiring is formed by lift-off. How to form.
チップをパッケージ上に予め取り付けその後、回路に合
わせてアルミ配線パターンを形成する方法。(2) In the master slice IC of claim 1,
A method in which the chip is mounted on the package in advance, and then an aluminum wiring pattern is formed to match the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63302101A JPH02148764A (en) | 1988-11-29 | 1988-11-29 | Analog master-slice ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63302101A JPH02148764A (en) | 1988-11-29 | 1988-11-29 | Analog master-slice ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02148764A true JPH02148764A (en) | 1990-06-07 |
Family
ID=17904943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63302101A Pending JPH02148764A (en) | 1988-11-29 | 1988-11-29 | Analog master-slice ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02148764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05114718A (en) * | 1991-02-19 | 1993-05-07 | Nec Corp | Programmable analog master |
-
1988
- 1988-11-29 JP JP63302101A patent/JPH02148764A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05114718A (en) * | 1991-02-19 | 1993-05-07 | Nec Corp | Programmable analog master |
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