JPH02146722A - Manufacture of quantum fine line - Google Patents
Manufacture of quantum fine lineInfo
- Publication number
- JPH02146722A JPH02146722A JP30030588A JP30030588A JPH02146722A JP H02146722 A JPH02146722 A JP H02146722A JP 30030588 A JP30030588 A JP 30030588A JP 30030588 A JP30030588 A JP 30030588A JP H02146722 A JPH02146722 A JP H02146722A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- plane
- substrate
- quantum well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000003776 cleavage reaction Methods 0.000 claims abstract description 25
- 230000007017 scission Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 description 21
- 230000004888 barrier function Effects 0.000 description 11
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 8
- 238000004943 liquid phase epitaxy Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005476 size effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体中に形成される量子細線の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing quantum wires formed in a semiconductor.
第２図は、従来の量子細線の製造方法を示す工程断面図
である。平面基板１上に量子井戸構造２をエピタキシャ
ル成長により形成しく第２図（Ａ）参照）、その上にス
トライプ状のマスクパターン３を形成する（第２図（Ｂ
）参照）。その後、このマスクパターンを用いて量子井
戸構造２の上層バリア層４を選択的にエツチングしく第
２図（Ｃ）参照）、さらに井戸層５を選択的にエツチン
グする（第２図（Ｄ）参照）。ついで、マスクパターン
３を除去しく第２図（Ｅ）参照）、バリア層４と同じ半
導体を用いて、細線状に残された井戸層５を埋め込み、
量子細線を形成する（第２図（Ｆ）参照）。FIG. 2 is a process cross-sectional view showing a conventional quantum wire manufacturing method. A quantum well structure 2 is formed on a flat substrate 1 by epitaxial growth (see FIG. 2(A)), and a striped mask pattern 3 is formed thereon (see FIG. 2(B)).
)reference). Thereafter, using this mask pattern, the upper barrier layer 4 of the quantum well structure 2 is selectively etched (see FIG. 2(C)), and the well layer 5 is further selectively etched (see FIG. 2(D)). ). Next, the mask pattern 3 is removed (see FIG. 2(E)), and the well layer 5 left in the form of a thin line is buried using the same semiconductor as the barrier layer 4.
A quantum wire is formed (see FIG. 2(F)).
しかし、ストライプ状のマスク３をパターンニングする
際にリソグラフィ技術を用いるため、量子サイズ効果を
得るのに十分な細いパターンニングを行うことが困難で
あった。However, since lithography technology is used when patterning the striped mask 3, it is difficult to perform patterning thin enough to obtain a quantum size effect.
また、量子井戸構造２をエツチングする場合、表面の損
傷を極力少なくするために通常はウェットエツチングを
用いる必要があるが、ウェットエツチングは制御性およ
び再現性の点で問題があった。特に、隣り合う量子細線
において、エツチングで形成した量子細線幅を原子層単
位（数Ａ単位）で均一にすることは、不可能に近い。し
たがって、得られる量子細線中の量子化されたエネルギ
準位が、互いに隣り合う細線で異なるという問題があっ
た。Further, when etching the quantum well structure 2, it is usually necessary to use wet etching in order to minimize damage to the surface, but wet etching has problems in terms of controllability and reproducibility. In particular, it is nearly impossible to make the width of quantum wires formed by etching uniform in atomic layer units (several amps) in adjacent quantum wires. Therefore, there is a problem in that the quantized energy levels in the obtained quantum wires differ between adjacent wires.
本発明の課題は、このような問題点を解消することにあ
る。An object of the present invention is to solve these problems.
上記課題を解決するために、本発明は、平面基板上に量
子井戸構造を持つ半導体層を形成した後、基板の平面に
垂直な方向にへき開し、その後、量子井戸構造を持つ半
導体層のうちの井戸層を構成する半導体の禁制帯を包含
する禁制帯を有する半導体を前記へき開面に成長するこ
とにより、量子細線を形成するものである。In order to solve the above problems, the present invention forms a semiconductor layer with a quantum well structure on a flat substrate, cleaves it in a direction perpendicular to the plane of the substrate, and then cleaves the semiconductor layer with a quantum well structure on a flat substrate. A quantum wire is formed by growing a semiconductor having a forbidden band including the forbidden band of the semiconductor constituting the well layer on the cleavage plane.
量子細線の長手方向に垂直な２方向の寸法のうち、１方
向は平面基板上の量子井戸構造を成長するときの精度で
決定され、もう一つの方向は、へき開時の精度で決定さ
れる。Of the two dimensions perpendicular to the longitudinal direction of the quantum wire, one direction is determined by the accuracy when growing a quantum well structure on a flat substrate, and the other direction is determined by the accuracy when cleaving.
一方、量子井戸構造は、分子線エピタキシー（ＭＢＥ）
法や有機金属気相成長（ＯＭＶＰＥ）法などの方法で、
単原子層程度の精度で平坦なヘテロ界面が形成される。On the other hand, the quantum well structure is created using molecular beam epitaxy (MBE).
method, metal organic vapor phase epitaxy (OMVPE) method, etc.
A flat heterointerface is formed with an accuracy comparable to that of a monoatomic layer.
また、へき開で形成される面も、単原子層の精度で平坦
となる。Furthermore, the surface formed by cleavage is also flat with the precision of a monoatomic layer.
したがって、本発明によって得られる量子細線は、隣り
合う量子細線の間で寸法の違いがほとんど無く、そのた
めに、量子細線中の量子化されたエネルギ準位がほとん
ど一定となる。Therefore, in the quantum wire obtained by the present invention, there is almost no difference in size between adjacent quantum wires, and therefore the quantized energy level in the quantum wire is almost constant.
第２図は、本発明の一実施例を示す工程斜視図である。 FIG. 2 is a process perspective view showing an embodiment of the present invention.
なお、図における寸法比率は、見易さを優先しているた
めに、必ずしも実際の寸法比率と合致していない。Note that the dimensional ratios in the figures do not necessarily match the actual dimensional ratios because priority is given to ease of viewing.
ＩｎＰ基板ｌＯの（１００）面上に、１００Ａ程度の厚
さのＧａ Ｉ ｎＡｓ層とＩｎＰ層を交互に複数回重ね
た多重量子井戸構造１１をＯＭＶＰＥ法により成長し、
その上にＩｎＰ層１２を厚く形成する（第１図（Ａ）参
照）。なお、ＩｎＰの禁制帯は、Ｇａ１ｎＡｓの禁制帯
を包含しているため、量子井戸構造１１のうち、Ｇａ
Ｉ ｎＡｓ層が井戸層となり、ＩｎＰ層がバリア層とな
る。A multi-quantum well structure 11 in which Ga InAs layers and InP layers each having a thickness of about 100 A are alternately stacked multiple times is grown on the (100) plane of an InP substrate lO by the OMVPE method.
A thick InP layer 12 is formed thereon (see FIG. 1(A)). In addition, since the forbidden band of InP includes the forbidden band of Ga1nAs, in the quantum well structure 11, Ga
The InAs layer becomes a well layer, and the InP layer becomes a barrier layer.
つぎに、この量子井戸構造１１が形成されたＩｎＰ基板
１０を、（０１１）面でへき開する（第１図（Ｂ）参照
）。そして、へき開面に、まずＯＭＶＰＥ法でＩｎＰを
数μｍ程度成長した後、さらに、液相エピタキシー（Ｌ
Ｐ Ｅ）法により、ＩｎＰを５０〜１００μｍ成長し
て、ＩｎＰ成長層１３を形成する（第１図（Ｃ）参照）
。ＩｎＰ成長層１３を、ＯＭＶＰＥ法とＬＰＥ法の２種
類の方法を用いて形成するのはつぎの理由による。Next, the InP substrate 10 on which the quantum well structure 11 is formed is cleaved along the (011) plane (see FIG. 1(B)). Then, after first growing InP to several μm on the cleavage plane using the OMVPE method, further liquid phase epitaxy (L
InP is grown to a thickness of 50 to 100 μm using the PE method to form an InP growth layer 13 (see FIG. 1(C)).
. The reason why the InP growth layer 13 is formed using two methods, the OMVPE method and the LPE method, is as follows.
すなわち、ＬＰＥ法は成長速度が速いという利点を有す
るものの、へき開面をメルトバックしてしまうという欠
点を有するため、最初からＬＰＥ法を用いてＩｎＰを成
長させると、単原子層の精度で平坦となっているへき開
面の平坦性が失われてしまう。一方、ＯＭＶＰＥ法は、
へき開面の平坦性を保存しつつＩｎＰの成長を達成する
ことができるが、その成長速度が遅い。そこで、画成長
方法の欠点を相殺しつつそれぞれの利点を生かし、最初
にＯＭＶＰＥ法で薄い膜を形成し、その後ＬＰＥ法で厚
くしている。この場合、ＯＭＶＰＥ法に代えてＭＢＥ法
を用いても同様のメリットが得られる。In other words, although the LPE method has the advantage of a fast growth rate, it has the disadvantage of melting back the cleavage plane, so if you grow InP using the LPE method from the beginning, you will not be able to grow InP with the precision of a single atomic layer. The flatness of the cleavage plane is lost. On the other hand, the OMVPE method
Although InP growth can be achieved while preserving the flatness of the cleavage plane, the growth rate is slow. Therefore, by taking advantage of the advantages of each of the image growth methods while offsetting their drawbacks, a thin film is first formed using the OMVPE method, and then thickened using the LPE method. In this case, similar advantages can be obtained by using the MBE method instead of the OMVPE method.
つぎに、量子井戸構造１１の幅Ａが１００〜２００八程
度となるように、量子井戸構造１１が形成されているＩ
ｎＰ基板１１を（０１１）面で再びへき開する（第１図
（Ｄ）参照）。そして、最後に、この第２のへき開面に
ＯＭＶＰＥ法により、数μｍのＩｎＰ層１４を成長する
ことにより、ＩｎＰで囲まれたＧａ Ｉ ｎＡｓの量子
細線が形成される（第１図（Ｅ）参照）。Next, I
The nP substrate 11 is again cleaved along the (011) plane (see FIG. 1(D)). Finally, by growing an InP layer 14 of several micrometers on this second cleavage plane by OMVPE, a quantum wire of GaInAs surrounded by InP is formed (Fig. 1(E)). reference).
なお、本実施例では量子細線をＧａ Ｉ ｎＡｓ、量子
細線を囲むバリア層をＩｎＰとしたが、材料はこれに限
定されるものではなく、量子細線を構成する半導体の禁
制帯がバリア層を構成する半導体の禁制帯に包含される
ような関係にあれば良い。In this example, the quantum wire was made of GaInAs, and the barrier layer surrounding the quantum wire was InP, but the material is not limited to these, and the forbidden band of the semiconductor that makes up the quantum wire makes up the barrier layer. It is sufficient if the relationship is included in the forbidden band of the semiconductor.
このような関係を有するものとして、たとえば、量子細
線にＧａＡｓ、バリア層にＡ、ＱＧａＡｓを用いたもの
などが挙げられる。また、量子細線の周囲のバリア層を
全て同じ材料で構成する必要はなく、上記の禁制帯の関
係を満足する材料であれば、量子細線の上下のバリア層
と左右のバリア層の材料が相違していてもよい。Examples of materials having such a relationship include those using GaAs for the quantum wire and A or QGaAs for the barrier layer. In addition, it is not necessary that all the barrier layers around the quantum wire be made of the same material; as long as the material satisfies the above forbidden band relationship, the barrier layers above and below the quantum wire and the barrier layers on the left and right can be made of different materials. You may do so.
また、本実施例では、第１のへき開面を形成した後、そ
のへき開面にバリア層となる成長層を形成し、その後、
第１のへき開面に平行に第２のへき開面を形成し、その
上にバリア層となる成長層を形成しているが、２つのへ
き開面を初めに形成してから、両へき開面にバリア層を
成長させてもよい。Furthermore, in this example, after forming the first cleavage plane, a growth layer serving as a barrier layer is formed on the cleavage plane, and then,
A second cleavage plane is formed parallel to the first cleavage plane, and a growth layer that becomes a barrier layer is formed on top of the second cleavage plane. Layers may be grown.
以上説明したように、本発明の量子細線の製造方法によ
れば、量子細線の長手方向に垂直な２方向の寸法のうち
、１方向は平面基板上の量子井戸構造を成長するときの
精度で決定され、もう一つの方向は、へき開時の精度で
決定されるので、いずれの方向の寸法も単原子層程度の
精度で制御できる。したがって、本発明により製造され
た量子細線は、量子細線中の量子化されたエネルギが一
定かつ急峻となり、これを用いたデバイスの性能向上に
大きく貢献する。As explained above, according to the quantum wire manufacturing method of the present invention, one of the dimensions in two directions perpendicular to the longitudinal direction of the quantum wire has the precision required when growing a quantum well structure on a flat substrate. Since the other direction is determined by the precision at the time of cleavage, the dimensions in either direction can be controlled with precision comparable to that of a monoatomic layer. Therefore, in the quantum wire manufactured according to the present invention, the quantized energy in the quantum wire is constant and steep, which greatly contributes to improving the performance of devices using the quantum wire.
第１図は、本発明の一実施例を示す工程斜視図、第２図
は、従来の量子細線の製造方法を示す工程断面図である
。
１０・・・ＩｎＰ基板、１１・・・量子井戸構造、１３
．１４・・・ＩｎＰ成長層。
特許出願人 住友電気工業株式会社FIG. 1 is a process perspective view showing an embodiment of the present invention, and FIG. 2 is a process cross-sectional view showing a conventional quantum wire manufacturing method. 10... InP substrate, 11... quantum well structure, 13
．． 14...InP growth layer. Patent applicant: Sumitomo Electric Industries, Ltd.
Claims (1)
る工程と、 前記基板の平面に垂直な方向にへき開して前記量子井戸
構造を持つ半導体層を細線化する工程と、前記量子井戸
構造を持つ半導体層のうちの井戸層を構成する半導体の
禁制帯を包含する禁制帯を有する半導体を前記へき開面
に成長する工程とを備えた量子細線の製造方法。 ２、平面基板上に量子井戸構造を持つ半導体層を形成す
る工程と、 前記基板の平面に垂直な方向に第１のへき開面を形成す
る工程と、 前記量子井戸構造を持つ半導体層のうちの井戸層を構成
する半導体の禁制帯を包含する禁制帯を有する半導体を
前記第１のへき開面に成長する工程と、 前記第１のへき開面に平行な第２のへき開面を形成する
ことにより前記量子井戸構造を持つ半導体層を細線化す
る工程と、 前記量子井戸構造を持つ半導体層のうちの井戸層を構成
する半導体の禁制帯を包含する禁制帯を有する半導体を
前記第２のへき開面に成長する工程と を備えた量子細線の製造方法。[Claims] 1. A step of forming a semiconductor layer having a quantum well structure on a flat substrate, and a step of cleaving the semiconductor layer having a quantum well structure into thin wires by cleaving in a direction perpendicular to the plane of the substrate. and growing a semiconductor having a forbidden band including a forbidden band of a semiconductor constituting a well layer of the semiconductor layer having a quantum well structure on the cleavage plane. 2. A step of forming a semiconductor layer having a quantum well structure on a flat substrate; a step of forming a first cleavage plane in a direction perpendicular to the plane of the substrate; a step of growing a semiconductor having a forbidden band including a forbidden band of the semiconductor constituting the well layer on the first cleavage plane; and forming a second cleavage plane parallel to the first cleavage plane. A step of thinning a semiconductor layer having a quantum well structure, and forming a semiconductor having a forbidden band including a forbidden band of a semiconductor constituting a well layer in the semiconductor layer having a quantum well structure on the second cleavage plane. A method for producing a quantum wire, comprising a growing step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30030588A JPH02146722A (en) | 1988-11-28 | 1988-11-28 | Manufacture of quantum fine line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30030588A JPH02146722A (en) | 1988-11-28 | 1988-11-28 | Manufacture of quantum fine line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02146722A true JPH02146722A (en) | 1990-06-05 |
Family
ID=17883180
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30030588A Pending JPH02146722A (en) | 1988-11-28 | 1988-11-28 | Manufacture of quantum fine line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02146722A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011045944A (en) * | 2009-08-26 | 2011-03-10 | National Institute For Materials Science | Nanoribbon and manufacturing method thereof, fet using nanoribbon and manufacturing method thereof, and base sequence determination method using nanoribbon and apparatus for the same |
-
1988
- 1988-11-28 JP JP30030588A patent/JPH02146722A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011045944A (en) * | 2009-08-26 | 2011-03-10 | National Institute For Materials Science | Nanoribbon and manufacturing method thereof, fet using nanoribbon and manufacturing method thereof, and base sequence determination method using nanoribbon and apparatus for the same |
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