JPH02141852A - Input circuit - Google Patents
Input circuitInfo
- Publication number
- JPH02141852A JPH02141852A JP63296666A JP29666688A JPH02141852A JP H02141852 A JPH02141852 A JP H02141852A JP 63296666 A JP63296666 A JP 63296666A JP 29666688 A JP29666688 A JP 29666688A JP H02141852 A JPH02141852 A JP H02141852A
- Authority
- JP
- Japan
- Prior art keywords
- input
- inverter
- mosfet
- threshold
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
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- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は入力回路に関し、特にその入力回路の論理しき
い値が通常のＣＭＯ８論理回路より高くなるように改良
した入力回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input circuit, and more particularly to an input circuit improved so that the logic threshold of the input circuit is higher than that of a normal CMO8 logic circuit.
従来の入力回路は第２図に示すように、入力にゲートと
ドレインを短絡したＮＭＯ３ＦＥＴ Ｍｌｌを接続し
、ソースと接地電圧の間に負荷素子Ｌ１をつなぎ、この
ソース電圧をインバータエ、の入力とし、インバータエ
、の出力がこの入力回路の出力となる。As shown in Figure 2, the conventional input circuit connects an NMO3FET Mll whose gate and drain are shorted to the input, connects a load element L1 between the source and ground voltage, and uses this source voltage as the input of the inverter. , inverter, becomes the output of this input circuit.
次にこの回路の動作を説明する。第３図は各回路素子の
論理しきい値の電源電圧依存性を表わしている。まず、
インバータエ、は通常のＣＭＯＳインバータでその論理
しきい値が電源電圧に比例して変化し直線３１で示され
る特性となる。入力とインバータエ、の間にはある一定
の電圧降下を起こす素子がある。ここではゲートとドレ
インを短絡したＮＭＯ８ＦＥＴ Ｍｌｌを使用してい
るからこのＮＭＯ８ＦＥＴ Ｍｌｌのしきい値分の電
圧Ｖ１２が生じる。この電圧と前に説明したインバータ
エ、の論理しきい値電圧の和が第２図の入力回路のしき
い値となる。ここではＮＭＯＳ Ｆ ＥＴＭＩＩに働く
バックゲートバイアスにより生ずるしきい値の上昇があ
る為、ＮＭＯ３ＦＥＴＭｌｌのソース電圧が高くなるに
つれＶＳ２が増して直線３３で示される特性となる。Next, the operation of this circuit will be explained. FIG. 3 shows the power supply voltage dependence of the logic threshold of each circuit element. first,
The inverter is a normal CMOS inverter whose logical threshold value changes in proportion to the power supply voltage, and has a characteristic shown by a straight line 31. There is an element that causes a certain voltage drop between the input and the inverter. Since an NMO8FET Mll whose gate and drain are short-circuited is used here, a voltage V12 corresponding to the threshold value of the NMO8FET Mll is generated. The sum of this voltage and the logic threshold voltage of the inverter described above becomes the threshold of the input circuit of FIG. Here, since there is a rise in the threshold value caused by the back gate bias acting on the NMOS FET MII, as the source voltage of the NMOS FET Mll increases, VS2 increases, resulting in the characteristic shown by the straight line 33.
上述した従来の入力回路は通常のＭＯＳＦＥＴを使った
入力回路の入力インピーダンスが１０６Ω以上と非常に
高いのに対して負荷素子Ｌ１により決まる電流が入力に
流れてしまう。一般に入力回路の入力インピーダンスは
高ければ高いほど良いとされる為負荷素子Ｌ１のインピ
ーダンスはあまり小さくできない。ところが負荷素子Ｌ
１のインピーダンスが大きいとインバータエ、の入力部
につく浮遊容量を充電する時はＮＭＯ８ＦＥＴＭｌｌの
オン抵抗を十分低い値にするようトランジスタの大きさ
を決められるから問題ない。これはＭｌｌがしきい値の
電位差を作る事が目的だからである。しかし放電する時
は負荷素子側にしか電流が流れない為時定数が大きくな
りスイッチング時間が長くかかるという欠点がある。In the conventional input circuit described above, a current determined by the load element L1 flows into the input, whereas the input impedance of the input circuit using a normal MOSFET is very high at 10<6>Ω or more. Generally, it is said that the higher the input impedance of the input circuit, the better, so the impedance of the load element L1 cannot be made very small. However, load element L
If the impedance of 1 is large, there is no problem when charging the stray capacitance attached to the input part of the inverter because the size of the transistor can be determined so that the on-resistance of NMO8FET Mll is set to a sufficiently low value. This is because the purpose of Mll is to create a threshold potential difference. However, when discharging, current flows only to the load element side, so the time constant becomes large and the switching time takes a long time.
本発明の入力回路はゲートとドレインを短絡しドレイン
側を入力とした第１のＭＯＳＦＥＴと、一端を接地され
た負荷素子とを具備する入力回路において、前記第１の
ＭＯＳＦＥＴと並列に第１のＭＯＳＦＥＴの同導電型の
ＭＯＳＦＥＴをつなぎそのゲートはソース側につないだ
事を特徴とするものである。The input circuit of the present invention includes a first MOSFET whose gate and drain are short-circuited and whose drain side is input, and a load element whose one end is grounded. It is characterized in that MOSFETs of the same conductivity type are connected and their gates are connected to the source side.
第１図は本発明の実施例の回路図で、入力はソースとド
レインを短絡したＮＭＯ８ＦＥＴ ＭｌとＮＭＯ３Ｆ
ＥＴ Ｍ２のドレインに接続され、ＮＭＯ８ＦＥＴ
ＭｌのソースとＮＭＯ８ＦＥＴＭ２のソースとゲート
をそれぞれ接続し接地電圧との間に負荷素子り、を接続
しこの点をインバータエ、の入力と接続しこのインバー
タの出力を本人力回路の出力とする。Figure 1 is a circuit diagram of an embodiment of the present invention, where the inputs are NMO8FET Ml and NMO3F with their sources and drains shorted.
Connected to the drain of ET M2, NMO8FET
The source of Ml and the source and gate of NMO8FETM2 are connected respectively, and a load element is connected between the ground voltage and the input of an inverter, and the output of this inverter is used as the output of the main power circuit.
つぎにこの回路の動作を説明する。入力回路としての動
作は入力の変化がインバータエ、の入力側に付く浮遊容
量と負荷素子Ｌ１のインピーダンスで決まる時定数τよ
り十分遅い場合は従来例と同様インバータエ、の論理し
きい値よりＮＭＯ３ＦＥＴ Ｍｌのしきい値分高い入
力が入るとインバータＩ、の出力が変化する。Next, the operation of this circuit will be explained. As for the operation as an input circuit, if the input change is sufficiently slower than the time constant τ determined by the stray capacitance attached to the input side of the inverter and the impedance of the load element L1, the NMO3FET When an input that is higher than the threshold value of M1 is input, the output of the inverter I changes.
つぎに入力される信号が早い場合で変化“ｌ”→“０”
の時を考えるとインバータ１１の入力側は時定数τに従
ってゆっくり変化するが入力との電位差ＶＩ２がＮＭＯ
３ＦＥＴ Ｍ２のしきい値を越えるとＮＭＯ８ＦＥＴ
Ｍ２がオンし入力との電位差 Ｖ、２＝−（ＮＭＯ
８ＦＥＴ Ｍ２のしきい値）を保ったまま“０”へ変
化する。この時ＮＭＯ３ＦＥＴ Ｍ２のしきい値く
インバータエ、の論理しきい値
とすれば入力がいくら早く変化しても本人力回路の出力
は入力の変化に追従して変化する。When the next input signal is fast, it changes from “l” to “0”
Considering the case when , the input side of the inverter 11 changes slowly according to the time constant τ, but the potential difference VI2 with the input
3FET When the threshold of M2 is exceeded, NMO8FET
M2 turns on and the potential difference with the input is V, 2=-(NMO
The threshold value of 8FET M2) is maintained and changes to "0". At this time, if the threshold value of the NMO3FET M2 is the logical threshold value of the inverter, no matter how quickly the input changes, the output of the self-powered circuit will change to follow the change in the input.
また入力が“０”→“ｌ”に変化する時はそもそもＮＭ
Ｏ３ＦＥＴ Ｍｌのオン抵抗が負荷素子Ｌｌのインピ
ーダンスより低くなるようにしてありかつ、いくらオン
抵抗を低くしても良いので必要なスピードが確保できる
ようなトランジスタの大きさを選べる。もしＮＭＯ３Ｆ
ＥＴ Ｍｌのオン抵抗が負荷素子Ｌ１のインピーダン
スより太きいとインバータ■１の入力が上がらない為こ
の回路自体が動作しない。Also, when the input changes from “0” to “l”, the NM
The on-resistance of the O3FET Ml is set to be lower than the impedance of the load element Ll, and since the on-resistance can be lowered as much as possible, the size of the transistor can be selected to ensure the required speed. If NMO3F
If the on-resistance of ET Ml is greater than the impedance of load element L1, the input of inverter 1 will not rise, and this circuit itself will not operate.
第４図は本発明の他の実施例で入力はゲートとドレイン
を短絡したＮＭＯ３ＦＥＴ ＭｌとＮＭＯ３ＦＥＴ
Ｍ２のドレインに接続されＭｌ、Ｍ２のそれぞれのソ
ースとＭ２のゲートは接続されＰＭＯ８ＦＥＴ Ｍ３
のソースにつながる。Ｍ３のゲートは接地されドレイン
は接地電圧との間に負荷素子Ｌ１を接続しこの接続点に
インバータエ、の入力をつなぎ、このインバータの出力
を本人力回路の出力とする。Figure 4 shows another embodiment of the present invention, where the input is an NMO3FET Ml and an NMO3FET with the gate and drain shorted.
PMO8FET M3 is connected to the drain of M2, and the sources of M1 and M2 are connected to the gate of M2.
leads to the source. A load element L1 is connected between the gate of M3 and the ground voltage, and the input of an inverter is connected to this connection point, and the output of this inverter is used as the output of the personal power circuit.
つぎにこの回路の動作を第３図を使って説明する。まず
インバータエ、は通常のＣＭＯＳインバータでその論理
しきい値は電源電圧に比例し変化し直線３１で示される
特性となる。入力とインバータ１１の間にはある電圧降
下を起こす素子がある。１つはゲートとドレインを短絡
したＮＭＯ３ＦＥＴ Ｍｌで、このしきい個分ソース
側がドレイン側より低くなる。もう１つはＮＭＯＳ Ｆ
ＥＴ Ｍｌのソースと負荷素子Ｌ１の間にあるＰＭ
０８ＦＥＴ Ｍ３で、ゲートが接地電圧の為ソース・
ゲート間にこのＰＭＯ８ＦＥＴ Ｍ３のしきい値以上
の電圧が加わらない限りオンしない。Next, the operation of this circuit will be explained using FIG. First, the inverter is a normal CMOS inverter whose logical threshold value changes in proportion to the power supply voltage and has a characteristic shown by a straight line 31. There is an element between the input and the inverter 11 that causes a certain voltage drop. One is an NMO3FET Ml whose gate and drain are shorted, and the source side is lower than the drain side by this threshold. The other is NMOS F
PM between the source of ET Ml and load element L1
08FET M3, the gate is grounded voltage, so the source
It will not turn on unless a voltage higher than the threshold of this PMO8FET M3 is applied between the gates.
従ってＮＭＯ３ＦＥＴ Ｍｌにはこの分バックバイア
スされひわけだからしきい値はさらに増す。Therefore, the NMO3FET Ml is back biased by this amount, so the threshold value further increases.
従って曲線３２で示すように低い電源電圧の時でも、
■、。＝ （ＰＭＯ３ＦＥＴ Ｍ３のしきい値）＋（
ＮＭＯ３ＦＥＴ Ｍｌのしきい値
（ＰＭＯ３ＦＥＴ Ｍ３のしきい値分のバックバイア
ス有’）））・・・・・・（１）の電圧以下にはこの入
力回路の論理しきい値は下がらない事になり、かつ電源
が高くなりＰＭＯ５ＦＥＴ Ｍ３がオンしても抵抗と
して働らく為、ＮＭＯ８ＦＥＴ Ｍｌには従来より余
分にバックゲートバイアスが加わり、本実施例のほうが
高い論理しきい値を示す。Therefore, as shown by curve 32, even when the power supply voltage is low, (1). = (Threshold value of PMO3FET M3) + (
Threshold value of NMO3FET Ml (with back bias equivalent to the threshold value of PMO3FET M3)))...The logic threshold value of this input circuit will not fall below the voltage in (1). , and even if the power supply becomes high and the PMO5FET M3 is turned on, it acts as a resistor, so an extra back gate bias is applied to the NMO8FET M1 compared to the conventional one, and this embodiment shows a higher logic threshold.
また（１）式で示すようにそれぞれのＭＯＳＦＥＴのし
きい値をイオン注入により高く設定したり低く設定した
りする事により誤動作しない電圧を選ぶ事も可能でさら
にＮＭＯ８ＦＥＴ Ｍｌを２個以上直列に接続する事
によりＮＭＯ８ＦＥＴ Ｍｌのしきい値を上げると同
じ効果を得ることもできる。ＮＭＯ８ＦＥＴ Ｍｌは
入力が下がった時ソース側の電位をドレイン側の電位よ
りしきい値分高い電位にする事で“１″→“０″に入力
が変化した時にＭｌ、Ｍｌのソース側の電荷を抜き取り
回路が高速にスイッチングできる。In addition, as shown in equation (1), it is possible to select a voltage that will not malfunction by setting the threshold value of each MOSFET higher or lower by ion implantation, and furthermore, two or more NMO8FETs Ml can be connected in series. The same effect can be obtained by increasing the threshold of NMO8FET M1 by doing this. NMO8FET Ml makes the potential on the source side a threshold value higher than the potential on the drain side when the input drops, so that when the input changes from "1" to "0", the charge on the source side of Ml and Ml is reduced. The extraction circuit can switch at high speed.
なお、直線３４は論理しきい値が電源電圧と同じ場合で
この入力回路の論理しきい値がこの線より下がると普通
のインバータを使用した入力回路と同じ動作をしてしま
う。Note that the straight line 34 indicates the case where the logic threshold value is the same as the power supply voltage, and if the logic threshold value of this input circuit falls below this line, the input circuit will operate in the same way as an input circuit using an ordinary inverter.
第５図は本発明のさらに他の実施例の回路図で、入力は
ゲートとドレインと短絡したＮＭＯＳ Ｆ ＥＴ Ｍ
ｌとＮＭＯ３ＦＥＴ Ｍｌのドレインに接続されＭｌ
、ＭｌのそれぞれのソースとＭｌのゲートは接続されＮ
ＭＯ８ＦＥＴ Ｍ４のドレインにつながりこのゲート
はＶＤＤにつながる。Ｍ４のソースはＰＭＯ３ＦＥＴ
Ｍ５のソースとつながりゲートは接地されＮウェルは
ＶＤＤとつながる。FIG. 5 is a circuit diagram of still another embodiment of the present invention, in which the input is an NMOS FET M whose gate and drain are shorted.
connected to the drain of NMO3FET Ml and Ml
, Ml and the gate of Ml are connected N
It is connected to the drain of MO8FET M4 and its gate is connected to VDD. M4 source is PMO3FET
It is connected to the source of M5, its gate is grounded, and its N well is connected to VDD.
Ｍ５のドレインは接地電圧との間に負荷素子Ｌ１を接続
しこの接続点にインバータ１１の入力をつなぎ、このイ
ンバータの出力を本人力回路の出力とする。A load element L1 is connected between the drain of M5 and the ground voltage, and the input of an inverter 11 is connected to this connection point, and the output of this inverter is used as the output of the personal power circuit.
動作は前述の実施例と同じだがゲートが電源とつながっ
たＮＭＯ３ＦＥＴ Ｍ４がある為このソース電位Ｖｃ
はｖｃ＝電源電圧−Ｍ４のしきい値（Ｖｃ分のバックバ
イアスがかかっている。）となりＰＭＯ８ＦＥＴ Ｍ
５のＮウェル電圧が電源につながっている為、この分の
バックバイアスＶ。が加わりＰＭＯ８ＦＥＴ Ｍ５の
しきい値が上昇し、式（１）かられかるように、この入
力回路のしきい値も上昇する。従ってＮＭＯ３ＦＥＴ
Ｍ４のしきい値を変えてもこの入力回路のしきい値を
変える事ができる。The operation is the same as the previous embodiment, but since there is an NMO3FET M4 whose gate is connected to the power supply, this source potential Vc
is vc = power supply voltage - threshold of M4 (back bias equal to Vc is applied), and PMO8FET M
Since the N-well voltage of 5 is connected to the power supply, the back bias V is for this amount. As a result, the threshold of PMO8FET M5 increases, and as can be seen from equation (1), the threshold of this input circuit also increases. Therefore, NMO3FET
The threshold value of this input circuit can also be changed by changing the threshold value of M4.
またこの回路はＰＭＯ３ＦＥＴ Ｍ５のＮウェルがｖ
ＤＤに固定されおりかつＭ５のソースは入力にいくら高
い電圧が加わっても（ＶヤーｖＴ（ＮＭＯ３ＦＥＴ
Ｍ４のしきい値））より高くならないので第４図の例に
対しＰＭＯ８ＦＥＴ Ｍ５の耐圧は通常のＰＭＯ８Ｆ
ＥＴと同じで良い。Also, in this circuit, the N well of PMO3FET M5 is
The source of M5 is fixed to DD and no matter how high the voltage is applied to the input (V
The withstand voltage of PMO8FET M5 is the same as that of normal PMO8F in contrast to the example shown in Figure 4.
Same as ET.
以上説明したように本発明は入力が“１”→“０”に変
化する時のスピードを従来にくらべ大幅に早める効果が
ある。As explained above, the present invention has the effect of greatly increasing the speed at which the input changes from "1" to "0" compared to the conventional method.
第１図は本発明の一実施例図、第２図は従来例図、第３
図は第１図と第２図の特性図、第４図は本発明の他の実
施例図、第５図は本発明のさらに他の実施例図である。
Ｍ＋ ｒ Ｍｌ ｒ Ｍ４ｒ Ｍ＋ ＋・・・・・・Ｎ
ＭＯ３ＦＥＴ、Ｍ、。
Ｍ５・・・・・・ＰＭＯ３ＦＥＴ％ １１・・・・・・
インバータ、Ｌｌ・・・・・・負荷素子。
代理人 弁理士 内 原 晋
等
図
芽
回Figure 1 is a diagram of an embodiment of the present invention, Figure 2 is a diagram of a conventional example, and Figure 3 is a diagram of a conventional example.
The figures are characteristic diagrams of FIGS. 1 and 2, FIG. 4 is a diagram of another embodiment of the present invention, and FIG. 5 is a diagram of still another embodiment of the present invention. M+ r Ml r M4r M+ +・・・・・・N
MO3FET, M. M5...PMO3FET% 11...
Inverter, Ll...Load element. Agent: Patent Attorney Susumu Uchihara
Claims (1)
のＭＯＳＦＥＴと一端が基準点に接続された負荷素子と
を有する入力回路において、前記第１のＭＯＳＦＥＴと
並列に第１のＭＯＳＦＥＴと同導電型の第２のＭＯＳＦ
ＥＴをつなぎそのゲートはソース側につなぐ事を特徴と
する入力回路。The first one with the gate and drain shorted and the drain side input.
In an input circuit including a MOSFET and a load element whose one end is connected to a reference point, a second MOSFET of the same conductivity type as the first MOSFET is connected in parallel with the first MOSFET.
An input circuit characterized by connecting ET and its gate to the source side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63296666A JP2751265B2 (en) | 1988-11-22 | 1988-11-22 | Input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63296666A JP2751265B2 (en) | 1988-11-22 | 1988-11-22 | Input circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02141852A true JPH02141852A (en) | 1990-05-31 |
| JP2751265B2 JP2751265B2 (en) | 1998-05-18 |
Family
ID=17836505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63296666A Expired - Lifetime JP2751265B2 (en) | 1988-11-22 | 1988-11-22 | Input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2751265B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4917656A (en) * | 1972-06-05 | 1974-02-16 | ||
| JPS54158156A (en) * | 1978-06-05 | 1979-12-13 | Toshiba Corp | Schmitt trigger circuit |
| JPS6264121A (en) * | 1985-09-13 | 1987-03-23 | Toshiba Corp | Field effect transistor circuit |
-
1988
- 1988-11-22 JP JP63296666A patent/JP2751265B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4917656A (en) * | 1972-06-05 | 1974-02-16 | ||
| JPS54158156A (en) * | 1978-06-05 | 1979-12-13 | Toshiba Corp | Schmitt trigger circuit |
| JPS6264121A (en) * | 1985-09-13 | 1987-03-23 | Toshiba Corp | Field effect transistor circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2751265B2 (en) | 1998-05-18 |
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