JPH02141127U - - Google Patents
Info
- Publication number
- JPH02141127U JPH02141127U JP1989046430U JP4643089U JPH02141127U JP H02141127 U JPH02141127 U JP H02141127U JP 1989046430 U JP1989046430 U JP 1989046430U JP 4643089 U JP4643089 U JP 4643089U JP H02141127 U JPH02141127 U JP H02141127U
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- data
- flop
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Pulse Circuits (AREA)
Description
第1図は本考案の一実施例を示す遅延回路図、
第2図は第1図における入出力端子及び各点の動
作波形図、第3図は従来の一例を示す遅延回路図
、第4図は第3図におけるクロツク、入出力端子
Rおよび各点の動作波形図、第5図は従来の他の
例を示す遅延回路図、第6図は第5図における入
出力端子の動作波形図である。
1……2入力マルチプレクサ、2,3……リセ
ツト付D型フリツプフロツプ、7……2入力OR
、8……2入力EX−NOR、D1,D2……マ
ルチプレクサ入力、A……マルチプレクサ入力選
択信号、Y……マルチプレクサ出力、CK……ク
ロツク入力、D……データ入力、Q……正転デー
タ出力、……反転データ出力、IN……入力端
子、OUT……出力端子。
FIG. 1 is a delay circuit diagram showing an embodiment of the present invention;
2 is an operation waveform diagram of the input/output terminals and each point in FIG. 1, FIG. 3 is a delay circuit diagram showing a conventional example, and FIG. 4 is a diagram of the clock, input/output terminal R, and each point in FIG. 3. FIG. 5 is a delay circuit diagram showing another conventional example, and FIG. 6 is an operation waveform diagram of the input/output terminals in FIG. 5. 1... 2-input multiplexer, 2, 3... D-type flip-flop with reset, 7... 2-input OR
, 8...2 input EX-NOR, D1, D2...multiplexer input, A...multiplexer input selection signal, Y...multiplexer output, CK...clock input, D...data input, Q...normal rotation data Output,...Inverted data output, IN...Input terminal, OUT...Output terminal.
Claims (1)
入力にロウレベルを与える二つのデータ入力、デ
ータ入力選択信号および出力用の各端子を有する
二入力マルチプレクサと、前記マルチプレクサの
出力をクロツク入力とし且つ正転データ出力を次
段に送出するとともに反転データ出力を自己のデ
ータ入力とするリセツト端子を有する第一のフリ
ツプフロツプと、前記第一のフリツプフロツプの
正転データ出力をクロツク入力とし且つデータ入
力および正転データ出力をそれぞれ入力端子およ
び出力端子に接続するリセツト端子を有する第二
のフリツプフロツプと、前記マルチプレクサの出
力および第一のフリツプフロツプへのリセツト入
力を二入力にし且つその出力を前記マルチプレク
サのデータ入力選択信号とする二入力ORと、前
記入力端子からの遅延させる信号と前記第二のフ
リツプフロツプ出力とを二入力にし且つその出力
をリセツト入力とする二入力EX−NORとを備
え、前記第二のフリツプフロツプに供給された入
力信号をその出力端子に遅延させて出力すること
を特徴とする遅延回路。 A two-input multiplexer that has two data inputs that give a high level to one data input and a low level to the other data input, a data input selection signal, and each terminal for output; A first flip-flop has a reset terminal that sends an output to the next stage and uses an inverted data output as its own data input, and a clock input that uses the normal data output of the first flip-flop as a data input and a normal data output. a second flip-flop having a reset terminal connected to an input terminal and an output terminal, respectively; the output of the multiplexer and the reset input to the first flip-flop are two inputs; and the output thereof is a data input selection signal of the multiplexer. It is provided with a two-input OR, and a two-input EX-NOR which has two inputs as the signal to be delayed from the input terminal and the output of the second flip-flop, and uses the output as a reset input, and is supplied to the second flip-flop. A delay circuit that delays and outputs an input signal to its output terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989046430U JPH02141127U (en) | 1989-04-19 | 1989-04-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989046430U JPH02141127U (en) | 1989-04-19 | 1989-04-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02141127U true JPH02141127U (en) | 1990-11-27 |
Family
ID=31561504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989046430U Pending JPH02141127U (en) | 1989-04-19 | 1989-04-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02141127U (en) |
-
1989
- 1989-04-19 JP JP1989046430U patent/JPH02141127U/ja active Pending
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