JPH02140960A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH02140960A JPH02140960A JP29502388A JP29502388A JPH02140960A JP H02140960 A JPH02140960 A JP H02140960A JP 29502388 A JP29502388 A JP 29502388A JP 29502388 A JP29502388 A JP 29502388A JP H02140960 A JPH02140960 A JP H02140960A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- film
- aluminum
- content
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000002161 passivation Methods 0.000 claims abstract description 9
- 229910000676 Si alloy Inorganic materials 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims abstract description 5
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 3
- 239000007789 gas Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は耐湿性の向上を目的とした半導体集積回路装置
及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same for the purpose of improving moisture resistance.
モールドパッケージの半導体集積回路装置は、セラミッ
クパッケージのそれに比較して、ブラッシャクッカテス
トに代表される耐湿性試験に於いてチップのポンディン
グ電極として用いられているアルミが腐食されやすい。In a semiconductor integrated circuit device in a mold package, aluminum used as a chip bonding electrode is more likely to be corroded in a moisture resistance test such as a brush cooker test than in a ceramic package.
このため従来、チップの組立て工程、いわゆる後工程に
於いて、モールド樹脂の材質を改良したり、樹脂封入技
術の改良により外部から侵入する水分が不純物を防ぐこ
とによって耐湿性を向上させている。For this reason, conventionally, in the chip assembly process, the so-called post-process, moisture resistance has been improved by improving the material of the molding resin and improving the resin encapsulation technology to prevent moisture from entering from the outside and impurities.
上述した従来のモールド樹脂の改良による耐湿性の向上
には以下に述べる問題がある。第１にモールド樹脂とリ
ードフレームの間隙から水分が侵入して耐湿性を低下さ
せるといった不良モードの対策として、モールド樹脂と
リードフレームとの密着力の高い樹脂を用いる必要があ
るが、これにより封入工程にて用いる金型と樹脂とが剥
離しにくくなるため製造上の困難さが発生する。Improvement in moisture resistance by improving the conventional molding resin described above has the following problems. Firstly, as a countermeasure against failure modes in which moisture enters through the gap between the mold resin and the lead frame and reduces moisture resistance, it is necessary to use a resin that has high adhesion between the mold resin and the lead frame. Manufacturing difficulties occur because the mold used in the process and the resin become difficult to separate.
第２に、モールドパッケージ内にある水分が、実装工程
に於けるハンダリフロー工程に代表される熱処理工程に
於いて、膨張し樹脂のクラックを引き起こし、耐湿性の
低下を引き起してしまうことの対策として、樹脂を硬く
して、クラックが発生しない様に機械的強度を大きくす
る必要があるが、これによって高度の大きくなった樹脂
がその応力のためにチップを損傷してしまう問題が発生
する。さらに、最近は、実装時の集積度を向上するため
に表面実装型パッケージに代表される様にパッケージの
多ピン化、縮小化、薄化が進められているが、これは上
述した様な耐湿性不良を改善することをますます困難に
している。Second, moisture in the molded package expands during the heat treatment process, typically the solder reflow process during the mounting process, causing cracks in the resin and reducing moisture resistance. As a countermeasure, it is necessary to harden the resin and increase its mechanical strength to prevent cracks from occurring, but this causes the problem that the increased resin damages the chip due to its stress. . Furthermore, recently, in order to improve the degree of integration during mounting, packages, as typified by surface mount packages, have been increasing in number of pins, becoming smaller, and becoming thinner. This makes it increasingly difficult to improve sexual defects.
本発明は、同一のアルミ層より形成されたアルミ配線及
びポンディング電極に於いてポンディング電極のみが耐
食性の高いアルミ・シリコン合金よりなることを特徴と
している。さらに、本発明はパッシベーション膜の被膜
及びボンディングパッド部分の開口を行った後、ウェハ
ー全面にシリコン膜をつけ、熱処理をして、ポンディン
グ開口部分にてポンディング電極であるところのアルミ
とこれに接して付けられたシリコンとが合金化スルモの
のパッシベーション膜の表面に付けられたシリコン膜は
合金化しないことを利用して、シリコンのみを除去する
エツチングで行うことによってパッシベーション膜表面
のポリシリコン膜を除去する手段を有している。The present invention is characterized in that among the aluminum wiring and the bonding electrode formed from the same aluminum layer, only the bonding electrode is made of an aluminum-silicon alloy with high corrosion resistance. Furthermore, in the present invention, after coating the passivation film and opening the bonding pad portion, a silicon film is applied to the entire surface of the wafer, heat treatment is performed, and aluminum, which is the bonding electrode, is bonded to the bonding electrode at the bonding opening portion. The polysilicon film on the surface of the passivation film is removed by etching, which removes only the silicon, taking advantage of the fact that the silicon film on the surface of the passivation film is not alloyed with the silicon attached in contact with it. It has means for removing.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（Ａ）乃至（Ｄ）は本発明の一実施例の断面図で
ある。まず、第１図（Ａ）のように、素子形成後のシリ
コン基板１上に１μｍ厚程度でシリコン含有率が０．０
１％未満のアルミニウム膜をつけ、パターンニングを行
ってアルミニウム配線３とポンディング電極３′を形成
する。この表面にパッシベーション膜として用いる約１
μｍの厚さのシリコン窒化膜４をつけ、ポンディング電
極３′部分を開口する。以下述べた構造の製造方法は現
在行われいる既存の技術を用いて問題ない。またパッシ
ベーション膜４は、プラズマ窒化膜や、リンガラス、ポ
リイミド膜など従来バッジベージコン膜として用いられ
ているものでかまわない。次に、第１図（Ｂ）のように
、蒸着法にて０．０１〜０．２μｍ例えば５００人程鹿
のポリシリコン５をつける。次に、第１図（ｃ）のよう
に窒素雰囲気にて４００〜５００℃の間の４５０℃で熱
処理を行う。その時間は１０〜９０分、例えば６０分に
する。これによってポンディング開口部にて露出してい
るアルミニウムとシリコンが反応し、アルミ−シリコン
合金膜３１１となる。シリコンの含有率は０．０１〜１
％となる。このときポンディング開口部以外に於いてパ
ッシベーション膜上につけられたポリシリコンは合金化
しない。そして、第１図（Ｄ）のように、酸素を２０％
含んだＣＦ４ガスを導入し５０ｐａの圧力にて高周波電
力を印加して得られるプラズマガスにてシリコン膜５を
除去する。この時シリコン膜の下にあるパッシベーショ
ン膜するいはアルミ−シリコン合金３″はほとんど膜ベ
リしない為シリコンのみが選択的に除去される。FIGS. 1A to 1D are cross-sectional views of one embodiment of the present invention. First, as shown in FIG. 1(A), silicon content of 0.0 is applied to a silicon substrate 1 with a thickness of about 1 μm after device formation.
An aluminum film of less than 1% is deposited and patterned to form aluminum wiring 3 and a bonding electrode 3'. Approximately 1
A silicon nitride film 4 with a thickness of .mu.m is deposited, and an opening is made at the portion of the bonding electrode 3'. The method for manufacturing the structure described below can be used without any problems using existing techniques currently in use. Further, the passivation film 4 may be a film conventionally used as a badge-container film, such as a plasma nitride film, a phosphorus glass film, or a polyimide film. Next, as shown in FIG. 1B, a layer of polysilicon 5 having a thickness of 0.01 to 0.2 μm, for example, about 500 layers, is applied by vapor deposition. Next, as shown in FIG. 1(c), heat treatment is performed at 450° C. between 400 and 500° C. in a nitrogen atmosphere. The time is 10 to 90 minutes, for example 60 minutes. As a result, the aluminum and silicon exposed at the bonding opening react to form an aluminum-silicon alloy film 311. Silicon content is 0.01-1
%. At this time, the polysilicon deposited on the passivation film in areas other than the bonding openings is not alloyed. Then, as shown in Figure 1 (D), add 20% oxygen.
The silicon film 5 is removed using a plasma gas obtained by introducing CF4 gas containing CF4 and applying high frequency power at a pressure of 50 pa. At this time, since the passivation film or the aluminum-silicon alloy 3'' under the silicon film hardly buries, only the silicon is selectively removed.
第１図（Ｂ）に示す様なシリコン膜５をつける方法とし
てプラズマＣＶＤ法を用いてもよい。この方法は真空チ
ャンバー内にシラン（ＳｉＨ４）を導入し５〜１５ｐａ
の圧力とし、約４００℃の温度にて高周波電力を印加す
ることによってアモルファスシリコン膜をつけることが
できる。A plasma CVD method may be used as a method for depositing the silicon film 5 as shown in FIG. 1(B). This method introduces silane (SiH4) into a vacuum chamber and
An amorphous silicon film can be formed by applying high frequency power at a pressure of about 400° C. and a temperature of about 400° C.
以上説明した様に、本発明による半導体チップはポンデ
ィング電極が耐食性のある合金となっているために従来
品に比較して、耐湿性を大きく向上することができる。As explained above, in the semiconductor chip according to the present invention, since the bonding electrode is made of a corrosion-resistant alloy, the moisture resistance can be greatly improved compared to conventional products.
さらに、ポンディング電極のみを合金化し、配線部分は
従来のアルミのままであることを可能とする構造及び製
法であるために、ショットキーダイオードに代表される
様に配線材によって大きく特性の変化する素子を搭載し
た集積回路に於いても何ら問題を引き起こさない。さら
に、リソグラフィー工程の回数が増加することもなく、
アルミ配線とポンディング電極が同時に形成されること
は従来通りであるために、工程が複雑になることもない
割には効果の大きい際めで優れた方法である。Furthermore, because the structure and manufacturing method allows only the bonding electrode to be alloyed and the wiring part to remain the same as conventional aluminum, the characteristics can vary greatly depending on the wiring material, as typified by Schottky diodes. It does not cause any problems in integrated circuits equipped with the elements. Furthermore, there is no increase in the number of lithography steps,
Since the aluminum wiring and the bonding electrode are formed at the same time as in the past, it is an excellent method that is highly effective and precise, although the process does not become complicated.
第１図（Ａ）乃至（Ｄ）は本発明の一実施例を工程順に
示す縦断面図である。
１・・・・・・シリコン基板、２・・・・・・層間絶縁
膜、３・・・・・・アルミ配線、３′・・・・・・ポン
ディング電極、３″・・・・・・シリコン−アルミ合金
、４・・・・・・シリコン窒化Ｌ ５・・・・・・シ
リコン膜。
代理人 弁理士 内 原 晋
隋１図FIGS. 1A to 1D are vertical cross-sectional views showing an embodiment of the present invention in the order of steps. 1...Silicon substrate, 2...Interlayer insulating film, 3...Aluminum wiring, 3'...Ponding electrode, 3''...・Silicon-aluminum alloy, 4...Silicon nitride L 5...Silicon film. Agent: Patent attorney Uchihara Jin Sui Figure 1
Claims (2)
膜で選択的に覆われ、露出した部分をボンディングパッ
ドとする半導体装置において、該パッドの少なくとも表
面部分はシリコン含有率が０．０１〜１％のアルミニウ
ムシリコン合金であり、それ以外はシリコン含有率が０
．０１％未満であることを特徴とする半導体装置。(1) In a semiconductor device in which the uppermost aluminum wiring film is selectively covered with a passivation film and the exposed portion is used as a bonding pad, at least the surface portion of the pad is made of aluminum with a silicon content of 0.01 to 1%. Silicon alloy, otherwise silicon content is 0
．． 1. A semiconductor device characterized in that it is less than 0.01%.
ウム配線層を形成し、該層をパッシベーション膜で選択
的に覆い、全面にシリコン膜をつけ、窒素雰囲気にて熱
処理を行い、フレオンガスを主体としたプラズマエッチ
ング方法を用いて該ポリシリコン膜の除去を行うことを
特徴とする半導体装置の製造方法。(2) Form an aluminum wiring layer with a silicon content of less than 0.01%, selectively cover the layer with a passivation film, apply a silicon film to the entire surface, heat treat it in a nitrogen atmosphere, and use Freon gas as the main component. A method for manufacturing a semiconductor device, characterized in that the polysilicon film is removed using a plasma etching method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29502388A JP2727605B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29502388A JP2727605B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02140960A true JPH02140960A (en) | 1990-05-30 |
| JP2727605B2 JP2727605B2 (en) | 1998-03-11 |
Family
ID=17815329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29502388A Expired - Lifetime JP2727605B2 (en) | 1988-11-21 | 1988-11-21 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2727605B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8026584B2 (en) * | 2007-10-18 | 2011-09-27 | Samsung Electronics Co., Ltd. | Semiconductor package, module, system having solder ball coupled to chip pad and manufacturing method thereof |
-
1988
- 1988-11-21 JP JP29502388A patent/JP2727605B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8026584B2 (en) * | 2007-10-18 | 2011-09-27 | Samsung Electronics Co., Ltd. | Semiconductor package, module, system having solder ball coupled to chip pad and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2727605B2 (en) | 1998-03-11 |
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