JPH02132857A - Circuit built-in photodetector - Google Patents
Circuit built-in photodetectorInfo
- Publication number
- JPH02132857A JPH02132857A JP63286529A JP28652988A JPH02132857A JP H02132857 A JPH02132857 A JP H02132857A JP 63286529 A JP63286529 A JP 63286529A JP 28652988 A JP28652988 A JP 28652988A JP H02132857 A JPH02132857 A JP H02132857A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- type
- layer
- transistor
- photodiode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 abstract description 42
- 239000012535 impurity Substances 0.000 abstract description 3
- 206010034972 Photosensitivity reaction Diseases 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 230000036211 photosensitivity Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 3
- 206010034960 Photophobia Diseases 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 208000013469 light sensitivity Diseases 0.000 description 2
- 241000238557 Decapoda Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は信号処理回路を内蔵し次受光素子の元感度を増
加し、かつ応答速度を高速化する構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a structure that incorporates a signal processing circuit, increases the original sensitivity of a secondary light receiving element, and increases the response speed.
（従来の技術）
回路内蔵受光素子は、光センサ，光アイソレータ等に広
く用いられている。第６図は従来の一般的な回路内蔵受
光素子の構造の断面図の一例を示す。同図において一枚
のＰ型半導体基板１０表面には受光素子であるホトダイ
オード部ＡとＮＰＮトランジスタＢ等の信号処理回路構
成素子とが形成されている。ホトダイオード部人は、Ｐ
型半導体基板１に埋込まれたＮ型埋込拡散層２，その上
に成長させ九Ｎ型エピタキシャル層４，その表面のＰ型
拡散層６（ホトダイオードの一方の電極となる）及びコ
レクタ補償拡散層５（ホトダイオードの他方の電極とな
る）等から構成される。Ｎｆ’Ｎトランジスタ部Ｂは、
Ｐ型半導体基板１に埋込まれたＮ型埋込拡散層２−１，
その上に成長させたＮ型エピタキシャル層４−１，その
表面のＰ型拡散層６−１（｝ランジスタのベースとなる
），その中のＮ型拡散層７（トランジスタの工きツタと
なる）及びＮ型エピタキシャル層４及び４−１の側方の
コレクタ補償拡散層５，５，・・・等から構成される。(Prior Art) Photodetectors with built-in circuits are widely used in optical sensors, optical isolators, and the like. FIG. 6 shows an example of a cross-sectional view of the structure of a conventional general light-receiving element with a built-in circuit. In the figure, a photodiode section A, which is a light receiving element, and signal processing circuit components such as an NPN transistor B are formed on the surface of one P-type semiconductor substrate 10. The photodiode club member is P.
N-type buried diffusion layer 2 buried in type semiconductor substrate 1, nine N-type epitaxial layer 4 grown thereon, P-type diffusion layer 6 on its surface (which becomes one electrode of the photodiode), and collector compensation diffusion. It is composed of layer 5 (which becomes the other electrode of the photodiode), etc. The Nf'N transistor part B is
N-type buried diffusion layer 2-1 buried in P-type semiconductor substrate 1,
An N-type epitaxial layer 4-1 grown on it, a P-type diffusion layer 6-1 on its surface (becomes the base of the transistor), and an N-type diffusion layer 7 therein (becomes the base of the transistor) and collector compensation diffusion layers 5, 5, . . . on the sides of the N-type epitaxial layers 4 and 4-1.
ホトダイオード部ＡとＮＰＮ｝ランジスタ部Ｂとその他
の素子との間は、素子間分離Ｐ型拡散層３，３，・・・
によって分離される。なお、図において点線２０は、エ
ピタキシャル成長を行なう前のＰ型半導体基板１の表面
を示す。Between the photodiode section A and NPN} transistor section B and other elements, element isolation P-type diffusion layers 3, 3, . . .
separated by In the figure, a dotted line 20 indicates the surface of the P-type semiconductor substrate 1 before epitaxial growth.
（発明が解決しようとする課題）
最近のデータ伝送の高速化，Ｓ／Ｎ比向上等の要求から
回路内蔵受光素子の高光感度化，応答速度の高速化等が
望まれている。(Problems to be Solved by the Invention) Recent demands for higher data transmission speeds, improved S/N ratios, etc. have led to demands for higher optical sensitivity and faster response speeds for light-receiving elements with built-in circuits.
前述の第６図のような構造においては、ホトダイオード
部ＡのＮ型エピタキシャル層４とＮＰＮトランジスタ部
ＢｏＮ型エピタキシャル層４−１の厚さは同一になって
いる。In the structure shown in FIG. 6 described above, the thickness of the N-type epitaxial layer 4 of the photodiode section A and the BoN-type epitaxial layer 4-1 of the NPN transistor section are the same.
光感度を上げるには、ホトダイオード部ＡのＮ濫エピタ
キシャルＭｊ４の厚さを、信号用として使用する光の波
長に応じ十分厚くする必要がある。In order to increase the optical sensitivity, it is necessary to make the thickness of the N-type epitaxial layer Mj4 of the photodiode section A sufficiently thick according to the wavelength of the light used for signal purposes.
しかし、Ｎ型エピタキシャル層４があ′！シ厚くなると
、この層の中の空乏層化していない部分を、発生し九光
キャリアが拡散により走行する時間が長くなシ応答速度
の高速化を妨げる。ま九、Ｎ型エピタキシャル層４−１
の厚さを厚くすると、ＮＰＮ｝ランジスタ部ＢＯＮ屋エ
ピタキシャル層４−１の厚さも厚くなり、ＮＰＮ｝ラン
ジスタのコレクタ抵抗の増大となり、応答速度高速化の
障害となる。However, the N-type epitaxial layer 4 is missing! When the layer becomes thicker, the non-depleted portions of the layer are generated, and the time taken for optical carriers to travel due to diffusion is longer, which impedes an increase in the response speed. 9. N-type epitaxial layer 4-1
If the thickness of the NPN transistor is increased, the thickness of the BON epitaxial layer 4-1 of the NPN transistor section also becomes thick, which increases the collector resistance of the NPN transistor, which becomes an obstacle to increasing the response speed.
一方、回路内蔵受光素子の応答速度高速化には、ホトダ
イオード部の接合容量の低減が有効であり、そのために
は、Ｎ型エピタキシャル層４の比抵抗を高くすることが
必要である。しかし、Ｎ型エピタキシャル層４−１の比
抵抗が高くなると，ＮＰＮトランジスタのコレクタ抵抗
が増大し、応答速度高速化に対して、反対の結果となる
。On the other hand, reducing the junction capacitance of the photodiode portion is effective for increasing the response speed of the photodetector with a built-in circuit, and for this purpose, it is necessary to increase the specific resistance of the N-type epitaxial layer 4. However, when the resistivity of the N-type epitaxial layer 4-1 increases, the collector resistance of the NPN transistor increases, which has the opposite effect on increasing the response speed.
以上のことから、回路内蔵受光素子の高光感度と、高速
の応答速度を両立させるためには、ホトダイオード部Ａ
のＮ型エピタキシャル層４は高比抵抗でかつ厚く、ＮＰ
Ｎ｝ランジスタ部ＢｏＮ型エピタキシャル層４−１は低
比抵抗でかつ薄くする必要があるが、従来のような構造
では、前記の相反する条件を満足させることは困難であ
った。From the above, in order to achieve both high light sensitivity and high response speed of the photodetector with a built-in circuit, it is necessary to
The N-type epitaxial layer 4 has a high specific resistance and is thick, and is
N} The BoN type epitaxial layer 4-1 in the transistor section needs to have a low resistivity and be thin, but it is difficult to satisfy the above contradictory conditions with a conventional structure.
（！ｌ題を解決するための手段）
本発明においては前述の問題を解決するため、ホトダイ
オード部のエピタキシャル層は、Ｎ型埋込拡散層の上に
高比抵抗のエピタキシャル層を二層堆積して厚くし、Ｎ
ＰＮ｝ランジスタ部Ｂは、下部エピタキシャル層下にＰ
型埋込拡散層を設け、さらに上部エピタキシャル層下に
Ｎ型埋込拡散層を設け、上部エピタキシャル層部分に深
いＮ型拡散層を設けた。(Means for Solving the Problem) In the present invention, in order to solve the above-mentioned problem, the epitaxial layer of the photodiode section is formed by depositing two high resistivity epitaxial layers on the N-type buried diffusion layer. Make it thicker, then
PN} The transistor part B has P transistor under the lower epitaxial layer.
A type buried diffusion layer was provided, an N type buried diffusion layer was further provided under the upper epitaxial layer, and a deep N type diffusion layer was provided in the upper epitaxial layer portion.
（作用）
前述のような構成によって、ホトダイオード部のＮ型エ
ピタキシャル層は高比抵抗で厚く、また、ＮＰＮ｝ラン
ジスタ部の実効エピタキシャル層は，Ｐ型埋込拡散層上
部の深いＮ型拡散層によシ補償された部分となるから、
回路内蔵受光素子の高光感度化．応答速度の高速化を同
時に実現できる。(Function) With the above-mentioned configuration, the N-type epitaxial layer in the photodiode part has a high resistivity and is thick, and the effective epitaxial layer in the NPN transistor part is in the deep N-type diffusion layer above the P-type buried diffusion layer. Because it will be a compensated part,
High light sensitivity of photodetector with built-in circuit. At the same time, it is possible to achieve faster response speed.
（実施例）
第１のは本発明の一実施例の断面図であり、第２図乃至
第４図は第１図の構造を得るまでの各工程の断面因であ
る。(Example) The first is a cross-sectional view of an example of the present invention, and FIGS. 2 to 4 are cross-sectional views of each process until the structure shown in FIG. 1 is obtained.
まず、最初に第２図に示されるように、Ｐ箆半導体基板
１の表面のホトダイオード部予定領域咽の左方）には第
一のＮｆｆｉ埋込拡散Ｍ２、ＮＰＮ｝ランジスタ部予定
領域（図の右方）にはＰ型埋込拡散層１２を形成する。First, as shown in FIG. 2, the first Nffi buried diffusion M2, NPN} transistor region (to the left of the photodiode region on the surface of the semiconductor substrate 1) (in the figure) A P-type buried diffusion layer 12 is formed on the right side).
このときホトダイオードと信号処理回路素子とを分離す
る部分（図の左方）にもＰ型埋込拡散層１２を形成する
。At this time, a P-type buried diffusion layer 12 is also formed in a portion separating the photodiode and the signal processing circuit element (left side in the figure).
次に、第３図に示されるように、全面に例えばｌＯＯΩ
α程度の高比抵抗の第一のＮ型エピタキシャル層８を成
長させる。このとき、図の左方の素子分離用のＰ型埋込
拡散層ｌ２と、図の右方のＮＰＮ｝ランジスタ部予定領
域のＰｆｉ埋込拡散層１２は、いずれもＮｆｆｉエピタ
キシャル層８の内部に拡散し、最初のＰ型半導体基板１
０表面である点線２０よク上部Ｋ拡がる。第一のＮ型埋
込拡散層２も、Ｎ型エピタキシャル層８の中に拡散する
。Next, as shown in FIG. 3, for example, lOOΩ is applied to the entire surface.
A first N-type epitaxial layer 8 having a high specific resistance of approximately α is grown. At this time, the P-type buried diffusion layer 12 for element isolation on the left side of the figure and the Pfi buried diffusion layer 12 in the NPN} transistor region on the right side of the figure are both inside the Nffi epitaxial layer 8. Diffused, the first P-type semiconductor substrate 1
The upper part K expands beyond the dotted line 20, which is the 0 surface. The first N-type buried diffusion layer 2 also diffuses into the N-type epitaxial layer 8 .
その後、ＮＰＮ｝ランジスタ部予定領域の表面に第二の
Ｎ型埋込拡散層１０を形成する。Thereafter, a second N-type buried diffusion layer 10 is formed on the surface of the region where the NPN transistor portion is to be formed.
さらに、第４因に示されるように、例えば１００゛Ω個
程度の高比抵抗の第二のＮ型エピタキシャル層９を全面
に成長させる。そして、ＮＰＮ｝ランジスタ部予定領域
には、例えば１０備程度の比抵抗Ｋなるように適当な不
純物濃度の、深いＮｆｆｉ拡散層１１を形成する。この
とき、第二のＮ型埋込拡散層ｌＯは、Ｐ型埋込拡散層１
０及びＮ型拡散層１１の内部にある程度拡散する。同因
において点線３０はＮ型エピタキシャル層８が成長され
之ときの表面を示す。Furthermore, as shown in the fourth factor, a second N-type epitaxial layer 9 having a high specific resistance of, for example, about 100 Ω is grown over the entire surface. Then, a deep Nffi diffusion layer 11 having an appropriate impurity concentration so as to have a specific resistance K of about 10, for example, is formed in the region where the NPN transistor portion is to be formed. At this time, the second N-type buried diffusion layer lO is the P-type buried diffusion layer 1.
It diffuses to some extent inside the 0 and N type diffusion layers 11. In the same way, a dotted line 30 indicates the surface on which the N-type epitaxial layer 8 is grown.
このようにして形成され九基板の表面から，各素子問の
分離用のＰ型拡散層１３．１３，・・・、コレクタ補償
拡散層５．５・・・、ホトダイオードの電極６及びＮＰ
Ｎ ｝ランジスタのベース６−１用のＰ型拡散層、エミ
ッタ拡散層７等を形成すると、第１図の構造が得られる
〇
第１図において、ホトダイオード部人のエピタキシャル
層は、高比抵抗のＮ型エビタキシ．ヤル層８と高比抵抗
のＮ型エピタキシャル層９の合計の厚さを有する。ＮＰ
Ｎ｝ランジスタ部Ｂのエピタキシャル層の厚さは、高比
抵抗のＮ型エピタキシャル層９の厚さと略々同等になっ
ている。また、それぞれのエピタキシャル層の比抵抗は
、ホトダイオード部Ａでは、エピタキシャル底長された
１１の高比抵抗であク、トランジスタ部Ｂでは、Ｎ型拡
散層１１を形成する際、適切な濃度の不純物を注入する
ことにより、十分に低い比抵抗とすることができる。From the surface of the nine substrates formed in this way, P-type diffusion layers 13, 13, . . . for isolation between each element, collector compensation diffusion layers 5, 5, .
N }By forming the P-type diffusion layer for the base 6-1 of the transistor, the emitter diffusion layer 7, etc., the structure shown in Fig. 1 is obtained. In Fig. 1, the epitaxial layer of the photodiode section has a high specific resistance. Type N shrimp. The total thickness of the layer 8 and the high resistivity N-type epitaxial layer 9 is the same. NP
The thickness of the epitaxial layer of the N} transistor portion B is approximately equal to the thickness of the high resistivity N-type epitaxial layer 9. In addition, the specific resistance of each epitaxial layer is a high specific resistance of 11 in the photodiode section A, which is the epitaxial bottom length, and in the transistor section B, when forming the N-type diffusion layer 11, an appropriate concentration of impurity is added. By injecting , a sufficiently low resistivity can be achieved.
第５図は第１図の構造の改良され九もので、ホトダイオ
ード部ＡのＮ型エピタキシャル層８及び９の周囲の上部
をコレクタ補償拡散層５によって、ま次、下部を第二の
Ｎ型埋込拡散層１０によって包囲してある。この場合は
、第１図の構造に比してコレクタ補償拡散層５を浅くす
ることができるので、チップ面積を縮小できる。ホトダ
イオード部Ａの直列抵抗は、コレクタ補償拡散層５が深
い場合と同様に低くすることができる。FIG. 5 shows an improved structure of FIG. 1, in which the upper part around the N-type epitaxial layers 8 and 9 of the photodiode section A is covered with a collector compensation diffusion layer 5, and the lower part is covered with a second N-type buried layer. It is surrounded by a diffusion layer 10. In this case, since the collector compensation diffusion layer 5 can be made shallower than in the structure shown in FIG. 1, the chip area can be reduced. The series resistance of the photodiode section A can be made as low as in the case where the collector compensation diffusion layer 5 is deep.
（発明の効果〕
本発明によれば、ホトダイオード部は高比抵抗で厚膜の
エピタキシャル層を有し、その比抵抗及び厚さを、実際
の使用状態のバイアス電圧において、完全に空乏層化す
るように設定しておけば、いわゆるｐ−ｉ−ｎ型の構造
とすることができ、光電又換効率′のよい応答速度の速
いホトダイオードを得ることができる。また、トランジ
スタ部は、実効的に低比抵抗で薄膜のエピタキシャル層
を有し、高速なトランジスタとなる。両者を結合するこ
とにより、集積度の高い光感度．応答速度ともにすぐれ
九回路内蔵受元素子を得ることができる。(Effects of the Invention) According to the present invention, the photodiode portion has a thick epitaxial layer with high resistivity, and its resistivity and thickness are completely reduced to a depletion layer at a bias voltage under actual use. If this setting is made, a so-called p-i-n type structure can be obtained, and a photodiode with good photoelectric conversion efficiency and a fast response speed can be obtained.In addition, the transistor section can be effectively It has a thin epitaxial layer with low resistivity and is a high-speed transistor. By combining the two, it is possible to obtain a highly integrated nine-circuit receiving element with excellent photosensitivity and response speed.
第１図は本発明の一実施例の断面図、第２図，第３図．
第４図は第１図の構造を得るための各工程を示す断面図
、第５図は他の実施例の断面図、第６図は従来の構造の
断面図である。
１・・・Ｐ型半導体基板、２・・・Ｎ型埋込拡散層、４
．４−１・・・Ｎｆｉエピタキシャル層、５・・・コレ
クタ補償拡散層、訃・・Ｎ型エピタキシャル層（高比抵
抗）、９・・・Ｎ型エピタキシャル層（高比抵抗）、１
０・・・Ｎ型埋込拡散層、１１・・・Ｎ型拡散層、１２
・・・Ｐ型埋込拡散層、ｌ３・・・素子間分離用Ｐ型拡
散層、Ａ・・・ホトダイオード、Ｂ・・・トランジスタ
第３図Figure 1 is a sectional view of an embodiment of the present invention, Figures 2 and 3.
FIG. 4 is a sectional view showing each step to obtain the structure shown in FIG. 1, FIG. 5 is a sectional view of another embodiment, and FIG. 6 is a sectional view of a conventional structure. 1... P-type semiconductor substrate, 2... N-type buried diffusion layer, 4
．． 4-1 Nfi epitaxial layer, 5 Collector compensation diffusion layer, N type epitaxial layer (high resistivity), 9 N type epitaxial layer (high resistivity), 1
0...N-type buried diffusion layer, 11...N-type diffusion layer, 12
...P-type buried diffusion layer, l3...P-type diffusion layer for element isolation, A...photodiode, B...transistor Fig. 3
Claims (1)
路とよりなり、受光素子は第一の導電型を有する層と、
これに埋込まれた第二の導電型の層と、その上に積層さ
れた第二の導電型の高比抵抗の厚い複数のエピタキシャ
ル層とを有し、信号処理回路は第一の導電型を有する厚
い層と、これに埋込まれた第二の導電型の層と、その上
に設けられた第二の導電型の低比抵抗の薄い層とを有す
ることを特徴とする回路内蔵受光素子1. Consists of a light-receiving element and a signal processing circuit formed on one substrate, and the light-receiving element includes a layer having a first conductivity type,
The signal processing circuit has a second conductivity type layer embedded therein and a plurality of thick epitaxial layers of the second conductivity type with high specific resistance laminated thereon. A light receiving device with a built-in circuit, characterized in that it has a thick layer having a second conductivity type, a second conductivity type layer embedded therein, and a second conductivity type low resistivity thin layer provided thereon. element
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63286529A JPH0724300B2 (en) | 1988-11-11 | 1988-11-11 | Light receiving element with built-in circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63286529A JPH0724300B2 (en) | 1988-11-11 | 1988-11-11 | Light receiving element with built-in circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02132857A true JPH02132857A (en) | 1990-05-22 |
| JPH0724300B2 JPH0724300B2 (en) | 1995-03-15 |
Family
ID=17705589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63286529A Expired - Fee Related JPH0724300B2 (en) | 1988-11-11 | 1988-11-11 | Light receiving element with built-in circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0724300B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61265866A (en) * | 1985-05-20 | 1986-11-25 | Sharp Corp | Circuit built-in light-receiving element |
| JPS62131570A (en) * | 1985-12-03 | 1987-06-13 | Sharp Corp | Semiconductor light receiving device |
-
1988
- 1988-11-11 JP JP63286529A patent/JPH0724300B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61265866A (en) * | 1985-05-20 | 1986-11-25 | Sharp Corp | Circuit built-in light-receiving element |
| JPS62131570A (en) * | 1985-12-03 | 1987-06-13 | Sharp Corp | Semiconductor light receiving device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0724300B2 (en) | 1995-03-15 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |