JPH02130946A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02130946A JPH02130946A JP28529388A JP28529388A JPH02130946A JP H02130946 A JPH02130946 A JP H02130946A JP 28529388 A JP28529388 A JP 28529388A JP 28529388 A JP28529388 A JP 28529388A JP H02130946 A JPH02130946 A JP H02130946A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- chip
- pad
- semiconductor chip
- metal cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 239000000919 ceramic Substances 0.000 abstract description 18
- 238000007789 sealing Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 description 8
- 230000010354 integration Effects 0.000 description 5
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体集積回路のパッケージ構造に関し、半導体集積回
路の電源ラインの抵抗を減らし、かつパッケージに入れ
る半導体集積回路チップの高集積化を図ることを目的と
し、
周辺部に信号用パッドを有し、中央部に電源用パッドを
有する半導体チップと、前記半導体チップを収容し、前
記半導体チップの信号用パッドが接続される外部リード
を有するパッケージと、前記パッケージに設けられて前
記半導体チップを密封する金属キャップとを有し、前記
金属キャップには、前記電源用パッドに接続されるコン
タクト用突起物が設けられ、前記半導体チップへの電源
供給は、前記金属キャップを介して行われることを含み
構成する。[Detailed Description of the Invention] [Summary] With regard to the package structure of a semiconductor integrated circuit, the purpose of this invention is to reduce the resistance of the power supply line of the semiconductor integrated circuit and to increase the degree of integration of the semiconductor integrated circuit chip placed in the package. a semiconductor chip having a signal pad at the center and a power supply pad at the center; a package accommodating the semiconductor chip and having an external lead to which the signal pad of the semiconductor chip is connected; and a metal cap for sealing the semiconductor chip, the metal cap is provided with a contact protrusion connected to the power supply pad, and power is supplied to the semiconductor chip through the metal cap. Contains and constitutes what will be done.
本発明は、半導体集積回路のパッケージ構造に関する。 The present invention relates to a package structure for a semiconductor integrated circuit.
近年、半導体集積回路の高速化、高集積化に伴い、半導
体集積回路全体に均一で安定した電源供給が必要になっ
ている。このため、半導体チップ内の回路配置、特に電
源用パッドの配置が工夫されている。In recent years, as semiconductor integrated circuits have become faster and more highly integrated, it has become necessary to supply uniform and stable power to the entire semiconductor integrated circuit. For this reason, circuit layout within a semiconductor chip, particularly the layout of power supply pads, has been devised.
〔従来の技術］
半導体チップ内の電源用パッドは、バイポーラＩＣを例
にとると、コレクタ電源（ＶＣＣ）用およびエミッタ電
源（Ｖ、）用などがあり、集積回路を構成する各素子に
均一に電源供給を行うためには、各素子からほぼ等しい
距離にある半導体チップの中央部に電源用パッドが配置
されていた方が都合がよい。[Prior Art] In the case of a bipolar IC, for example, power supply pads in a semiconductor chip are used for collector power supply (VCC) and emitter power supply (V, ), and are uniformly applied to each element constituting an integrated circuit. In order to supply power, it is convenient for the power supply pad to be placed in the center of the semiconductor chip at approximately the same distance from each element.
第３図は、このような半導体チップを搭載した半導体装
置の上面図である。FIG. 3 is a top view of a semiconductor device equipped with such a semiconductor chip.
図において、１０３は集積回路が形成されたＳｉチップ
で、中央部に電源用パッド２０４が配置されている。ま
た、１０４はＶ□電源用バッド２０４と電源用外部リー
ド１１９とを接続するための＾Ｕワイヤ、１０５はＶ０
電源用パッド２０４以外のパッドと外部リードとを接続
するための＾Ｕワイヤ、１０６はＳｔチップ１０３をグ
イボンディングするためのステージ、１０７はセラミッ
ク基板、１０８はセラミック側壁、１１９はｖ０電源用
外部リード、１２９はＶＣＣ電源用外部リード、２０９
は信号用外部リードである。In the figure, 103 is a Si chip on which an integrated circuit is formed, and a power supply pad 204 is arranged in the center. Further, 104 is a ^U wire for connecting the V□ power supply pad 204 and the power supply external lead 119, and 105 is a V0
^U wire for connecting pads other than the power supply pad 204 and external leads, 106 is a stage for bonding the St chip 103, 107 is a ceramic substrate, 108 is a ceramic side wall, 119 is an external lead for v0 power supply , 129 is an external lead for VCC power supply, 209
is an external signal lead.
ところで、この半導体装置の構成によれば、半導体チッ
プサイズが大きくなれば、中央部に設けられたＶｔｔ電
源用パッド２０４とＶＩｔ電源用外部リード１１９とを
接続する＾Ｕワイヤ１０４の長さがますます長くなる。By the way, according to the configuration of this semiconductor device, as the semiconductor chip size increases, the length of the ^U wire 104 that connects the Vtt power supply pad 204 provided in the center and the VIt power supply external lead 119 increases. It gets longer.
このため、■、電源用外部リード１１９からＶＩ電源用
パッド２０４に到るまでのワイヤにおける電源電圧の降
下が大きくなり、回路素子の動作が遅くなったり、場合
によっては誤動作を招く。For this reason, (1) the drop in the power supply voltage in the wire from the power supply external lead 119 to the VI power supply pad 204 becomes large, slowing down the operation of the circuit elements, or causing malfunction in some cases.
第４図は、この問題を解決する半導体装置の上面図であ
る。FIG. 4 is a top view of a semiconductor device that solves this problem.
同図において、第３図と同一の符号は同一のものを表す
。In this figure, the same symbols as in FIG. 3 represent the same things.
この構成によれば、ＶａｔおよびＶＣＣ電源用パッドを
、それぞれＳＩチップ１０３の周辺に４ケ所ずつ設けて
いるので、電源から供給される電流を４つに分配するこ
とになり、またワイヤの長さも短くで済むので、電源電
圧の降下量を少なくすることができる。According to this configuration, the Vat and VCC power supply pads are provided at four locations around the SI chip 103, so the current supplied from the power supply is divided into four, and the length of the wire is also reduced. Since the length can be shortened, the amount of drop in the power supply voltage can be reduced.
しかし、第４図の半導体装置によると、半導体チップ内
に電源用パッドを８個設けることになり、その分、信号
用パッドの配置や個数に制限を受け、半導体装置の高集
積化が図れないという問題がある。However, according to the semiconductor device shown in Figure 4, eight power supply pads are provided within the semiconductor chip, which limits the arrangement and number of signal pads, making it difficult to achieve high integration of the semiconductor device. There is a problem.
本発明は、かかる従来の問題点に鑑みてなされたもので
、電源用のパッドの数を増やすことなく、また半導体チ
ップ内の電源パッドに適正な電源電圧を供給することの
できる半導体装置を提供することを目的とする。The present invention has been made in view of such conventional problems, and provides a semiconductor device that can supply an appropriate power supply voltage to power supply pads within a semiconductor chip without increasing the number of power supply pads. The purpose is to
（課題を解決するための手段〕
上記目的は、周辺部に信号用パッド１５を有し、中央部
に電源用パッド４を有する半導体チップ３と、前記半導
体チップ３を収容し、前記半導体チップ３の信号用パッ
ド１５が接続される外部リード９を有するパッケージと
、前記パッケージに設けられて前記半導体チップ３を密
封する金属キャンプ２とを有し、前記金属キャップ２に
は、前記電源用パッド４に接続されるコンタクト用突起
物ｌが設けられ、前記半導体チップ３への電源供給は、
前記金属キャップ２を介して行われることを特徴とする
半導体装置によって達成される。(Means for Solving the Problems) The above objects include a semiconductor chip 3 having a signal pad 15 in the peripheral part and a power supply pad 4 in the central part; The package includes an external lead 9 to which the signal pad 15 is connected, and a metal camp 2 provided in the package to seal the semiconductor chip 3. The metal cap 2 includes the power supply pad 4. A contact protrusion l connected to the semiconductor chip 3 is provided, and power supply to the semiconductor chip 3 is performed by
This is achieved by a semiconductor device characterized in that the metal cap 2 is used.
（作用〕
本発明によれば、半導体チップ中央部に電源用パッドを
配置し、金属キャップとに一体化された導体よりなるコ
ンタクト用突起物とを介して電源用パッドに電源供給を
行うなうものであるから、細いワイヤよりも配線抵抗が
極めて小さい。(Function) According to the present invention, a power supply pad is arranged in the center of a semiconductor chip, and power is supplied to the power supply pad via a contact protrusion made of a conductor integrated with a metal cap. Because it is a thin wire, the wiring resistance is much lower than that of a thin wire.
これにより、電源から半導体チップ上の電源パッドまで
の電圧降下が少なくできるので、素子の適正動作および
高速動作が保証される。This reduces the voltage drop from the power supply to the power supply pad on the semiconductor chip, ensuring proper and high-speed operation of the element.
更に電源用パッドを中央部に配置した分、従来の複数個
の電源用パッド領域として占有されていた部分が空き、
他の信号用パッド領域として有効に使うことができるの
で、高集積化に伴うチップサイズの増大を防止すること
ができる。Furthermore, since the power supply pad is placed in the center, the area previously occupied by multiple power supply pads becomes vacant.
Since it can be effectively used as a pad area for other signals, it is possible to prevent an increase in chip size due to higher integration.
以下、本発明を図示の一実施例により具体的に説明する
。Hereinafter, the present invention will be specifically explained with reference to an illustrated embodiment.
第１図（ａ）、（ｂ）は、本発明の実施例の半導体装置
の説明図である。FIGS. 1(a) and 1(b) are explanatory diagrams of a semiconductor device according to an embodiment of the present invention.
同図において、（ｂ）は組立途中の半導体装置の平面図
を、また、（ａ）は（ｂ）の平面図の八−入切断面図を
表わす。In the figure, (b) shows a plan view of the semiconductor device in the process of being assembled, and (a) shows an eight-fold cross-sectional view of the plan view of (b).
図において、１は銅にニッケルメッキを施した直径０．
５−霧φのコンタクト用突起物、２は銅にニッケルメッ
キを施した金属キャップで、コンタクト用突起物１と金
属キャップ２とは切削工作、溶接、接着用樹脂あるいは
高温半田などによる接着により一体化されている。In the figure, 1 is copper plated with nickel and has a diameter of 0.
5-Mist φ contact protrusion, 2 is a metal cap made of nickel-plated copper, and contact protrusion 1 and metal cap 2 are integrated by cutting, welding, bonding with adhesive resin or high-temperature solder, etc. has been made into
更に、３はＳｌチップ、４はＳｔチップ上のほぼ中央部
に形成されたＶＩＥ電源用パッドで、＾Ｕメフキなどに
より厚く形成されている。Further, 3 is a VIE power supply pad formed approximately in the center of the Sl chip and 4 on the St chip, and is thickly formed using U brushing or the like.
また、５はへ〇ワイヤで、Ｓｒチップ３と外部リード９
とをセラミック側壁８に設けられたスルーホール１１を
介して接続している。一般に、外部リード９は５００本
程度ある。６はＳｌチップ３を固定するための部分的に
Ａｕメツキされたセラミックからなるステージ、７はセ
ラミック基板、ｌＯは金属キャップ２によりＳｉチップ
３を密封するため半田などを流し込むキャップ封止溝、
１２は金属キャップ２と外部リード９とを接続するため
セラミック側壁８に設けられたスルーホール、１３はＳ
ｉチップ４をステージ６に接着するための樹脂膜、１６
はセラミック基板７とセラミック側壁８とからなるパッ
ケージを示す。In addition, 5 is a wire to 〇, between the Sr chip 3 and the external lead 9.
and are connected via a through hole 11 provided in the ceramic side wall 8. Generally, there are about 500 external leads 9. 6 is a stage made of ceramic partially plated with Au for fixing the Sl chip 3; 7 is a ceramic substrate; IO is a cap sealing groove into which solder or the like is poured in order to seal the Si chip 3 with the metal cap 2;
12 is a through hole provided in the ceramic side wall 8 for connecting the metal cap 2 and the external lead 9; 13 is an S
resin film for adhering the i-chip 4 to the stage 6, 16
shows a package consisting of a ceramic substrate 7 and a ceramic sidewall 8.
また、第２図は、本発明の実施例の半導体装置に搭載さ
れるＳＬチップの上面図である。Moreover, FIG. 2 is a top view of the SL chip mounted on the semiconductor device of the embodiment of the present invention.
同図において、１３はｖｃｃｔｔ源用パッド、１４は信
号用パッド、第１図と同じ符号のものは第１図と同じも
のを表す、なお、ｖ０電源用パッド４は、メツキなどの
手段により＾Ｕ膜が厚く形成されている。In the figure, 13 is a vcctt source pad, 14 is a signal pad, and the same symbols as in FIG. 1 represent the same ones as in FIG. The U film is formed thickly.
以上のように本発明の半導体装置によれば、外部リード
９と半導体チップ内のＶｔｔ電源用パッド４とを、電気
抵抗の極めて小さいコンタクト用突起物１と金属キャッ
プ２とを介して接続しているので、外部リード９からＶ
ｔｔ電源用バッド４までの電圧降下が少なくなる。この
ため、半導体チップ内の回路の高速動作および適正動作
が保証される。As described above, according to the semiconductor device of the present invention, the external lead 9 and the Vtt power supply pad 4 inside the semiconductor chip are connected via the contact protrusion 1 with extremely low electrical resistance and the metal cap 2. Therefore, from external lead 9 to V
The voltage drop to the tt power supply pad 4 is reduced. Therefore, high-speed operation and proper operation of the circuits within the semiconductor chip are guaranteed.
またｖ０電源用バッド４をチップの中央部に設けている
ので、各回路素子への電源供給を均一に行うことができ
る。Furthermore, since the v0 power supply pad 4 is provided in the center of the chip, power can be uniformly supplied to each circuit element.
更に、半導体チップの周辺部のｖ０電源用パッドを削除
することができるので、その空いた周辺部の領域を他の
信号用パッド配置領域として利用できるので、半導体集
積回路の高集積化が可能となる。Furthermore, since the v0 power supply pad on the periphery of the semiconductor chip can be deleted, the vacant area on the periphery can be used as an area for arranging other signal pads, making it possible to increase the integration density of semiconductor integrated circuits. Become.
次に、第１図を参照しながら、本発明の実施例の半導体
装置の製造方法について、概略説明する。Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be briefly explained with reference to FIG.
先ず、セラミック基板７とセラミック側壁８とで構成さ
れたパッケージ１６をグイボンディング用の治具にセッ
トする。First, the package 16 composed of the ceramic substrate 7 and the ceramic side wall 8 is set in a bonding jig.
次に、セラミック基板７のステージ６上の＾Ｕメツキ部
分に接着用の導電性樹脂膜１３を塗布した後、第２図に
示すＳｌチップ３を圧着して１５０°Ｃの熱処理を行な
う、これにより、導電性樹脂膜１３が硬化し、同時にＳ
ｉチップ３が固定される。Next, after applying a conductive resin film 13 for adhesion to the ^U plating part on the stage 6 of the ceramic substrate 7, the Sl chip 3 shown in FIG. 2 is crimped and heat treated at 150°C. As a result, the conductive resin film 13 is cured, and at the same time S
The i-chip 3 is fixed.
しかる後、Ｓｌチップ３上の電源用および信号用パッド
１３．１４とセラミック側壁８上にメタライズされたワ
イヤポンディングパッドとをＡｕワイヤ５でボンディン
グし、接続する。このワイヤボンディングは、ｖ０用電
源パッド４を除いてＳｌチップ３上の約５００箇所のポ
ンディングパッドすべてについて行う。Thereafter, the power supply and signal pads 13 and 14 on the Sl chip 3 and the wire bonding pads metallized on the ceramic side wall 8 are bonded and connected with the Au wire 5. This wire bonding is performed on all of the approximately 500 bonding pads on the Sl chip 3 except for the v0 power supply pad 4.
なお、セラミック側壁８上のワイヤポンディングパッド
は、スルーホール１１を介して外部リード９と接続され
ている。Note that the wire bonding pad on the ceramic side wall 8 is connected to the external lead 9 via a through hole 11.
また、セラミック側壁８上にはあらかじめキャップ封止
溝ｌＯが設けられており、この中に半田メツキ、その他
の方法で高温半田が被着されている。そして、パッケー
ジ１６をあらかじめ２５０℃に昇温して、半田を溶融し
ておく。Further, a cap sealing groove lO is previously provided on the ceramic side wall 8, into which high-temperature solder is applied by soldering or other methods. Then, the package 16 is heated to 250° C. in advance to melt the solder.
次に、金属キャップ２と一体化されているコンタクト用
突起物１を、Ｓｉチップ３のＶｔｔ用電源パッド４に軽
く圧着して接触させる。Next, the contact protrusion 1 integrated with the metal cap 2 is lightly pressed and brought into contact with the Vtt power supply pad 4 of the Si chip 3.
このとき、金属キャップ２の縁はキャップ封止溝１０の
溶融半田上に位置しており、これを冷却すれば半田が固
まり、密封がなされる。At this time, the edge of the metal cap 2 is located on the molten solder in the cap sealing groove 10, and when this is cooled, the solder hardens and sealing is achieved.
ここに、キャップ封止溝１０は、コンタクト用突起物１
とＳｉチップ３のＶｔｔ用電源パッド４との位置合わせ
を容易にし、また溶融半田は、コンタクト用突起物ｌと
Ｓｉチップ３のＶ、用電源パッド４との高さを調整する
ので、該突起物１とＶ□用電源バッド４とを確実に接触
させることができる。Here, the cap sealing groove 10 is connected to the contact protrusion 1
and the Vtt power supply pad 4 of the Si chip 3, and the molten solder adjusts the height of the contact protrusion 1 and the Vtt power supply pad 4 of the Si chip 3. The object 1 and the V□ power supply pad 4 can be brought into reliable contact.
また、Ｖｔｔ用電源パッド４をメツキなどにより厚くつ
けられたＡｕ１ｌ！で形成すれば、半田が固化・収縮す
る際に生じるコンタクト用突起物１からの衝撃をやわら
げることができるので、Ｓｉチップ３を保護することが
できる。Also, the Vtt power supply pad 4 is thickly attached by plating etc. Au1l! By forming the Si chip 3, it is possible to soften the impact from the contact protrusion 1 that occurs when the solder solidifies and shrinks, so the Si chip 3 can be protected.
なお、実施例ではコンタクト用突起物１に接触する電源
としてＶ■用電源を例として説明したが、ＶＣＣやＶＳ
Ｓ等の他の電源でもよい。In the embodiment, the power supply for V is used as an example of the power supply that comes into contact with the contact protrusion 1, but VCC and VS
Other power sources such as S may also be used.
また、障害が発生した時など、金属キャップ２を取り除
いて特性調査する必要がある場合があるが、金属キャッ
プ２を取り除くと、■、電源用パッド４は外部リード９
から開放されるので、素子特性は測れなくなる。In addition, when a failure occurs, it may be necessary to remove the metal cap 2 and investigate the characteristics, but if the metal cap 2 is removed,
Since it is released from , element characteristics cannot be measured.
このため、一般にはＳｔチップ３上に特性調査用のｖ０
電極用パッドを設けておき、外部リード９の１本と接続
しておくが望ましい。Therefore, in general, v0 for characteristic investigation is placed on the St chip 3.
It is desirable to provide an electrode pad and connect it to one of the external leads 9.
また短絡防止のため、金属キャップは絶縁コーティング
を行って、外部との絶縁を図ることが望ましい。Furthermore, to prevent short circuits, it is desirable that the metal cap be coated with an insulating coating to insulate it from the outside.
以上のように本発明の半導体装置によれば、半導体チッ
プ内の各素子に接続される電源線の配線抵抗を小さ（で
きるので、半導体集積回路の高速化に有効である。また
信号用パッドが効率よく半導体チップ周辺に配置できる
ので、半導体集積回路の高集積度化に有効である。As described above, according to the semiconductor device of the present invention, the wiring resistance of the power supply line connected to each element in the semiconductor chip can be reduced, which is effective for speeding up the semiconductor integrated circuit. Since it can be efficiently arranged around a semiconductor chip, it is effective in increasing the degree of integration of semiconductor integrated circuits.
第１図（ａ）、（ｂ）は、本発明の実施例の半導体装置
の説明図、
第２図は、本発明の実施例の半導体装置に搭載されるＳ
ｉチップの上面図、
第３図は、従来例の半導体装置の上面図、第４図は、他
の従来例の半導体装置の上面図である。
〔符号の説明〕
１・・・コンタクト用突起物、
２・・・金属キャップ、
３．１０３・・・Ｓｉチップ、
４．１４・・・電源用パッド、
５ 、１０４．１０５−Ａｕワイヤ、
６．１０６・・・ステージ、
７．１０７・・・セラミック基板、
８．１０８・・・セラミック側壁、
９・・・外部リード、
１１９・・・Ｖ□電源用外部リード、
１２９・・・ＶＣＣ電源用外部リード、２０９・・・信
号用外部リード、
ｌＯ・・・キャップ封止溝、
１１．１２・・・スルーホール、
１３・・・樹脂膜、
１５・・・信号用パッド、
１６・・・パフケージ。FIGS. 1(a) and (b) are explanatory diagrams of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention
FIG. 3 is a top view of an i-chip, FIG. 3 is a top view of a conventional semiconductor device, and FIG. 4 is a top view of another conventional semiconductor device. [Explanation of symbols] 1...Contact protrusion, 2...Metal cap, 3.103...Si chip, 4.14...Power supply pad, 5, 104.105-Au wire, 6 .106... Stage, 7.107... Ceramic substrate, 8.108... Ceramic side wall, 9... External lead, 119... External lead for V□ power supply, 129... For VCC power supply External lead, 209... Signal external lead, lO... Cap sealing groove, 11.12... Through hole, 13... Resin film, 15... Signal pad, 16... Puff cage .
Claims (1)
パッド（４）を有する半導体チップ（３）と、 前記半導体チップ（３）を収容し、前記半導体チップ（
３）の信号用パッド（１５）が接続される外部リード（
９）を有するパッケージと、前記パッケージに設けられ
て前記半導体チップ（３）を密封する金属キャップ（２
）とを有し、前記金属キャップ（２）には、前記電源用
パッド（４）に接続されるコンタクト用突起物（１）が
設けられ、前記半導体チップ（３）への電源供給は、前
記金属キャップ（２）を介して行われることを特徴とす
る半導体装置。[Claims] A semiconductor chip (3) having a signal pad (15) in a peripheral part and a power supply pad (4) in a central part; (
External lead (3) to which the signal pad (15) is connected
9), and a metal cap (2) provided on the package to seal the semiconductor chip (3).
), the metal cap (2) is provided with a contact protrusion (1) connected to the power supply pad (4), and power is supplied to the semiconductor chip (3) through the power supply pad (4). A semiconductor device characterized in that it is formed through a metal cap (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28529388A JPH02130946A (en) | 1988-11-11 | 1988-11-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28529388A JPH02130946A (en) | 1988-11-11 | 1988-11-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02130946A true JPH02130946A (en) | 1990-05-18 |
Family
ID=17689649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28529388A Pending JPH02130946A (en) | 1988-11-11 | 1988-11-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02130946A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100392843C (en) * | 2004-06-02 | 2008-06-04 | 富士通株式会社 | Semiconductor device |
| US20120187562A1 (en) * | 2007-03-26 | 2012-07-26 | International Business Machines Corporation | Semiconductor Package and Method for Fabricating the Same |
| US8564100B2 (en) | 2010-06-15 | 2013-10-22 | Renesas Electronics Corporation | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01205434A (en) * | 1988-02-10 | 1989-08-17 | Nec Corp | Semiconductor device |
-
1988
- 1988-11-11 JP JP28529388A patent/JPH02130946A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01205434A (en) * | 1988-02-10 | 1989-08-17 | Nec Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100392843C (en) * | 2004-06-02 | 2008-06-04 | 富士通株式会社 | Semiconductor device |
| US20120187562A1 (en) * | 2007-03-26 | 2012-07-26 | International Business Machines Corporation | Semiconductor Package and Method for Fabricating the Same |
| US8952551B2 (en) | 2007-03-26 | 2015-02-10 | International Business Machines Corporation | Semiconductor package and method for fabricating the same |
| US8564100B2 (en) | 2010-06-15 | 2013-10-22 | Renesas Electronics Corporation | Semiconductor device |
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