JPH0212893A - Manufacture of hybrid integrated circuit - Google Patents
Manufacture of hybrid integrated circuitInfo
- Publication number
- JPH0212893A JPH0212893A JP63163214A JP16321488A JPH0212893A JP H0212893 A JPH0212893 A JP H0212893A JP 63163214 A JP63163214 A JP 63163214A JP 16321488 A JP16321488 A JP 16321488A JP H0212893 A JPH0212893 A JP H0212893A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- terminal
- lead terminals
- insulating substrate
- terminal lands
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910000679 solder Inorganic materials 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 238000005476 soldering Methods 0.000 claims abstract description 7
- 239000000919 ceramic Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 16
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000007598 dipping method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Manufacturing Of Electrical Connectors (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路の製造方法に関し、特に集積回路
を搭載する絶縁基板へのリード端子の接続方法の改善に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a hybrid integrated circuit, and more particularly to an improvement in a method for connecting lead terminals to an insulating substrate on which an integrated circuit is mounted.
従来、混成集積回路では、絶縁基板に導体回路パターン
を形成した後、半導体素子やチップコンデンサ等の電子
部品を搭載し、更に絶縁基板に設けた端子ランドにリー
ド端子を半田デイツプ法により接続する方法がとられて
いる。Conventionally, in hybrid integrated circuits, after forming a conductor circuit pattern on an insulating substrate, electronic components such as semiconductor elements and chip capacitors are mounted, and then lead terminals are connected to terminal lands provided on the insulating substrate using a solder dip method. is taken.
上述した従来のリード端子接続方法では、リード端子の
ピッチが縮小化されるのに伴って隣接する端子ランドや
リード端子間で半田が接続される、所謂半田ブリッジが
生じ易くなり、リード接続後に短絡した半田を除去する
修正作業が必要とされる等、製造工数が多くなり、しか
も混成集積回路の信顛性が低下されるという問題がある
。In the conventional lead terminal connection method described above, as the pitch of lead terminals is reduced, so-called solder bridges, where solder is connected between adjacent terminal lands or lead terminals, tend to occur, resulting in short circuits after lead connection. There are problems in that the number of manufacturing steps increases, such as the need for correction work to remove the solder that has been applied, and the reliability of the hybrid integrated circuit is reduced.
本発明は半田ブリッジを抑制し、リード端子のピッチの
縮小化を可能とし、かつ接続作業の容易化を可能とする
混成集積回路の製造方法を提供することを目的としてい
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit that suppresses solder bridging, enables a reduction in the pitch of lead terminals, and facilitates connection work.
本発明の混成集積回路の製造方法は、セラミック等の絶
縁基板上に、その一部を端子ランドとする導体回路パタ
ーンを形成する工程と、この導体回路パターンの端子ラ
ンドを除く領域に半田を印刷する工程と、前記絶縁基板
に半導体素子やチップコンデンサ等の各種電子部品を搭
載し、かつこれら部品をリフローにより導体回路パター
ンに半田付けする工程と、前記端子ランドにリード端子
を接触させるとともに端子ランド上に半田チップを載置
する工程と、リフローにより載置した半田チップを溶融
させてリード端子を端子ランドに半田付けする工程とを
含んでいる。The method for manufacturing a hybrid integrated circuit of the present invention includes the steps of forming a conductive circuit pattern, a part of which serves as a terminal land, on an insulating substrate such as a ceramic substrate, and printing solder on an area of the conductive circuit pattern excluding the terminal land. a step of mounting various electronic components such as semiconductor elements and chip capacitors on the insulating substrate and soldering these components to a conductive circuit pattern by reflow; The process includes a step of placing a solder chip on top, and a step of melting the placed solder chip by reflow and soldering the lead terminal to the terminal land.
上述した製造方法では、端子ランド上に載置した半田チ
ップを溶融することによりリード端子の接続を実現し、
半田デイツプ法を不要として隣接端子間の半田ブリッジ
を防止する。In the manufacturing method described above, the connection of the lead terminal is realized by melting the solder chip placed on the terminal land.
To prevent solder bridges between adjacent terminals by eliminating the need for a solder dip method.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図及び第２図は本発明を製造工程順に示す斜視図で
ある。FIGS. 1 and 2 are perspective views showing the present invention in the order of manufacturing steps.
先ず、第１図のように、セラミック等からなる絶縁基板
１に導体回路パターン２を形成し、この導体回路パター
ン２の一部で絶縁基板１の一辺に沿って複数個の端子ラ
ンド３を形成する。そして、この導体回路パターン２上
には半田を印刷する。First, as shown in FIG. 1, a conductive circuit pattern 2 is formed on an insulating substrate 1 made of ceramic or the like, and a plurality of terminal lands 3 are formed along one side of the insulating substrate 1 using a part of this conductive circuit pattern 2. do. Then, solder is printed on this conductive circuit pattern 2.
このとき、端子ランド３及びその近傍領域には半田の印
刷を行なわない。At this time, no solder is printed on the terminal land 3 and its vicinity.
次いで、前記絶縁基板１に半導体素子４やチップコンデ
ンサ５等の各種電子部品を搭載し、絶縁基板１をリフロ
ー炉（図示せず）を通して半田を溶融させることにより
、前記半導体素子４やチップコンデンサ５等の実装を行
う。Next, various electronic components such as semiconductor elements 4 and chip capacitors 5 are mounted on the insulating substrate 1, and the semiconductor elements 4 and chip capacitors 5 are melted by passing the insulating substrate 1 through a reflow oven (not shown) to melt the solder. etc. will be implemented.
しかる上で、第２図に示すように端子ランド３に対して
リード端子６を接触させ、かつ端子ランド３上に半田チ
ップ７を載置する。この半田チップは、例えば２００μ
ｍの厚さで１．５Ｘ １．Ｏ＋ｒｎ＋＋角の大きさのも
のを用いる。そして、このままの状態でリフロー炉に通
し、載置した半田チップ７を溶融させ、リード端子６を
端子ランド３に半田付けする。Then, as shown in FIG. 2, the lead terminal 6 is brought into contact with the terminal land 3, and the solder chip 7 is placed on the terminal land 3. This solder chip is, for example, 200μ
1.5X with a thickness of m 1. Use one with an angle of O+rn++. Then, this state is passed through a reflow oven to melt the mounted solder chips 7 and solder the lead terminals 6 to the terminal lands 3.
その後、これまでと同様に外装を行うことにより、混成
集積回路を完成する。Thereafter, the hybrid integrated circuit is completed by packaging as before.
この製造方法によれば、リード端子６を端子ランド３に
半田付けする際に、半田デイツプ法を使用しないため、
隣接する端子ランドやリード端子のピッチ寸法が微小な
場合でも、これらの間で半田ブリッジが生じることを防
止できる。これにより、半田付は工程の後に短絡した半
田を除去する修正作業が不要とされ、しかも混成集積回
路の信頌性が向上できる。According to this manufacturing method, the solder dip method is not used when soldering the lead terminal 6 to the terminal land 3.
Even if the pitch between adjacent terminal lands or lead terminals is minute, it is possible to prevent solder bridges from occurring between them. This eliminates the need for correction work to remove short-circuited solder after the soldering process, and also improves the reliability of the hybrid integrated circuit.
以上説明したように本発明は、端子ランドにリード端子
を接触させるとともにその上に半田チップを載置し、か
つこの半田チップをリフローにより溶融させてリード端
子を端子ランドに半田付けしているので、半田デイツプ
によるリード端子の接続を不要とし、隣接端子間の半田
ブリッジを防止して接続作業の簡略化、及び混成集積回
路の信頬性の向上を図ることができる。As explained above, in the present invention, a lead terminal is brought into contact with a terminal land, a solder chip is placed on top of the lead terminal, and the solder chip is melted by reflow to solder the lead terminal to the terminal land. This eliminates the need to connect lead terminals using solder dips, prevents solder bridging between adjacent terminals, simplifies the connection work, and improves the reliability of the hybrid integrated circuit.
第１図及び第２図は本発明の製造方法を工程順に示す斜
視図である。
１・・・絶縁基板、２・・・導体回路パターン、３・・
・端子ランド、４・・・半導体素子、５・・・チップコ
ンデンサ、６・・・リード端子、７・・・半田チップ。1 and 2 are perspective views showing the manufacturing method of the present invention in order of steps. 1... Insulating substrate, 2... Conductor circuit pattern, 3...
- Terminal land, 4... Semiconductor element, 5... Chip capacitor, 6... Lead terminal, 7... Solder chip.
Claims (1)
ドとして構成される導体回路パターンを形成する工程と
、この導体回路パターンの端子ランドを除く領域に半田
を印刷する工程と、前記絶縁基板に半導体素子やチップ
コンデンサ等の各種電子部品を搭載し、かつこれら部品
をリフローにより導体回路パターンに半田付けする工程
と、前記端子ランドにリード端子を接触させるとともに
端子ランド上に半田チップを載置する工程と、リフロー
により載置した半田チップを溶融させてリード端子を端
子ランドに半田付けする工程とを含むことを特徴とする
混成集積回路の製造方法。1. A process of forming a conductor circuit pattern, a part of which is configured as a terminal land, on an insulating substrate such as a ceramic, a process of printing solder on an area of the conductor circuit pattern excluding the terminal land, and a process of printing a semiconductor on the insulating substrate. A process of mounting various electronic components such as elements and chip capacitors, and soldering these components to a conductive circuit pattern by reflow, and a process of bringing a lead terminal into contact with the terminal land and placing a solder chip on the terminal land. A method for manufacturing a hybrid integrated circuit, comprising the steps of: melting the mounted solder chip by reflow and soldering the lead terminal to the terminal land.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63163214A JPH0212893A (en) | 1988-06-30 | 1988-06-30 | Manufacture of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63163214A JPH0212893A (en) | 1988-06-30 | 1988-06-30 | Manufacture of hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0212893A true JPH0212893A (en) | 1990-01-17 |
Family
ID=15769469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63163214A Pending JPH0212893A (en) | 1988-06-30 | 1988-06-30 | Manufacture of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0212893A (en) |
-
1988
- 1988-06-30 JP JP63163214A patent/JPH0212893A/en active Pending
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