JPH0212350A - Information processor - Google Patents

Information processor

Info

Publication number
JPH0212350A
JPH0212350A JP63164010A JP16401088A JPH0212350A JP H0212350 A JPH0212350 A JP H0212350A JP 63164010 A JP63164010 A JP 63164010A JP 16401088 A JP16401088 A JP 16401088A JP H0212350 A JPH0212350 A JP H0212350A
Authority
JP
Japan
Prior art keywords
operand
storage means
instruction processing
operands
processing means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63164010A
Other languages
Japanese (ja)
Inventor
Tokuo Watanabe
渡邊　徳男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63164010A priority Critical patent/JPH0212350A/en
Publication of JPH0212350A publication Critical patent/JPH0212350A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To supply an operand at a high speed to an instruction processing means from a buffer memory means by giving the reading requests of plural blocks to a main memory means in the case the buffer memory stores no valid operand at all. CONSTITUTION:An instruction processing means 1 gives an operand reading request to a buffer memory 2. In the case a buffer memory part 21 stores no valid operand at all, the means 1 produces continuously the reading requests for plural blocks. A main memory means 3 processes successively the reading request produced by the means 2 and sends the operands to the means 2. A control part 22 stores successively the operands received from the means 3 in the part 21. In this case, the operand requested by the means 1 is included in the block that is returned first and therefore sent to the means 1. In such a way, the operands are supplied at a high speed to the means 1 from the means 2.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は情報処理装置に関し、特にオペランドを格納し
ている＃ｌｔ衝記憶手段に関するものであり、緩衝記憶
内に有効なオペランドが一つも存在しない時に於けるオ
ペランド供給の高速化に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device, and particularly relates to #lt memory means for storing operands, and the present invention relates to an information processing device that stores operands. This relates to speeding up the supply of operands when the data is not available.

〔従来の技術〕[Conventional technology]

従来、この種の情報処理装置は、命令処理手段より緩衝
記憶手段に対してオペランドの読み出し要求があった時
に、緩衝記憶手段はそのオペランドが現在緩衝記憶内に
存在するが否かを調査し、緩衝記憶内に存在した時は、
そのオペランドを命令処理手段へ送り、存在しない時は
、そのオペランドを含むブロックの読み出し要求のみを
主記憶手段に対して発行するとなっていた。Conventionally, in this type of information processing device, when an instruction processing means issues a request to read an operand to a buffer storage means, the buffer storage means investigates whether the operand currently exists in the buffer storage. When it exists in buffer memory,
The operand is sent to the instruction processing means, and if the operand does not exist, only a read request for the block containing the operand is issued to the main storage means.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の情報処理装置は、ｙＩＷ！記憶手段に対
して命令処理手段からオペランドの読み出し要求があっ
た時に、緩衝記憶手段は、そのオペランドが緩衝記憶内
に存在するか否かを調べ、存在しない時にそのオペラン
ドを含むブロックの読み出し要求のみを主記憶手段に対
して発行するようになっているので、Ｍ衝記憶内に有効
なオペランドが一つも存在しない場合に於いては、緩衝
記憶内に有効なオペランドが蓄積されるまでの間、命令
処理手段が要求するオへランドがｔａ街記憶内に存在す
る確率が低く、オペランド供給が遅くなるという欠点が
ある。The conventional information processing device described above is yIW! When there is a request to read an operand from the instruction processing means to the storage means, the buffer storage means checks whether the operand exists in the buffer storage, and if it does not exist, only requests to read the block containing the operand. is issued to the main memory means, so if there is no valid operand in the memory, until a valid operand is accumulated in the buffer memory, There is a drawback that the probability that the operand required by the instruction processing means exists in the data memory is low, and the operand supply becomes slow.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の情報処理装置の構成は、命令語の解読及び処理
を行う命令処理手段と、該命令処理手段が命令を処理す
る為に必要なオペランドを格納する主記憶手段と、前記
命令処理手段と前記主記憶手段との間にあって前記主記
憶手段に格納されているオペランドの一部の写しをブロ
ック単位で記憶し、前記命令処理手段がオペランドの読
み出し要求を発行した時に、該オペランドを含むブロッ
クの読み出し要求を前記主記憶手段に発行するとともに
、該ブロックと連続する複数ブロックの読み出し要求を
も前記主記憶手段に対して発行する為の制御回路を具備
した緩衝記憶手段とを含んで構成される事を特徴とする
。The information processing device of the present invention has a configuration including an instruction processing means for decoding and processing an instruction word, a main storage means for storing operands necessary for the instruction processing means to process the instruction, and the instruction processing means. A copy of a part of the operand stored in the main storage means between the main storage means and the main storage means is stored in units of blocks, and when the instruction processing means issues a read request for an operand, a copy of the block containing the operand is stored. Buffer storage means equipped with a control circuit for issuing a read request to the main storage means and also issuing read requests for a plurality of blocks consecutive to the block to the main storage means. characterized by things.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を示すブロック構成図であり
、１は命令処理手段、２は緩衝記憶手段、２１は緩衝記
憶部、２２は制御部、３は主記憶手段である。FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is an instruction processing means, 2 is a buffer storage means, 21 is a buffer storage section, 22 is a control section, and 3 is a main storage means.

命令処理手段１は、緩衝記憶手段４に対してオペランド
の読み出し要求を発行する。制御部２２はＩ［ｒ記憶部
２１の要求のあったオペランドが存在するか否かを調べ
、存在する時は、Ｍ衝記憶部２１から命令処理手段１ヘ
オペランドを送る。存在しない時は、主記憶手段３に対
して、要求のあったオペランドを含むブロックの読み出
し要求を発行するとともに、現在緩衝記憶部２１に有効
なオペランドが一つもない場合には、連続する複数のブ
ロックの読み出し要求をも発行する。主記憶手段３は緩
衝記憶手段２から発行された読み出し要求を順次処理し
、緩衝記憶手段２ヘオペランドを送る。制御部２２は主
記憶手段３から送られて来たオペランドを緩衝記憶部２
１へ順次格納するが、最初のブロックが返って来た時、
ブロックの中には命令処理手段１が要求しているオペラ
ンドが存在する為、それを命令処理手段１へ送る。The instruction processing means 1 issues an operand read request to the buffer storage means 4. The control section 22 checks whether the requested operand exists in the I[r storage section 21, and if it exists, sends the operand from the M storage section 21 to the instruction processing means 1. If the operand does not exist, a request to read the block containing the requested operand is issued to the main storage means 3, and if there is no valid operand in the buffer storage section 21, consecutive multiple operands are read out. It also issues a block read request. The main storage means 3 sequentially processes read requests issued from the buffer storage means 2 and sends operands to the buffer storage means 2. The control unit 22 stores the operands sent from the main storage unit 3 in the buffer storage unit 2.
1 in sequence, but when the first block is returned,
Since there is an operand requested by the instruction processing means 1 in the block, it is sent to the instruction processing means 1.

仮に命令処理手段とＭＩＩ記憶手段との間の単位時間を
１．緩衝記憶手段と主記憶手段との間の単位時間を５．
ブロックの大きさを１０とし、命令処理手段が第１のオ
ペランドから順次読み出し要求を発行したとする時、命
令処理手段が第１のオペランド要求を発行してから第１
１のオペランドを得るまでの時間は、従来技術では４２
であるのに対し、本実施例では３２となる。Suppose that the unit time between the instruction processing means and the MII storage means is 1. 5. Unit time between buffer storage means and main storage means.
Assuming that the block size is 10 and the instruction processing means issues read requests sequentially starting from the first operand, the instruction processing means issues the first operand request, then the first
In the conventional technology, the time it takes to obtain an operand of 1 is 42
However, in this embodiment, it is 32.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、Ｍ衝記憶に有効なオペラ
ンドが一つもない時に、主記憶手段に対して複数ブロッ
クの読み出し要求を行うことにより、命令処理手段への
緩衝記憶手段からのオペランド供給を高速に出来る効果
がある。As explained above, the present invention supplies operands from the buffer storage means to the instruction processing means by requesting the main storage means to read multiple blocks when there is no valid operand in the M memory. This has the effect of speeding up the process.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示すブロック構成図である
。 １・・・命令処理手段、２・・・ＭＷｔ記憶手段、２１
・・・制御部、２２・・・緩衝記憶部、３・・・主記憶
手段。FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Instruction processing means, 2... MWt storage means, 21
. . . control unit, 22 . . . buffer storage unit, 3 . . . main storage means.

Claims (1)

【特許請求の範囲】[Claims] 命令語の解読及び処理を行う命令処理手段と、該命令処
理手段が命令を処理する為に必要なオペランドを格納す
る主記憶手段と、前記命令処理手段と前記主記憶手段と
の間にあって前記主記憶手段に格納されているオペラン
ドの一部の写しをブロック単位で記憶し、前記命令処理
手段がオペランドの読み出し要求を発行した時に、該オ
ペランドを含むブロックの読み出し要求を前記主記憶手
段に発行するとともに、該ブロックと連続する複数ブロ
ックの読み出し要求をも前記主記憶手段に対して発行す
る為の制御回路を具備した緩衝記憶手段とを含んで構成
される事を特徴とする情報処理装置。an instruction processing means for decoding and processing instruction words; a main storage means for storing operands necessary for the instruction processing means to process the instructions; A copy of a part of the operand stored in the storage means is stored in block units, and when the instruction processing means issues a read request for the operand, a read request for the block containing the operand is issued to the main storage means. An information processing apparatus characterized in that the information processing apparatus further comprises buffer storage means having a control circuit for also issuing a read request for a plurality of blocks consecutive to the block to the main storage means.
JP63164010A 1988-06-29 1988-06-29 Information processor Pending JPH0212350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63164010A JPH0212350A (en) 1988-06-29 1988-06-29 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63164010A JPH0212350A (en) 1988-06-29 1988-06-29 Information processor

Publications (1)

Publication Number Publication Date
JPH0212350A true JPH0212350A (en) 1990-01-17

Family

ID=15785055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63164010A Pending JPH0212350A (en) 1988-06-29 1988-06-29 Information processor

Country Status (1)

Country Link
JP (1) JPH0212350A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105098A (en) * 1993-10-07 1995-04-21 Nec Corp Replace device of instruction cache

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105098A (en) * 1993-10-07 1995-04-21 Nec Corp Replace device of instruction cache

Similar Documents

Publication Publication Date Title
JPH03127147A (en) Information processing system
JPH07113903B2 (en) Cache storage control method
JPH01269142A (en) Buffer memory control system
JPH1196072A (en) Memory access control circuit
JPH0212350A (en) Information processor
JPS593774A (en) Access processing system
GB2037466A (en) Computer with cache memory
JPH02280246A (en) Information processor
JPS5853075A (en) Information processor provided with high speed separation buffer
JPH02257342A (en) Information processor
JPH0240717A (en) Information processor
JPH04260145A (en) Buffer storage device
JPS6391756A (en) Partial write instruction processing system for storage device
JP2895892B2 (en) Data processing device
JP2735400B2 (en) Asynchronous I / O control method
JPH0236011B2 (en)
JPS6242235A (en) Virtual stack system
JPH04264640A (en) Buffer storage device
JPH01142846A (en) Cache memory control system for information processor
JPH04291642A (en) Cache control system
JPS61165163A (en) Channel selecting system
JPS6243737A (en) Interruption control system
JPH0476139B2 (en)
JPS63103342A (en) Main memory controller
JPH01283653A (en) Memory pool managing system