JPH02119427A - Output buffer circuit - Google Patents

Output buffer circuit

Info

Publication number
JPH02119427A
JPH02119427A JP63273704A JP27370488A JPH02119427A JP H02119427 A JPH02119427 A JP H02119427A JP 63273704 A JP63273704 A JP 63273704A JP 27370488 A JP27370488 A JP 27370488A JP H02119427 A JPH02119427 A JP H02119427A
Authority
JP
Japan
Prior art keywords
output
power supply
circuit
buffer circuit
output buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63273704A
Other languages
Japanese (ja)
Inventor
Tomonaga Shigiyou
倫永 執行
Tsukasa Uneuchi
宇根内　司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP63273704A priority Critical patent/JPH02119427A/en
Publication of JPH02119427A publication Critical patent/JPH02119427A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manipulation Of Pulses (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To suppress the production of malfunction by providing a power voltage control circuit limiting a power voltage applied to an output inverter circuit. CONSTITUTION:A gate voltage of an N-channel transistor(TR) 2 and a P-channel TR 3 is controlled by resistors 6-8 connected in series between a power supply and a ground and the TRs are component of a power voltage control circuit of an output inverter circuit. Since the output of TRs 4, 5 is not in full swing in a range of the power voltage, an output load capacitor 9 is not completely charged and discharged, a transient current is decreased, thereby decreasing the drive of an internal power supply due to a power impedance. Thus, an output buffer circuit hardly causing malfunction is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は出力バッファ回路、特にＣＭＯ８型Ｏ８回路の
出力バッファ回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit, and particularly to an output buffer circuit of a CMO8 type O8 circuit.

〔従来の技術〕[Conventional technology]

一般に論理ＩＣにおいて論理出力を他のデバイスに接続
する為、そのインターフェイスとして出力バッファ回路
を使用している。このような従来の出力バッファ回路の
、−例を第３図に示す。第４図は第３図の動作を示す波
形図である。第３図において１０はインバータ、１１は
Ｐチャンネルトランジスタ、１２はＮチャンネルトラン
ジスタ、１３は出力負荷容量で、Ｐ、Ｎ両トランジスタ
１１゜１２とを電源と接地間に直列に接続し、インバー
タ１０の出力なＰ、Ｎ両トランジスタ１１．１２のゲー
トに接続し、Ｐ、Ｎ両トランジスタ１１゜１２の接続点
を出力とする構成となっている。尚、１３は負荷容量で
ある。Generally, in a logic IC, an output buffer circuit is used as an interface to connect the logic output to another device. An example of such a conventional output buffer circuit is shown in FIG. FIG. 4 is a waveform diagram showing the operation of FIG. 3. In FIG. 3, 10 is an inverter, 11 is a P-channel transistor, 12 is an N-channel transistor, and 13 is an output load capacitance. Both P and N transistors 11 and 12 are connected in series between the power supply and ground. It is connected to the gates of both the output P and N transistors 11 and 12, and the connection point between the P and N transistors 11 and 12 is configured as an output. Note that 13 is the load capacity.

第３図の動作を第４図で用いて説明する。第４図におい
て入力信号ｅはインバータ１０で反転され、その反転さ
れた出力がＰ、Ｎ両トランジスタ１１．１２により再度
反転され、入力信号ｅと同相で出力信号ｆとして出力さ
れる。の出力ｆが電源電圧範囲をフルスイングする為出
力負荷容量１３を完全に充放電する。充放電する時に流
れる電流がｇである。The operation shown in FIG. 3 will be explained using FIG. 4. In FIG. 4, an input signal e is inverted by an inverter 10, and the inverted output is again inverted by both P and N transistors 11 and 12, and is outputted as an output signal f in phase with the input signal e. Since the output f fully swings over the power supply voltage range, the output load capacitance 13 is completely charged and discharged. The current that flows during charging and discharging is g.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の出力バッファ回路は電源電圧範囲をフル
スイングする為出力負荷容量を完全に充放電することに
なる。この充放電電流は電源の２（インピーダンス）に
作用し、内部電源ドリフトを引き起す。このドリフトに
よりデバイスは種々の誤動作を生ずるという欠点がある
。The conventional output buffer circuit described above fully charges and discharges the output load capacitance because it swings over the full power supply voltage range. This charging/discharging current acts on the impedance of the power supply and causes internal power supply drift. This drift causes the device to malfunction in various ways, which is a drawback.

本発明の目的は以上の欠点を解決し、誤動作の生じにく
い出力バッファ回路を提供することにある。An object of the present invention is to solve the above-mentioned drawbacks and provide an output buffer circuit that is less likely to malfunction.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の出力バッファ回路は、互いに異なる２個のトラ
ンジスタを直列に接続した出力インバータ回路を備える
出力バッファ回路において、前記出力インバータ回路に
加える電源電圧を制限する電源電圧制限回路を備えるこ
とにより構成される。The output buffer circuit of the present invention includes an output inverter circuit in which two different transistors are connected in series, and includes a power supply voltage limiting circuit that limits the power supply voltage applied to the output inverter circuit. Ru.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の出力バッファ回路の回路図
、第２図はその動作を説明する波形図である。第１図に
おいて、１はインバータ、トランジスタ４，５はそれぞ
れＰチャンネルトランジスタ、Ｎチャンネルトランジス
タで出力インバータ回路を構成している。また、２はＮ
チャンネルトランジスタ、３はＰチャンネルトランジス
タで電源と接地間に直列に接続される抵抗６，７．８に
よりそれぞれのゲート電圧を制御されて、前記出力イン
バータ回路の電源電圧制限回路を構成している。尚、９
は出力負荷容量を示す。FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram illustrating its operation. In FIG. 1, 1 is an inverter, and transistors 4 and 5 are P-channel transistors and N-channel transistors, respectively, forming an output inverter circuit. Also, 2 is N
The channel transistor 3 is a P-channel transistor whose gate voltage is controlled by resistors 6, 7.8 connected in series between the power supply and ground, thereby forming a power supply voltage limiting circuit of the output inverter circuit. Furthermore, 9
indicates the output load capacity.

第１図の動作を第２図を用いて説明する。The operation shown in FIG. 1 will be explained using FIG. 2.

点ａがロウからハイに変化すると、点すはハイからロウ
にに変化する。このときトランジスタ４は導通状態、ト
ランジスタ５は非導通状態となる。When point a changes from low to high, point a changes from high to low. At this time, transistor 4 is in a conductive state and transistor 5 is in a non-conductive state.

トランジスタ４が導通状態によって電源電圧がシフトダ
ウンし、この電圧が点Ｃに出力される。このときトラン
ジスタ４を通って点ｄに電流が流れる。また点＆がハイ
からロウに変化すると点すはロウからハイに変化する。When transistor 4 is conductive, the power supply voltage is shifted down, and this voltage is output to point C. At this time, current flows through transistor 4 to point d. Also, when the point & changes from high to low, the point S changes from low to high.

このときトランジスタ４は非導通、トランジスタ５は導
通状態となる。At this time, transistor 4 becomes non-conductive and transistor 5 becomes conductive.

トランジスタ５が導通状態となると、接地と接続された
側の電源電圧制限回路によって接地電圧がシフトアップ
し、この電圧が点Ｃに出力される。When transistor 5 becomes conductive, the ground voltage is shifted up by the power supply voltage limiting circuit connected to the ground, and this voltage is output to point C.

このとき点ｄに電流が流れる。At this time, a current flows to point d.

従ってトランジスタ４，５は電源電圧範囲をフルスイン
グしないので出力負荷容量９を完全には充放電しなくな
り、第２図ｄの過渡電流が減少することで、電源インピ
ーダンスによる内部電源ドリフトを小さくすることが出
来る。Therefore, since the transistors 4 and 5 do not fully swing through the power supply voltage range, they do not completely charge or discharge the output load capacitance 9, reducing the transient current shown in Figure 2d, thereby reducing internal power supply drift due to power supply impedance. I can do it.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は電源電圧範囲をフルスイン
グさせないことにより誤動作を生じにくく出来る効果が
ある。また出力振幅が小さくなることから、遷移時間が
小さくなり、出力バッファ回路の伝達遅延時間も小さく
なる。更に、出力振幅はゲート電圧制御抵抗６，７．８
により、個々の負荷に対して最適値を選ぶことも可能と
なる。As explained above, the present invention has the advantage that malfunctions are less likely to occur by not making the power supply voltage range full swing. Furthermore, since the output amplitude is reduced, the transition time is reduced, and the transmission delay time of the output buffer circuit is also reduced. Furthermore, the output amplitude is determined by the gate voltage control resistance 6, 7.8
This makes it possible to select the optimum value for each individual load.

１．１０・・・・・・インバータ、２，５．１２・・・
・・・Ｎチャンネルトランジスタ、３，４．１１・・・
・・・Ｐチャンネルトランジスタ、６，７．８・・・・
・・抵抗、９．１３・・・・・・出力負荷容量。1.10...Inverter, 2,5.12...
...N-channel transistor, 3,4.11...
...P channel transistor, 6,7.8...
...Resistance, 9.13... Output load capacity.

Claims (1)

【特許請求の範囲】[Claims] 互いに極性の異なる２個のトランジスタを直列に接続し
た出力インバータ回路を備える出力バッファ回路におい
て、前記出力インバータ回路に加える電源電圧を制限す
る電源電圧制限回路を含むことを特徴とする出力バッフ
ァ回路An output buffer circuit comprising an output inverter circuit in which two transistors having different polarities are connected in series, the output buffer circuit comprising a power supply voltage limiting circuit that limits a power supply voltage applied to the output inverter circuit.
JP63273704A 1988-10-28 1988-10-28 Output buffer circuit Pending JPH02119427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63273704A JPH02119427A (en) 1988-10-28 1988-10-28 Output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63273704A JPH02119427A (en) 1988-10-28 1988-10-28 Output buffer circuit

Publications (1)

Publication Number Publication Date
JPH02119427A true JPH02119427A (en) 1990-05-07

Family

ID=17531396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63273704A Pending JPH02119427A (en) 1988-10-28 1988-10-28 Output buffer circuit

Country Status (1)

Country Link
JP (1) JPH02119427A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04150615A (en) * 1990-10-15 1992-05-25 Nec Corp Semiconductor logic circuit
JPH04172817A (en) * 1990-11-07 1992-06-19 Sharp Corp Digital integrated circuit
WO1995026077A1 (en) * 1994-03-24 1995-09-28 Siemens Aktiengesellschaft Low loss integrated circuit with reduced clock swing
WO1998024184A1 (en) * 1996-11-26 1998-06-04 Micron Technology, Inc. Adjustable output driver circuit
US6069504A (en) * 1997-01-06 2000-05-30 Micron Technnology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US6154058A (en) * 1998-04-06 2000-11-28 Nec Corporation Output buffer
JP2006197568A (en) * 2004-12-13 2006-07-27 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus using the same
US8038530B2 (en) 2005-02-28 2011-10-18 Wms Gaming Inc. Method and apparatus for filtering wagering game content
US8054111B2 (en) 2004-12-13 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance using the same
US8558576B2 (en) 2010-03-04 2013-10-15 Kabushiki Kaisha Toshiba Output buffer
US8861288B2 (en) 2011-12-23 2014-10-14 Semiconductor Energy Laboratory Co., Ltd. Level-shift circuit and semiconductor integrated circuit

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2876768B2 (en) * 1990-10-15 1999-03-31 日本電気株式会社 Semiconductor logic circuit
JPH04150615A (en) * 1990-10-15 1992-05-25 Nec Corp Semiconductor logic circuit
JPH04172817A (en) * 1990-11-07 1992-06-19 Sharp Corp Digital integrated circuit
WO1995026077A1 (en) * 1994-03-24 1995-09-28 Siemens Aktiengesellschaft Low loss integrated circuit with reduced clock swing
US6084434A (en) * 1996-11-26 2000-07-04 Micron Technology, Inc. Adjustable output driver circuit
WO1998024184A1 (en) * 1996-11-26 1998-06-04 Micron Technology, Inc. Adjustable output driver circuit
US6069504A (en) * 1997-01-06 2000-05-30 Micron Technnology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US6154058A (en) * 1998-04-06 2000-11-28 Nec Corporation Output buffer
JP2006197568A (en) * 2004-12-13 2006-07-27 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus using the same
US8054111B2 (en) 2004-12-13 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance using the same
US8179170B2 (en) 2004-12-13 2012-05-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance using the same
JP2014017887A (en) * 2004-12-13 2014-01-30 Semiconductor Energy Lab Co Ltd Semiconductor device and electronic apparatus
US8038530B2 (en) 2005-02-28 2011-10-18 Wms Gaming Inc. Method and apparatus for filtering wagering game content
US8558576B2 (en) 2010-03-04 2013-10-15 Kabushiki Kaisha Toshiba Output buffer
US8861288B2 (en) 2011-12-23 2014-10-14 Semiconductor Energy Laboratory Co., Ltd. Level-shift circuit and semiconductor integrated circuit

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