JPH02112250A - Method of coupling semiconductor chip with substrate - Google Patents

Method of coupling semiconductor chip with substrate

Info

Publication number
JPH02112250A
JPH02112250A JP1222780A JP22278089A JPH02112250A JP H02112250 A JPH02112250 A JP H02112250A JP 1222780 A JP1222780 A JP 1222780A JP 22278089 A JP22278089 A JP 22278089A JP H02112250 A JPH02112250 A JP H02112250A
Authority
JP
Japan
Prior art keywords
substrate
chip
bonding
ridge
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1222780A
Other languages
Japanese (ja)
Other versions
JP2678944B2 (en
Inventor
Alois Karl
アロイス、カール
Karl Osojnik
カール、オソイニク
Werner Spaeth
ウエルナー、シユペート
Guenther Waitl
ギユンター、ワイトル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH02112250A publication Critical patent/JPH02112250A/en
Application granted granted Critical
Publication of JP2678944B2 publication Critical patent/JP2678944B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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Abstract

PURPOSE: To make it possible to join a semiconductor chip to a substrate without needing a high-temperature process or such an auxiliary joining medium as a solder or a flux by a method wherein a small protuberance, the so-called bump, is formed on the rear of the chip or the substrate for the necessary contact of the chip with the substrate and the joining of the chip to the substrate is performed by a pressure and/or an ultrasonic action. CONSTITUTION: A protuberance 3 is formed on the rear of a semiconductor chip 1 for joining the chip 1 with a substrate 2. The joining of the chip 1 to the substrate 2 is performed by a pressure and an ultrasonic action. This protuberance 3 consists of a metal having a ductility and as the metal having the ductility, aluminum, silver or gold is specially suitable. It is preferable that the protuberance is formed in a diameter of 10 to 50μm and a height of 5 to 40μm. Thereby, direct joining of a photodiode to an integrated circuit can be performed without needing auxiliary bonding wires for connecting electrically the circuit with the photodiode.

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明はデバイスの支持部分、接触部分、絶縁部分又
は接続部分としての基板に半導体チップを結合する方法
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for bonding a semiconductor chip to a substrate as a supporting, contacting, insulating or connecting part of a device.

［従来の技術］ 種々の電子又は光・電子半導体デバイスの製造のために
、半導体チップを基板に結合することが必要である。そ
の際基板はデバイスの支持体として半導体材料から成り
、ダイオード、トランジスタ又は集積回路の形に構成す
ることができる。基板はまた結合部分として例えば導電
路を有することもでき、又は光導波路構造を有すること
もできる。更に基板は誘電性材料例えばセラミックから
成り、絶縁機能又は支持機能を受は持つこともできる。BACKGROUND OF THE INVENTION For the manufacture of various electronic or opto-electronic semiconductor devices, it is necessary to bond semiconductor chips to substrates. The substrate in this case consists of a semiconductor material as a support for the device and can be configured in the form of a diode, a transistor or an integrated circuit. The substrate can also have, for example, conductive tracks or optical waveguide structures as coupling parts. Furthermore, the substrate can be made of a dielectric material, for example a ceramic, and can have an insulating or supporting function.

また基板は電気的又は熱的接触部分又は結合部分として
、電圧源に接続するために又は場合によってはヒートシ
ンクへの必要な熱的接触を形成するために用いることも
できる。このような事例は例えば、レーザダイオードを
ペルチェ式冷却要素に結合することが必要であるときに
起こる。The substrate can also be used as an electrical or thermal contact or coupling part, for connecting to a voltage source or possibly forming the necessary thermal contact to a heat sink. Such a case occurs, for example, when it is necessary to couple a laser diode to a Peltier cooling element.

今日通常行われる半導体チップを基板に結合する方法に
際しては、半導体は合金化とろう伺けとにより又は接着
剤により熱的又は電気的に伝導性に基板上に取り付けら
れる。しかしながらこれらの方法は高価かつ複雑であり
、更にリードフレーム又はチップに不利に作用するおそ
れがある。例えば合金化の際に必要な比較的高い温度に
ノ、（づき、半導体装置の基板上に設けられ通常の方法
で用いられる導体路が浸透合金化するおそれがあるか、
又は拡散工程により既に完成された半導体チップ（例え
ばシリコン装置の基板）の中に存在するｐｎ接合が不都
合に変化させられるおそれがある。In the methods commonly used today for bonding semiconductor chips to substrates, semiconductors are thermally or electrically conductively attached to a substrate by alloying, soldering, or adhesives. However, these methods are expensive and complex, and can also be detrimental to the lead frame or chip. For example, due to the relatively high temperatures required during alloying, there is a risk that the conductor tracks provided on the substrate of the semiconductor device and used in a conventional manner may undergo penetrant alloying.
Alternatively, the diffusion process may undesirably alter the pn junctions present in already completed semiconductor chips (eg, silicon device substrates).

［発明が解決しようとする課題］ この発明の課題は、高温工程あるいはろう又はフラック
スのような補助的な結合媒体を必要とすることなく、半
導体チップを基板に結合する筒中で安価な方法を提供す
ることである。OBJECT OF THE INVENTION It is an object of the invention to provide an in-tube, inexpensive method of bonding a semiconductor chip to a substrate without the need for high-temperature processes or auxiliary bonding media such as wax or flux. It is to be.

［課題を解決するための手段］ この課題はこの発明に基づき、半導体チップ又は基板の
裏面が必要な結合のために***を形成するように構成さ
れ、***のために延性の金属が用いられ、基板との結合
が圧力及び／又は超音波作用のもとに行われることによ
り解決される。[Means for Solving the Problem] This problem is based on the invention, in which the back side of the semiconductor chip or substrate is configured to form a ridge for the necessary bonding, a ductile metal is used for the ridge, The solution is that the bonding with the substrate takes place under pressure and/or ultrasonic action.

この発明の有利な実施態様は請求項２以下に記載されて
いる。Advantageous embodiments of the invention are described in the subclaims.

この発明に基づく方法の場合には、半導体チップ又は基
板の裏面は必要な接触のために小さい***いわゆるバン
プを取り付けられるように構成される。この***は延性
の金属から成る。延性の金属としてはアルミニウム、銀
又は金が特に適している。***は１１０７ｔないし５０
ＪＬｍの直径と５μｍないし４０ｇｍの高さとを有する
のが有利である。基板との結合は圧力及び／又は超音波
により行われる。この結合方法の態様は現在広く採用さ
れているネイルヘッドｅポール番ポンディングに類似し
ている。その際基板は１８０℃ないし３００　’Ｏの温
度に予熱される（超音波併用熱圧着法）のが有利である
。In the method according to the invention, the back side of the semiconductor chip or the substrate is constructed in such a way that it can be fitted with small elevations, so-called bumps, for the necessary contact. This ridge is made of ductile metal. Particularly suitable ductile metals are aluminum, silver or gold. The uplift is 1107t or 50
Advantageously, it has a diameter of JLm and a height of 5 μm to 40 gm. Bonding to the substrate is achieved by pressure and/or ultrasound. This aspect of the bonding method is similar to the currently widely adopted nail head e-pole bonding. The substrate is then preferably preheated to a temperature of 180 DEG C. to 300 DEG C. (thermo-compression method with ultrasonic waves).

パッド上に前記の***又は***を備えた支持体を取り付
けるときには、この発明に基づく方法を集積回路のポン
ディングのために用いることもできる。The method according to the invention can also be used for bonding integrated circuits when mounting the above-mentioned ridges or supports with ridges on pads.

［作用効果］ この発明に基づく方法により簡単かつ安価にいわゆるピ
ギーバック装置を実現することもできる。例えば両方向
のシリアルなデータ交換のためのピギーバック・ダイオ
ード装置の場合には、例えば発光ダイオードが比較的小
さい光出射角を備えた光送信器として、光ファイバの導
入のために孔を備えた比較的大きいホトダイオードの面
の下方に、発光ダイオードから出射される光の主ビーム
円錐がホトダイオードの孔の下方に来るように組み立て
られる。[Operation and Effect] A so-called piggyback device can be easily and inexpensively realized by the method based on the present invention. For example, in the case of piggyback diode devices for bidirectional serial data exchange, e.g. light-emitting diodes are equipped with holes for the introduction of optical fibers, as light transmitters with a relatively small light exit angle. A large photodiode is assembled below the surface of the photodiode in such a way that the main beam cone of light emitted by the light emitting diode is below the hole of the photodiode.

この発明に基づく方法の特別の長所は、非常に簡単なピ
ギーバック・ハイブリッドを製造できるということにあ
る。ガラスファイバによる最近の情報伝送のためには、
ホトダイオードが前置増幅器集積回路と共に一つのパッ
ケージの中にハイブリッド化されている検出器が必要と
なる。この発明に基づく方法により、電気的接続のため
に補助的なポンディングワイヤを必要とすることなく、
集積回路及びホトダイオードの直接の結合が可能となる
。A particular advantage of the method according to the invention is that very simple piggyback hybrids can be produced. For modern information transmission through glass fiber,
A detector is required in which a photodiode is hybridized with a preamplifier integrated circuit in one package. The method according to the invention eliminates the need for auxiliary bonding wires for electrical connection.
Direct coupling of integrated circuit and photodiode is possible.

ワイヤを用いない直接の結合技術によりキャパシタンス
及びインダクタンスの非常に小さい前置増幅器を実現す
ることができ、それによりこの前置増幅器は非常に良好
な伝送特性を有する。更にピギーバック装置は場所をと
らず、それにより標準パッケージ（Ｔｏ形パッケージ）
の採用が可能となる。Direct coupling techniques without wires make it possible to realize preamplifiers with very low capacitances and inductances, so that these preamplifiers have very good transmission properties. Furthermore, the piggyback device does not take up much space, which makes it easy to use in a standard package (To-type package).
It becomes possible to hire

この発明に基づく結合方法の別の適用分野は光半導体送
信器（発光ダイオード及び赤外発光ダイオード）である
。Another field of application of the coupling method according to the invention is optical semiconductor transmitters (light-emitting diodes and infrared light-emitting diodes).

ヒートシンクのそばにｐｎ接合を有する（倒立組立）半
導体送信器の場合には、導電性接着剤又はろうを使用す
る従来の結合方法の場合に短絡の危険が存在する。この
発明に基づく***（バンプ）結合方法によればこの危険
は確実に避けられる。また半導体送信器の出射特性が損
なわれない。特に妨げとなる残留接着剤が存在しないこ
とにより、発光半導体デバイスの縁での光吸収又は散乱
が避けられる。In the case of semiconductor transmitters with a pn junction next to the heat sink (inverted assembly), there is a risk of short circuits with conventional bonding methods using conductive adhesives or solders. The bump bonding method according to the invention reliably avoids this risk. Furthermore, the emission characteristics of the semiconductor transmitter are not impaired. In particular, the absence of interfering residual adhesive avoids light absorption or scattering at the edges of the light emitting semiconductor device.

この発明に基づく方法の重要な長所は従来の結合方法又
は接触方法に比べて特に、***構造により結合しようと
する半導体チップと基板との間の間隔を自由に調節でき
ることにある。An important advantage of the method according to the invention compared to conventional bonding or contacting methods is, in particular, that the distance between the semiconductor chip and the substrate to be bonded can be freely adjusted by means of the raised structure.

［実施例］ 次にこの発明に基づく結合方法の一実施例と複数の適用
例とを示す図面により、この発明の詳細な説明する。[Example] Next, the present invention will be described in detail with reference to drawings showing an example and a plurality of application examples of the coupling method based on the present invention.

第１図に示された一実施例の場合には、半導体チップｌ
の裏面はチップｌと基板２との間の結合のために***３
が形成されるように構成される。In one embodiment shown in FIG.
The back side of the chip has a raised ridge 3 for bonding between the chip l and the substrate 2.
is configured so that it is formed.

半導体チップ１と基板２どの結合は圧力及び超音波によ
り行われる。***３はこの実施例では約１１０７ｚの直
径を有する比較的小さい***部分Ａと、約５０μｍの直
径を有する比較的大きい段落部分Ｂとから成る。***部
分Ａの段落部分Ｂに対する比率は、結合の際に結合エネ
ルギーが***部分Ａの中で変換され、段落部分Ｂの形状
寸法がほとんど変化しない（間隔片としての機能）よう
に調節されるのが有利である。Bonding between the semiconductor chip 1 and the substrate 2 is performed using pressure and ultrasonic waves. The ridge 3 in this example consists of a relatively small raised section A with a diameter of approximately 1107z and a relatively large stepped section B with a diameter of approximately 50 μm. The ratio of the raised part A to the stepped part B is adjusted so that during bonding, the bonding energy is converted in the raised part A, and the geometry of the stepped part B hardly changes (functioning as a spacing piece). is advantageous.

第２図は適用例として、半導体チップ１としてのホトダ
イオードと基板２としての半導体集積回路との結合を示
す。蛇行状の矢印６によりホトダイオード（チップ（１
）上への光入射方向が示されている。半導体チップ（ホ
トダイオード）１と基板（集積回路）２との必要な結合
を***３が受は持ち、この***はこの適用例ではｎ形電
極（パッド）４又はｐ形電極（パッド）５とこれに対応
するホトダイオード（チップ１）の図示されていない電
極との間に設けられている。FIG. 2 shows, as an application example, a connection between a photodiode as a semiconductor chip 1 and a semiconductor integrated circuit as a substrate 2. The meandering arrow 6 indicates the photodiode (chip (1)
) The direction of light incidence upward is shown. The ridge 3 provides the necessary bond between the semiconductor chip (photodiode) 1 and the substrate (integrated circuit) 2, which in this application is connected to the n-type electrode (pad) 4 or the p-type electrode (pad) 5. and an electrode (not shown) of a photodiode (chip 1) corresponding to the photodiode (chip 1).

第３図に示された適用例の場合には、半導体チップｌと
して発光ダイオードが基板２としての導体路に***３を
介して結合される。発光ダイオード（チップ１）に結合
された導体路（基板２）は反射器として構成されるのが
合目的であり、第２の導体路はポンディングワイヤ７を
介して発光ダイオードに対する必要な第２の接触を受は
持つ。In the application example shown in FIG. 3, a light-emitting diode as semiconductor chip l is connected via a bump 3 to a conductor track as substrate 2. In the case of the application shown in FIG. The conductor track (substrate 2) connected to the light-emitting diode (chip 1) is expediently designed as a reflector, the second conductor track being connected via a bonding wire 7 to the necessary second conductor track for the light-emitting diode. Uke has contact with

第４図はこの発明に基づく方法の別の適用例として、チ
ップ１としてのホトダイオードと基板２としての前置増
幅器との***３を介しての結合を示す。この適用例では
ｐ形電極５がホトダイオード（チップ（１）のｐ形拡散
領域８に結合されている。基板２（前置増幅器）に通じ
る***３はｎ形電極（パッド）４上に設けられている。FIG. 4 shows a further application of the method according to the invention, in which a photodiode as chip 1 and a preamplifier as substrate 2 are coupled via a bump 3. In FIG. In this application a p-type electrode 5 is coupled to a p-type diffusion region 8 of the photodiode (chip (1)). A ridge 3 leading to the substrate 2 (preamplifier) is provided on the n-type electrode (pad) 4. ing.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明に基づく結合方法の一実施例としての
***の側面図、第２図ないし第４図はそれぞれ結合方法
の異なる適用例の側面図である。 ｌ・・・半導体チップ ２・・・基板 ３・・・*** Ａ・・・***部分 Ｂ・・・段落部分FIG. 1 is a side view of a protuberance as an embodiment of the bonding method according to the present invention, and FIGS. 2 to 4 are side views of different application examples of the bonding method. l... Semiconductor chip 2... Substrate 3... Protrusion A... Protrusion portion B... Paragraph portion

Claims (6)

【特許請求の範囲】[Claims] （１）デバイスの支持部分、接触部分、絶縁部分又は接
続部分としての基板に半導体チップを結合する方法にお
いて、半導体チップ（１）又は基板（２）の裏面が必要
な結合のために***（３）を形成するように構成され、
***（３）のために延性の金属が用いられ、基板（２）
との結合が圧力及び／又は超音波作用のもとに行われる
ことを特徴とする半導体 チップを基板に結合するための方法。(1) A method of bonding a semiconductor chip to a substrate as a supporting part, a contact part, an insulating part or a connecting part of a device, in which the back side of the semiconductor chip (1) or the substrate (2) is raised (3) for the necessary bonding. ),
A ductile metal is used for the ridges (3) and the substrate (2)
A method for bonding a semiconductor chip to a substrate, characterized in that the bonding is carried out under pressure and/or ultrasonic action. （２）***（３）のための延性の金属としてアルミニウ
ム、銀又は金が用いられることを特徴とする請求項１記
載の方法。2. Process according to claim 1, characterized in that the ductile metal for the elevations (3) is aluminum, silver or gold. （３）***（３）の直径が１０μｍないし５０μｍであ
り、***（３）の高さが５μｍないし４０μｍであるこ
とを特徴とする請求項１又は２記載の方法。3. A method according to claim 1, characterized in that the diameter of the ridge (3) is between 10 μm and 50 μm and the height of the ridge (3) is between 5 μm and 40 μm. （４）***（３）が比較的小さい***部分（Ａ）と比較
的大きい段落部分（Ｂ）とから形成され、***部分（Ａ
）の段落部分（Ｂ）に対する比率は、結合の際に結合エ
ネルギーが***部分（Ａ）の中で変換され、段落部分（
Ｂ）の形状寸法がほとんど変化しないように調節される
ことを特徴とする請求項１ないし３の一つに記載の方法
。(4) The ridge (3) is formed from a relatively small ridge portion (A) and a relatively large paragraph portion (B), and the ridge (3) is formed from a relatively small ridge portion (A) and a relatively large step portion (B)
) to the paragraph part (B), the bond energy is converted in the raised part (A) during bonding, and the ratio of the paragraph part (
4. Method according to claim 1, characterized in that the geometry of B) is adjusted in such a way that it hardly changes. （５）基板（２）がほぼ１８０℃ないし３００℃の温度
に予熱されることを特徴とする請求項１ないし４の一つ
に記載の方法。5. Method according to claim 1, characterized in that the substrate (2) is preheated to a temperature of approximately 180° C. to 300° C. （６）個別半導体チップ、半導体集積回路又は発光ダイ
オードをホトダイオードないし導体路に、又はホトダイ
オードを前置増幅器に、 又はレーザダイオードをヒートシンクに、 又はチップコンデンサ、チップ抵抗及び同様のデバイス
を結合することを特徴とする請求項１ないし５の一つに
記載の方法。(6) coupling individual semiconductor chips, semiconductor integrated circuits or light emitting diodes to photodiodes or conductor tracks, or photodiodes to preamplifiers, or laser diodes to heat sinks, or chip capacitors, chip resistors and similar devices; Method according to one of claims 1 to 5, characterized in that:
JP1222780A 1988-08-31 1989-08-28 Method for bonding a semiconductor chip to a substrate Expired - Fee Related JP2678944B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3829538.5 1988-08-31
DE3829538A DE3829538A1 (en) 1988-08-31 1988-08-31 METHOD FOR CONNECTING A SEMICONDUCTOR CHIP TO A SUBSTRATE

Publications (2)

Publication Number Publication Date
JPH02112250A true JPH02112250A (en) 1990-04-24
JP2678944B2 JP2678944B2 (en) 1997-11-19

Family

ID=6361979

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1222780A Expired - Fee Related JP2678944B2 (en) 1988-08-31 1989-08-28 Method for bonding a semiconductor chip to a substrate

Country Status (3)

Country Link
US (1) US5027995A (en)
JP (1) JP2678944B2 (en)
DE (1) DE3829538A1 (en)

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Also Published As

Publication number Publication date
DE3829538C2 (en) 1993-08-05
JP2678944B2 (en) 1997-11-19
US5027995A (en) 1991-07-02
DE3829538A1 (en) 1990-03-08

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