JPH02104446U - - Google Patents
Info
- Publication number
- JPH02104446U JPH02104446U JP1074089U JP1074089U JPH02104446U JP H02104446 U JPH02104446 U JP H02104446U JP 1074089 U JP1074089 U JP 1074089U JP 1074089 U JP1074089 U JP 1074089U JP H02104446 U JPH02104446 U JP H02104446U
- Authority
- JP
- Japan
- Prior art keywords
- information
- circuit
- input
- data
- normal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Hardware Redundancy (AREA)
Description
第１図は、マイコンに入力される情報をパラレ
ルにしてＡ系とＢ系の２つの情報を入力した例を
示すブロツク図、第２図は、第１図におけるマイ
コンのブロツク図、第３図は、マイコンから出力
される情報を入力してＡ系とＢ系の２つの情報を
比較するようにしたブロツク図である。
ＭＰＵ：マイクロプロセツサ、１０：排他的論
理和回路、１１：異常検知回路、１４，１６，１
７，１９……論理積回路。
Figure 1 is a block diagram showing an example of inputting information to a microcomputer in parallel and inputting two types of information, A and B. Figure 2 is a block diagram of the microcomputer in Figure 1. Figure 3 This is a block diagram in which information output from a microcomputer is input and two pieces of information, A-system and B-system, are compared. MPU: Microprocessor, 10: Exclusive OR circuit, 11: Abnormality detection circuit, 14, 16, 1
7,19...Logic product circuit.
Claims (1)
にしてＡ系、Ｂ系入力としてマイコン（ＭＰＵ）
に入力し、又はマイコン（ＭＰＵ）からのビツト
情報からなる出力情報を入力してＡ系、Ｂ系出力
情報として、該Ａ系及びＢ系情報を排他的論理和
回路１０に入力してその出力情報が“１”データ
がある場合はＡ系とＢ系の情報が不一致である旨
を検知する異常検知回路１１と、前記排他的論理
和１０の反転情報とＡ系の反転情報との論理積演
算をする論理積回路１４及びその反転情報と前記
異常検知回路１１で検知した異常情報との論理積
演算をする論理積回路１６で“０”データの一致
により“０”側の正常とする手段と、排他的論理
和回路１０の反転情報とＡ系情報との論理積演算
をする論理積回路１７及びその反転情報と前記異
常検知回路１１で検知した異常情報との論理積演
算をする論理積回路１９で“０”データの一致に
より“１”側の正常とする手段とからなり、“０
”データ側の正常と“１”データ側の正常とで入
出力情報が正常であるとすることを特徴とする入
出力情報の検知装置。 Input information consisting of one bit information is parallelized and used as A-system and B-system input to the microcontroller (MPU).
or input output information consisting of bit information from a microcomputer (MPU) as A-system and B-system output information, input the A-system and B-system information to the exclusive OR circuit 10, and output it. An abnormality detection circuit 11 that detects that the information of the A system and B system does not match when there is "1" data, and a logical product of the inverted information of the exclusive OR 10 and the inverted information of the A system means for determining normality on the "0" side by matching "0" data in an AND circuit 14 that performs an operation and an AND circuit 16 that performs an AND operation between its inverted information and the abnormality information detected by the abnormality detection circuit 11; and an AND circuit 17 that performs an AND operation between the inverted information of the exclusive OR circuit 10 and the A-system information, and an AND operation that performs an AND operation between the inverted information and the abnormality information detected by the abnormality detection circuit 11. In the circuit 19, when the "0" data matches, the "1" side is determined to be normal.
An input/output information detection device characterized in that the input/output information is determined to be normal depending on whether the data side is normal or the data side is normal when the data is normal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1074089U JPH02104446U (en) | 1989-01-31 | 1989-01-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1074089U JPH02104446U (en) | 1989-01-31 | 1989-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02104446U true JPH02104446U (en) | 1990-08-20 |
Family
ID=31218667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1074089U Pending JPH02104446U (en) | 1989-01-31 | 1989-01-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02104446U (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55154639A (en) * | 1979-05-18 | 1980-12-02 | Sanyo Electric Co Ltd | Control system for microcomputer |
| JPS55157022A (en) * | 1979-05-24 | 1980-12-06 | Matsushita Electric Ind Co Ltd | Output circuit for microcomputer |
| JPS5659335A (en) * | 1979-10-18 | 1981-05-22 | Nec Corp | Bus check system |
| JPS5851359B2 (en) * | 1978-03-06 | 1983-11-16 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | memory controller |
-
1989
- 1989-01-31 JP JP1074089U patent/JPH02104446U/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5851359B2 (en) * | 1978-03-06 | 1983-11-16 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | memory controller |
| JPS55154639A (en) * | 1979-05-18 | 1980-12-02 | Sanyo Electric Co Ltd | Control system for microcomputer |
| JPS55157022A (en) * | 1979-05-24 | 1980-12-06 | Matsushita Electric Ind Co Ltd | Output circuit for microcomputer |
| JPS5659335A (en) * | 1979-10-18 | 1981-05-22 | Nec Corp | Bus check system |
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