JPH02100142A - Saving and restoring system for arbitrary register - Google Patents
Saving and restoring system for arbitrary registerInfo
- Publication number
- JPH02100142A JPH02100142A JP25296988A JP25296988A JPH02100142A JP H02100142 A JPH02100142 A JP H02100142A JP 25296988 A JP25296988 A JP 25296988A JP 25296988 A JP25296988 A JP 25296988A JP H02100142 A JPH02100142 A JP H02100142A
- Authority
- JP
- Japan
- Prior art keywords
- register
- saving
- restoring
- arbitrary
- command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 5
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、レジスタ退避、復帰方式に関し、特に、任意
のレジスタの退避、復帰方式に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a register saving and restoring method, and particularly to an arbitrary register saving and restoring method.
従来の技術
従来、レジスタ退避、復帰の方式としては、個々のレジ
スタを１つずつ退避、復帰させるか、または複数のレジ
スタを固定で退避、復帰させるものであり、任意のレジ
スタを退避、復帰させることができなかった。Conventional technology Conventionally, the register saving and restoring methods were to save and restore individual registers one by one, or to save and restore a fixed number of registers, and to save and restore any register. I couldn't.
発明が解決しようとする課題
上述した、従来のし・ジスタ退避、復帰では、任意のレ
ジスタを退避、復帰させようとする時に、個々のレジス
タの退避、復帰を目的のレジスタすべてに行うか、もし
くは退避、復帰させる必要のないレジスタも含めて複数
のレジスタを一度に退避、復帰させなければならないた
めに、オーバヘッドが大きいという欠点がある。Problems to be Solved by the Invention In the above-mentioned conventional register saving and restoring, when saving and restoring any register, it is necessary to save and restore each register to all target registers, or Since a plurality of registers, including registers that do not need to be saved or restored, must be saved and restored at once, there is a drawback that overhead is large.
本発明は従来の技術に内在する上記欠点を解消する為に
なされたものであり、従って本発明の目的は、任意のレ
ジスタの退避、復帰をそれぞれ一つの命令で実行し、レ
ジスタの退避、復帰のオーバヘッドを小さくすることを
可能とした新規なレジスタ退避、復帰方式を提供するこ
とにある。The present invention has been made in order to eliminate the above-mentioned disadvantages inherent in the conventional technology, and therefore, an object of the present invention is to save and restore arbitrary registers by each one instruction, and to save and restore arbitrary registers. The purpose of the present invention is to provide a new register saving and restoring method that makes it possible to reduce the overhead of registers.
課題を解決するための手段
上記目的を達成する為に、゛本発明に係る任意のレジス
タ退避、復帰方式は、マイクロコンピュータ内の複数の
汎用レジスタと、該汎用レジスタの各、りの退避・非退
避、復帰・非復帰を示すレジスタ（コマンドレジスタ）
と、前記汎用レジスタを退避させるスタックエリアと、
任意の汎用レジスタを退避、復帰させる命令とを有して
いる。Means for Solving the Problems In order to achieve the above object, the arbitrary register saving and restoring method according to the present invention provides a method for saving and restoring a plurality of general-purpose registers in a microcomputer and saving and restoring each of the general-purpose registers. Register indicating save, return/non-return (command register)
and a stack area for saving the general-purpose register,
It has instructions to save and restore arbitrary general-purpose registers.
実施例
次に本発明をその好ましい一実施例について図面を参照
して具体的に説明する。Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.
第１図は本発明の一実施例を示すブロック構成図である
。FIG. 1 is a block diagram showing one embodiment of the present invention.
第１図を参照するに、本発明の一実施例は、任意のレジ
スタ退避、復帰命令を含むプログラムを内蔵するＲＯＭ
Ｉ １と、スタックエリアを含むＲＡＭ１２と、任意の
レジスタ退避、復帰命令をデコード可能なデコーダ１３
と、レジスタ退避・非退避、復帰・非復帰を示すコマン
ドレジスタ１４と、スタックポインタを含む汎用レジス
タ群１５と、演算実行とアドレス決定を行うＡＬＵ、
ＢＣＵＩ６と、プログラムカウンタ１７と、アドレスバ
ス１８と、データバス１９とで構成されている。Referring to FIG. 1, one embodiment of the present invention is a ROM containing a program including arbitrary register save and restore instructions.
I1, a RAM 12 including a stack area, and a decoder 13 capable of decoding arbitrary register save and restore instructions.
, a command register 14 that indicates register saving/non-saving, restoration/non-returning, a general-purpose register group 15 including a stack pointer, and an ALU that executes calculations and determines addresses.
It is composed of a BCUI 6, a program counter 17, an address bus 18, and a data bus 19.
今、任意のレジスタを退避させようとする時にＲＯＭＩ
Ｉには、コマンドレジスタ１４に値を格納する命令と
任意のレジスタを退避する命令が内蔵されている。Now, when trying to save any register, ROMI
I has a built-in instruction to store a value in the command register 14 and an instruction to save an arbitrary register.
第２図は第１図のコマンドレジスタ１４と汎用レジスタ
群！５との対応関係を示す図である。コマンドレジスタ
１４のビットが“１″の時には、対応するレジスタは任
意のレジスタ退避、復帰命令により退避、復帰させられ
る。コマンドレジスタ１４のビットが“Ｏ”の時には、
対応するトジスタは、任意のレジスタ退避、復帰命令に
より退避、復帰させられない。Figure 2 shows the command register 14 in Figure 1 and a group of general-purpose registers! 5 is a diagram showing the correspondence relationship with 5. When a bit in the command register 14 is "1", the corresponding register is saved and restored by an arbitrary register save and restore command. When the bit of command register 14 is “O”,
The corresponding register cannot be saved or restored by any register save or restore command.
第３図は、第１図のコマ〉′ドレジスク１４と汎用レジ
スタ群１５とＲＡｌｉ１２の一部であるスタックエリア
を示している。今、コマンドレジスタ１４に値を格納す
る命令により、コマンドレジスタ１４に０１０１０１０
１０１０１０１０１Ｂが格納されている時には、任意の
レジスタ退避命令を実行することにより、スタックエリ
アには最初にレジスタＲ１がスタックされ、以下図のよ
うにレジスタＲ１５までスタックされた後、最後にコマ
ンドレジスタがスタックされる。FIG. 3 shows a stack area which is a part of the frame>' register disk 14, general-purpose register group 15, and RAli 12 in FIG. Now, by the instruction to store a value in the command register 14, 0101010 is stored in the command register 14.
When 101010101B is stored, by executing any register save instruction, register R1 is stacked in the stack area first, register R15 is stacked as shown in the figure below, and finally the command register is stacked. be done.
任意のレジスタ復帰の時には、退避時に最後に退避され
たコマンドし・ジスタが最初に復帰し、コマンドレジス
タにより、順次、汎用レジスタが復帰する。When restoring any register, the command register that was saved last at the time of saving is restored first, and the general-purpose registers are sequentially restored by the command register.
発明の詳細
な説明したように、本発明によれば、あらかじめ退避し
ておくレジスタをコマンドレジスタに登録することによ
り、任意のレジスタの退避、復帰をそれぞれ一つの命令
で実行でき、なおかつレジスタ退避、復帰のオーバヘッ
ドを小さくできる効果が得られる。As described in detail, according to the present invention, by registering the register to be saved in advance in the command register, it is possible to save and restore any register with a single instruction, and to save and restore the register. This has the effect of reducing the return overhead.
第１図は本発明の一実施例を示すブロック構成図、第２
図は本発明に係るコマンドレジスタと汎用レジスタの対
応関係を示す図、第３図はコマンドレジスタの一例と任
意のレジスタ退避命令実行後のスタック状態を示す図で
ある。
１１・・・ＲＯＭ 、 １２・・・ＲＡＭ 、 １３・
・・デコーダ、１４・・・コマンドレジスタ、１５・・
・汎用レジスタ群、１６・・・ＡＬ［Ｉ。
ＢＣＵ 、 １７・・・プログラムカウンタ、１ト・・
アドレスバス、１９・・・データバスFIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing the correspondence between command registers and general-purpose registers according to the present invention, and FIG. 3 is a diagram showing an example of the command register and the stack state after execution of an arbitrary register save instruction. 11...ROM, 12...RAM, 13.
...Decoder, 14...Command register, 15...
- General-purpose register group, 16...AL[I. BCU, 17...Program counter, 1t...
Address bus, 19...data bus
Claims (1)
用レジスタの各々の退避・非退避、復帰・非復帰を示す
コマンドレジスタと、前記汎用レジスタを退避させるス
タックエリアと、前記コマンドレジスタで指定する汎用
レジスタを退避、復帰させる命令とを有し、前記コマン
ドレジスタを前もって設定することにより、指定の汎用
レジスタのみを前記スタックエリアに退避させ、該スタ
ックエリアから復帰させることを特徴とする任意のレジ
スタ退避、復帰方式。A plurality of general-purpose registers in the microcomputer, a command register indicating save/non-save, restoration/non-return of each general-purpose register, a stack area for saving the general-purpose register, and a general-purpose register specified by the command register. Saving and restoring any register, characterized in that it has a command register for saving and restoring, and by setting the command register in advance, only specified general-purpose registers are saved to the stack area and restored from the stack area. method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25296988A JPH02100142A (en) | 1988-10-07 | 1988-10-07 | Saving and restoring system for arbitrary register |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25296988A JPH02100142A (en) | 1988-10-07 | 1988-10-07 | Saving and restoring system for arbitrary register |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02100142A true JPH02100142A (en) | 1990-04-12 |
Family
ID=17244675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25296988A Pending JPH02100142A (en) | 1988-10-07 | 1988-10-07 | Saving and restoring system for arbitrary register |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02100142A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011150636A (en) * | 2010-01-25 | 2011-08-04 | Renesas Electronics Corp | Microprocessor and control method thereof |
-
1988
- 1988-10-07 JP JP25296988A patent/JPH02100142A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011150636A (en) * | 2010-01-25 | 2011-08-04 | Renesas Electronics Corp | Microprocessor and control method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4970641A (en) | Exception handling in a pipelined microprocessor | |
| JPH0248931B2 (en) | ||
| JPH0810437B2 (en) | Guest execution control method for virtual machine system | |
| JPH0436416B2 (en) | ||
| JPH02100142A (en) | Saving and restoring system for arbitrary register | |
| JPH056281A (en) | Information processor | |
| JPH0443301B2 (en) | ||
| GB2030331A (en) | Real-time Data Processing System for Processing Time Period Commands | |
| JP2883488B2 (en) | Instruction processing unit | |
| JPH02103635A (en) | Digital system | |
| JPS59144955A (en) | Information processor | |
| JPH04181331A (en) | Instruction retry system | |
| JPS62151942A (en) | Task changing-over system | |
| JPH0235332B2 (en) | SAINYUKANOPUROGURAMUSEIGYOSHORIHOSHIKI | |
| JPH01142942A (en) | Register saving system | |
| JPS62166463A (en) | Data transfer system | |
| JPH01175034A (en) | Register group loading accelerating system | |
| JPH05298142A (en) | Microprocessor | |
| JPS62217326A (en) | Computer capable of storing and switching plural os | |
| JPS63208945A (en) | Information processor | |
| JPS626329A (en) | Data transfer circuit | |
| JPH04245333A (en) | Information processor | |
| JPS6260034A (en) | Stored program system controller | |
| JPH0152775B2 (en) | ||
| JPH0417530B2 (en) |