JPH0199273A - Optoelectronic integrated element - Google Patents
Optoelectronic integrated elementInfo
- Publication number
- JPH0199273A JPH0199273A JP25683487A JP25683487A JPH0199273A JP H0199273 A JPH0199273 A JP H0199273A JP 25683487 A JP25683487 A JP 25683487A JP 25683487 A JP25683487 A JP 25683487A JP H0199273 A JPH0199273 A JP H0199273A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- electrode
- layer
- laser
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005693 optoelectronics Effects 0.000 title claims description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000005855 radiation Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は光電子集積素子に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to an optoelectronic integrated device.
第６図は例えばレーザとＦＥＴ １個を集積した縦型光
電子集積素子（ＬＤ−ＦＥＴ）の断面図である。図にお
いて（１）はｎ−ＩｎＰ基板、（２）はＩｎＧａＡｓＰ
活性層、（３）はＳｔｏｗ、（４）はＰ拡散領域、６旧
よＦＥＴ能動層、（５）はゲート電極、旬はドレイン電
極、同はソース電極、βυはＦＥＴ層とレーザ層の分離
層、（６）はレーザのＰ１！極、（７）はｎ電極である
。FIG. 6 is a cross-sectional view of a vertical optoelectronic integrated device (LD-FET) in which a laser and one FET are integrated, for example. In the figure, (1) is an n-InP substrate, and (2) is an InGaAsP substrate.
Active layer, (3) is Stow, (4) is P diffusion region, (6) is FET active layer, (5) is gate electrode, is drain electrode, is source electrode, βυ is separation between FET layer and laser layer layer, (6) is P1 of the laser! The pole (7) is an n-electrode.
次に作用について説明する。基板上に、まずレーザ層が
形成され、最上部にＦＥＴ能動層（５１１および各電極
が形成され、両者は分離層δυで電気的に分離されてい
る。レーザを駆動する電流は、Ｐ電極（６）の直下のＰ
拡散領域（４）を通じて活性層（２）に注入される。Next, the effect will be explained. A laser layer is first formed on the substrate, and an FET active layer (511) and each electrode are formed on the top, and both are electrically separated by a separation layer δυ.The current that drives the laser is applied to the P electrode ( 6) P directly below
It is implanted into the active layer (2) through the diffusion region (4).
従来の縦型ＬＤ−ＦＥＴは以上のような構成のため、レ
ーザとＦＥＴ １個づつのような小規模な集積にもかか
わらず、結晶成長を多層に行なう必要があった。また、
素子の面積が大きくなる欠点があった。Because of the above-described configuration of the conventional vertical LD-FET, it was necessary to perform crystal growth in multiple layers despite the small-scale integration of one laser and one FET. Also,
There was a drawback that the area of the element became large.
この発明は上記のような問題点を解消するためになされ
たもので、従来の装置、技術で簡単に、かつ、コンパク
トなＬＤ−ＦＥＴが安価にできることを目的とする。This invention was made to solve the above-mentioned problems, and aims to make a compact LD-FET simple and inexpensive using conventional equipment and techniques.
この発明に係る光・電子集積素子は、レーザの直下の基
板に対し、周囲を拡散することによって、（レーザに対
し）直列のＪ−ＦＥＴを形成したものである。The opto-electronic integrated device according to the present invention has a J-FET in series (with respect to the laser) formed by diffusing the periphery of the substrate directly below the laser.
この発明における光・電子集積素子は、レーザの直下ｉ
２：Ｊ−ＰＥＴを作り付けたことにより、ＬＤ−ＦＥＴ
カ従来の装置、技術のみで安価にかつ、コンパクトに
製造できる。The opto-electronic integrated device in this invention is directly below the laser.
2: By building J-PET, LD-FET
It can be manufactured inexpensively and compactly using only conventional equipment and technology.
以下、この発明の実施例を図番こついて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図〜第４図は、この発明の光電子集積素子の製造方
法の例、および構造を示すものである。第５図はその回
路図を示すものである。FIGS. 1 to 4 show an example of a method of manufacturing an optoelectronic integrated device according to the present invention and its structure. FIG. 5 shows the circuit diagram.
＠１図において、結晶成長を行ない、レーザ層を形成し
た基板（１）の活性層（２）の両側をエツチングするこ
とにより、メサを形成する。次に、全体にＳ ｉ ０２
（３３を形成し、メサの両側の５ｉ０２の一部を取り
除く。（第２図）ＳｉＯｚをマスクとし、基板のエツチ
ングを行ない、Ｐ拡散（４）を行なう。（第３図）この
とき拡散は活性層の直下がＦＥＴのチャンネルとなるよ
うに制御して行なう。In Figure 1, a mesa is formed by etching both sides of an active layer (2) of a substrate (1) on which crystal growth is performed and a laser layer is formed. Next, the entire S i 02
(33 is formed and a part of 5i02 on both sides of the mesa is removed. (Figure 2) Using SiOz as a mask, the substrate is etched and P diffusion (4) is performed. (Figure 3) At this time, the diffusion is This is controlled so that the area directly below the active layer becomes the channel of the FET.
第４図において、ゲート電極（５）、Ｐ電極（６）、ｎ
電極（力を形成する。In FIG. 4, the gate electrode (5), the P electrode (6), the n
Electrodes (forming forces)
次に、動作について説明する。Ｐ電極（６）より印加さ
れた電流は活性層（２）に注入されて発光するが、ゲー
ト（３）に電圧をかけることによってレーザは発光しな
くなる。すなわち、ゲート電圧のＯＮ 、 ＯＦＦによ
り、レーザは点滅する。Next, the operation will be explained. A current applied from the P electrode (6) is injected into the active layer (2) and emits light, but by applying a voltage to the gate (3), the laser no longer emits light. That is, the laser blinks depending on whether the gate voltage is turned on or off.
なお、上記実施例は材料にＩｎＰ系を使用したがＧａＡ
ｓ系等、他の材料でもよい。また、ｐ Ｍ板を用いても
よい。また、レーザは埋込型としているが、他のタイプ
のレーザでもよいことは言うまでもない。Note that although InP was used as the material in the above embodiment, GaA
Other materials such as s-based materials may also be used. Alternatively, a PM plate may be used. Further, although the laser is of an embedded type, it goes without saying that other types of lasers may be used.
以上のように、この発明はレーザの活性層直下にＪ−Ｆ
ＥＴを形成したので、ＬＤ−ＦＥＴが従来の装置および
技術で簡単、かつ安価にできるとともｆこ、コンパクト
になる。As described above, the present invention provides J-F directly under the active layer of the laser.
Because the ET is formed, the LD-FET is simple, inexpensive, and compact using conventional equipment and technology.
第１図〜第４図はこの発明の一実施例による光・電子集
積素子の製造方法および構造を示す断面図、第５図はそ
の回路図、第６図は従来の縦型光電子集積素子を示す断
面図である。図Ｃζおいて、（υはｎ−ＩｎＰ基板、（
２）はＩｎＧａＡｓＰ活性層、（３）は５ｉ０２、（４
）はＰ拡散領域、（５）はゲート電極、（６）はＰ電極
、（７）はｎ電極、６月よＦＥＴ能ａ層、（２）はドレ
イン電極、ｑυはソース電極、ｉ８υは分離層である。
尚、各図中、同一符号は同一または相当部分を示す。1 to 4 are cross-sectional views showing a manufacturing method and structure of an optoelectronic integrated device according to an embodiment of the present invention, FIG. 5 is a circuit diagram thereof, and FIG. 6 is a diagram showing a conventional vertical optoelectronic integrated device. FIG. In figure Cζ, (υ is n-InP substrate, (
2) is InGaAsP active layer, (3) is 5i02, (4
) is the P diffusion region, (5) is the gate electrode, (6) is the P electrode, (7) is the n electrode, June FET function a layer, (2) is the drain electrode, qυ is the source electrode, i8υ is the separation It is a layer. In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
Ｔを形成したことを特徴とする光電子集積素子。A junction type FE is formed by diffusion directly under the active region of the light emitting device.
An optoelectronic integrated device characterized by forming a T.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25683487A JPH0199273A (en) | 1987-10-12 | 1987-10-12 | Optoelectronic integrated element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25683487A JPH0199273A (en) | 1987-10-12 | 1987-10-12 | Optoelectronic integrated element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0199273A true JPH0199273A (en) | 1989-04-18 |
Family
ID=17298074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25683487A Pending JPH0199273A (en) | 1987-10-12 | 1987-10-12 | Optoelectronic integrated element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0199273A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103765060A (en) * | 2011-09-10 | 2014-04-30 | 伊格尔工业股份有限公司 | Sliding component |
-
1987
- 1987-10-12 JP JP25683487A patent/JPH0199273A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103765060A (en) * | 2011-09-10 | 2014-04-30 | 伊格尔工业股份有限公司 | Sliding component |
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