JPH0178428U - - Google Patents
Info
- Publication number
- JPH0178428U JPH0178428U JP1987174692U JP17469287U JPH0178428U JP H0178428 U JPH0178428 U JP H0178428U JP 1987174692 U JP1987174692 U JP 1987174692U JP 17469287 U JP17469287 U JP 17469287U JP H0178428 U JPH0178428 U JP H0178428U
- Authority
- JP
- Japan
- Prior art keywords
- inverter
- input
- capacitor
- output
- switch means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Analogue/Digital Conversion (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は従来例を示す回路図である。
１１……第１のコンデンサ、１２……第１のイ
ンバータ、１３……第１のアナログスイツチ、１
４……第２のコンデンサ、１５……第２のインバ
ータ、１６……第２のアナログスイツチ、１７…
…第３のアナログスイツチ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 11...first capacitor, 12...first inverter, 13...first analog switch, 1
4...Second capacitor, 15...Second inverter, 16...Second analog switch, 17...
...Third analog switch.
Claims (1)
る第１のコンデンサと、該第１のコンデンサの他
端が入力に接続される第１のインバータと、該第
１のインバータの入出力間に接続された第１のス
イツチ手段と、前記第１のインバータの出力が接
続された第２のコンデンサと、該第２のコンデン
サの他端が入力に接続される第２のインバータと
、該第２のインバータの入出力間に接続された第
２のスイツチ手段と、前記第１のインバータの入
力と前記第２のインバータの出力間に接続された
第３のスイツチ手段とを備え、前記入力電圧と基
準電圧の差を増幅する期間に第３のスイツチ手段
をオンすることを特徴とするコンパレータ回路。 a first capacitor to which an input voltage and a reference voltage are switched and applied; a first inverter to which the other end of the first capacitor is connected to the input; and a first inverter connected between the input and output of the first inverter. a second capacitor to which the output of the first inverter is connected; a second inverter to which the other end of the second capacitor is connected to the input; a second switch means connected between the input and output of the inverter; and a third switch means connected between the input of the first inverter and the output of the second inverter, the input voltage and the reference voltage A comparator circuit characterized in that the third switch means is turned on during a period in which the difference between the two is amplified.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987174692U JPH0178428U (en) | 1987-11-16 | 1987-11-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987174692U JPH0178428U (en) | 1987-11-16 | 1987-11-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0178428U true JPH0178428U (en) | 1989-05-26 |
Family
ID=31466533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987174692U Pending JPH0178428U (en) | 1987-11-16 | 1987-11-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0178428U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05346441A (en) * | 1991-01-31 | 1993-12-27 | Toshiba Corp | Comparator |
-
1987
- 1987-11-16 JP JP1987174692U patent/JPH0178428U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05346441A (en) * | 1991-01-31 | 1993-12-27 | Toshiba Corp | Comparator |