JPH0164227U - - Google Patents
Info
- Publication number
- JPH0164227U JPH0164227U JP1987157918U JP15791887U JPH0164227U JP H0164227 U JPH0164227 U JP H0164227U JP 1987157918 U JP1987157918 U JP 1987157918U JP 15791887 U JP15791887 U JP 15791887U JP H0164227 U JPH0164227 U JP H0164227U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- reset
- voltage
- transistor
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Electronic Switches (AREA)
Description
第１図から第３図までが本考案に関し、第１図
は本考案によるリセツト回路をリセツト対象回路
とともに示すその原理回路図、第２図はその主な
信号の動作波形図、第３図は本考案の一実施例の
回路図である。第４図以降は従来技術に関し、第
４図はリセツト回路の従来例の回路図、第５図は
その主な信号の動作波形図である。図において、
１：リセツト回路、２：リセツト対象回路、１
０：電流ミラー回路、１１：電流ミラー回路の基
準トランジスタ、１２：電流ミラー回路の従動ト
ランジスタ、２０：リセツトトランジスタ、３１
：第１の抵抗、３２：第２の抵抗、４０：電流ミ
ラー回路、４１：電流ミラー回路の基準トランジ
スタ、４２：電流ミラー回路の従動トランジスタ
、５０：リセツトトランジスタ、６１：第１の抵
抗、６２：第２の抵抗、Ｆ：浮動状態、ｉｂ：リ
セツトトランジスタのベース電流、ｉｄ：電流ミ
ラー回路の従動電流、ｉｒ：電流ミラー回路の基
準電流、Ｒ１：第１の抵抗の抵抗値、Ｒ２：第２
の抵抗の抵抗値、ＲＳ：リセツト信号、ｔ０〜ｔ
７：時刻、Ｖ１：第１の電圧、Ｖ２：第２の電圧
、ｖ：リセツトトランジスタのベース・エミツタ
間電圧、ｖｒ：電流ミラー回路の基準トランジス
タのベース・エミツタ間電圧、Ｖｔ：リセツト回
路の動作しきい値、である。
Figures 1 to 3 relate to the present invention. Figure 1 is a principle circuit diagram showing the reset circuit according to the present invention together with the reset target circuit, Figure 2 is an operating waveform diagram of its main signals, and Figure 3 is 1 is a circuit diagram of an embodiment of the present invention; FIG. 4 and subsequent figures relate to the prior art. FIG. 4 is a circuit diagram of a conventional example of a reset circuit, and FIG. 5 is an operation waveform diagram of its main signals. In the figure, 1: reset circuit, 2: reset target circuit, 1
0: Current mirror circuit, 11: Reference transistor of current mirror circuit, 12: Driven transistor of current mirror circuit, 20: Reset transistor, 31
: first resistor, 32: second resistor, 40: current mirror circuit, 41: reference transistor of current mirror circuit, 42: driven transistor of current mirror circuit, 50: reset transistor, 61: first resistor, 62 : second resistor, F: floating state, ib: base current of reset transistor, id: driven current of current mirror circuit, ir: reference current of current mirror circuit, R1: resistance value of first resistor, R2: first resistor. 2
resistance value of the resistor, RS: reset signal, t0 to t
7: time, V1: first voltage, V2: second voltage, v: voltage between base and emitter of reset transistor, vr: voltage between base and emitter of reference transistor of current mirror circuit, Vt: operation of reset circuit is the threshold.
Claims (1)
ときに第２の電圧下で動作する回路をリセツトす
るリセツト回路であつて、第１の電圧から第１の
抵抗を介して基準電流が供給される電流ミラー回
路と、第２の電圧から第２の抵抗を介してベース
電流を供給されベース・エミツタ間が電流ミラー
回路の従動トランジスタと並列接続されたリセツ
トトランジスタとを備え、リセツトトランジスタ
のコレクタ電位をリセツト信号として出力するよ
うにするとともに、電流ミラー回路の基準トラン
ジスタとリセツトトランジスタとのベース・エミ
ツタ間電圧の比に対する第１の抵抗と第２の抵抗
との抵抗値の比の関係を定値にするようにしたこ
とを特徴とするリセツト回路。 A reset circuit that resets a circuit operating under a second voltage when the value of the first voltage falls below a predetermined threshold value, the reset circuit resetting the circuit operating under the second voltage, the reset circuit resetting the circuit operating under the second voltage when the value of the first voltage falls below a predetermined threshold value. The reset transistor includes a current mirror circuit to which a current is supplied, and a reset transistor which is supplied with a base current from a second voltage via a second resistor and whose base and emitter are connected in parallel with the driven transistor of the current mirror circuit. The collector potential of the transistor is output as a reset signal, and the ratio of the resistance values of the first resistor and the second resistor to the base-emitter voltage ratio of the reference transistor and reset transistor of the current mirror circuit is A reset circuit characterized in that the relationship is set to a fixed value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987157918U JPH0164227U (en) | 1987-10-15 | 1987-10-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987157918U JPH0164227U (en) | 1987-10-15 | 1987-10-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0164227U true JPH0164227U (en) | 1989-04-25 |
Family
ID=31437777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987157918U Pending JPH0164227U (en) | 1987-10-15 | 1987-10-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0164227U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04101962A (en) * | 1990-08-13 | 1992-04-03 | Kawasaki Steel Corp | Cut plate sorting device in metal strip processing line |
-
1987
- 1987-10-15 JP JP1987157918U patent/JPH0164227U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04101962A (en) * | 1990-08-13 | 1992-04-03 | Kawasaki Steel Corp | Cut plate sorting device in metal strip processing line |
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