JPH0157510B2 - - Google Patents

Info

Publication number
JPH0157510B2
JPH0157510B2 JP601680A JP601680A JPH0157510B2 JP H0157510 B2 JPH0157510 B2 JP H0157510B2 JP 601680 A JP601680 A JP 601680A JP 601680 A JP601680 A JP 601680A JP H0157510 B2 JPH0157510 B2 JP H0157510B2
Authority
JP
Japan
Prior art keywords
light emitting
layer
carrier confinement
inp
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP601680A
Other languages
Japanese (ja)
Other versions
JPS56103485A (en
Inventor
Shigenobu Yamagoshi
Kazuo Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP601680A priority Critical patent/JPS56103485A/en
Publication of JPS56103485A publication Critical patent/JPS56103485A/en
Publication of JPH0157510B2 publication Critical patent/JPH0157510B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004Devices characterised by their operation
    • H01L33/002Devices characterised by their operation having heterojunctions or graded gap
    • H01L33/0025Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Lasers (AREA)
  • Led Devices (AREA)

Description

【発明の詳細な説明】 本発明はインジユウム ガリウム 砒素 燐
In1-xGaxAs1-uPuを発光領域として良好なヘテロ
構造を有する半導体発光素子に関する。
[Detailed Description of the Invention] The present invention relates to indium gallium arsenic phosphorus.
The present invention relates to a semiconductor light emitting device having a good heterostructure using In 1-x Ga x As 1-u P u as a light emitting region.

1μm帯光通信用発光素子としては、インジウム
燐InP基板と格子整合を満たしたまま1〜1.7μm
の波長範囲でエピタキシヤル成長が可能なことか
らIn1-xGaxAs1-uPu(0x1、0u1)を
発光領域とするものが使用されるようになつた。
従来のこの種の発光ダイオードは、第1図に示す
ように、n+形InP基板1と、InGaAsPからなる発
光領域すなわち活性層2と、活性層2をはさみダ
ブルヘテロ構造を構成するキヤリア閉じ込め層
3,4とを有し、キヤリア閉じ込め層3,4はそ
れぞれn型InP層、p型InP層を用いていた。5,
6はそれぞれAu―Ge―Ni電極、およびAu―Zn
電極であり、7はSiO2からなる絶縁膜、8は金
メツキ層である。
As a light emitting element for 1μm band optical communication, it is possible to use a 1-1.7μm light emitting device while satisfying lattice matching with an indium phosphorus InP substrate.
Because epitaxial growth is possible in the wavelength range of , those with a light emitting region of In 1-x Ga x As 1-u P u (0x1, 0u1) have come to be used.
As shown in FIG. 1, a conventional light emitting diode of this type includes an n + type InP substrate 1, a light emitting region or active layer 2 made of InGaAsP, and a carrier confinement layer sandwiching the active layer 2 and forming a double heterostructure. 3 and 4, and the carrier confinement layers 3 and 4 were an n-type InP layer and a p-type InP layer, respectively. 5,
6 are Au-Ge-Ni electrodes and Au-Zn, respectively.
The electrodes include an insulating film 7 made of SiO 2 and a gold plating layer 8.

第1図に示した従来の発光ダイオードでは、活
性層2を形成するIn1-xGaxAs1-uPuの発光波長が
長くなるにつれて即ちuの値が小さくなる程その
上にキヤリア閉じ込め層3,4としてInP層を成
長させることが困難となる。この場合In1-xGax
As1-uPuの上に組成が異なるIn1-vGavAs1-wPw
を成長させざるを得ない。しかしヘテロ構造によ
るキヤリア閉じ込め効率をよく行なおうとすると
wの値を大きくする必要があり結局InPの組成に
近いIn1-vGavAs1-wPwをキヤリア閉じ込め層3,
4として選ばねばならない。In1-vGavAs1-wPw
成長させる場合In+Ga+As+Pの4元溶液を用
いるが、w>uのとき、溶液中の砒素Asの濃度
が低くなるから、In1-xGaxAs1-uPu活性層2から
Asが供給される方向に反応がすすみ、即ち活性
層2の溶解が起きる。この溶解の現象はとくに活
性層2の薄い(〜0.2μm)半導体レーザでは到命
的である。
In the conventional light emitting diode shown in Fig. 1, as the emission wavelength of In 1-x Ga x As 1-u P u forming the active layer 2 becomes longer, that is, the value of u becomes smaller, carriers are confined on it. It becomes difficult to grow InP layers as layers 3 and 4. In this case In 1-x Ga x
There is no choice but to grow an In 1 -v Ga v As 1-w P w layer with a different composition on top of the As 1-u P u layer. However, in order to improve the carrier confinement efficiency by the heterostructure, it is necessary to increase the value of w, and in the end, the carrier confinement layer 3 is made of In 1-v Ga v As 1-w P w , which has a composition similar to InP.
Must be selected as 4. When growing In 1-v Ga v As 1-w P w , a quaternary solution of In+Ga+As+P is used, but when w>u, the concentration of arsenic As in the solution becomes low, so In 1-x Ga x As 1-u P uFrom active layer 2
The reaction progresses in the direction in which As is supplied, that is, the active layer 2 is dissolved. This phenomenon of dissolution is particularly fatal for semiconductor lasers in which the active layer 2 is thin (~0.2 μm).

このような問題の対策として、第2図に示すよ
うにIn0.59 Ga0.41 As0.92 P0.08活性層2とp型
InPキヤリア閉じ込め層4の間に非常に薄い
(0.15μm)p型In0.76 Ga0.24 As0.52 P0.48の溶
解阻止層9を介在させてAsの溶解を避けるもの
がある。しかし、この手段は活性層2とキヤリア
閉じ込め層4との間にキヤリア閉じ込めの不完全
な溶解阻止層を入れるため、その厚さを非常に薄
くしなければならずその再現性、制御性に問題が
ありキヤリア閉じ込め効果も不十分となるという
問題があつた。
As a countermeasure to this problem, as shown in Figure 2, In0.59 Ga0.41 As0.92 P0.08 active layer 2 and p-type
There is a method in which a very thin (0.15 μm) dissolution prevention layer 9 of p-type In0.76 Ga0.24 As0.52 P0.48 is interposed between the InP carrier confinement layer 4 to avoid dissolution of As. However, since this method inserts a dissolution prevention layer with incomplete carrier confinement between the active layer 2 and the carrier confinement layer 4, the thickness must be made very thin, which causes problems in reproducibility and controllability. There was a problem that the carrier confinement effect was insufficient.

本発明は上記従来の欠点を除去し、活性層が溶
解することなくかつ十分なキヤリア閉じ込め作用
も行なう効率良い半導体発光素子を提供すること
を目的とする。
An object of the present invention is to eliminate the above-mentioned conventional drawbacks and to provide an efficient semiconductor light emitting device in which the active layer does not dissolve and also provides sufficient carrier confinement.

本発明による半導体発光素子は、Inp基板を有
しIn1-xCaxAs1-uPu(0≦x≦1、0≦u≦1)を
発光領域とし発光波長を1.5〜1.7μmとしたヘテロ
構造を持つ発光素子において、発光領域の片側も
しくは両側に配設されたキヤリア閉じ込め層とし
て、InPと格子整合をとり、InPとほぼ同じまた
はそれ以上のエネルギギヤツプのAlyGazIn1-y-z
As(0≦y≦1、0≦z≦1、y+z≦1)を用
いることを特徴とする。
The semiconductor light emitting device according to the present invention has an Inp substrate, a light emitting region of In 1-x Ca x As 1-u P u (0≦x≦1, 0≦u≦1), and a light emission wavelength of 1.5 to 1.7 μm. In a light-emitting device with a heterostructure, Al y Ga z In 1-yz is used as a carrier confinement layer disposed on one or both sides of the light-emitting region, which is lattice-matched to InP and has an energy gap almost the same as or larger than that of InP.
It is characterized by using As (0≦y≦1, 0≦z≦1, y+z≦1).

以下、図面を参照して本発明の一実施例を発光
ダイオードを例として説明する。
Hereinafter, one embodiment of the present invention will be described using a light emitting diode as an example with reference to the drawings.

第3図において、(111)面または(100)面を
もつ錫Snドープのn+形InPウエハを基板11と
し、基板の影響を無くすため〜5μmの厚さのSn
をドープしたn+形InPをバツフア層12として次
に発光領域すなわち活性層13としてIn1-xGax
As1-uPu(0≦x≦1、0≦u≦1)を成長させ
る。ここで、発光波長〜1.5μmの時x=0.38、u
=0.19発光波長〜1.7μmの時x=0.47、u=0で
あり、不純物としては亜鉛Zn又はカドミウムCd
又はマグネシウムMg等の族原子をドープして
p形とするか又はSn等の族原子あるいはテル
ルTe等の族原子をドープするか又は非ドープ
でn形とした。続いてZn又はCdドープのp形Aly
GazIn1-y-zAsからなるキヤリア閉じ込め層14を
成長させた。ここにy=0.40、Z=0.07とし、エ
ネルギギヤツプはInP基板とほぼ同じに選択し
た。
In Fig. 3, the substrate 11 is a tin-Sn - doped n
The buffer layer 12 is made of n + type InP doped with In 1-x Ga
Grow As 1-u P u (0≦x≦1, 0≦u≦1). Here, when the emission wavelength is ~1.5 μm, x = 0.38, u
= 0.19 When the emission wavelength is ~ 1.7 μm, x = 0.47, u = 0, and the impurity is zinc Zn or cadmium Cd.
Alternatively, it may be doped with a group atom such as magnesium Mg to make it p-type, or it may be doped with a group atom such as Sn or tellurium Te or the like, or it may be undoped to make it n-type. Next, Zn or Cd doped p-type Al y
A carrier confinement layer 14 made of Ga z In 1-yz As was grown. Here, y = 0.40, Z = 0.07, and the energy gap was selected to be almost the same as that of the InP substrate.

AlyGazIn1-y-xAsは、(0y1、0z
1、y+z1)の範囲とし、InPと格子整合を
とりながらエネルギギヤツプを0.75〜1.5eV間で
変えることができる。キヤリア閉じ込め層14の
上にはAu―Znからなる10μm〜100μmφの径を持
つp電極15を形成し、電極部以外を〜3000Åの
SiO2膜16で絶縁し、その後Cr、Auを蒸着し、
放熱のために〜20μm厚のAuメツキ層17を形成
した。その後裏面のInP基板11を研磨し、Au―
Ge―Niからなるn電極18を設け、これには発
光部が見えるように窓19があけられる。
Al y Ga z In 1-yx As is (0y1, 0z
1, y+z1), and the energy gap can be varied between 0.75 and 1.5 eV while maintaining lattice matching with InP. A p-electrode 15 made of Au-Zn and having a diameter of 10 μm to 100 μmφ is formed on the carrier confinement layer 14, and the area other than the electrode portion is formed with a thickness of ~3000 Å.
Insulate with SiO 2 film 16, then evaporate Cr and Au,
An Au plating layer 17 with a thickness of ~20 μm was formed for heat dissipation. After that, the InP substrate 11 on the back side was polished and the Au-
An n-electrode 18 made of Ge--Ni is provided, and a window 19 is opened in the n-electrode 18 so that the light emitting part can be seen.

第3図に示した実施例では、キヤリア閉じ込め
層14としてAlyGazIn1-y-zAsを用いたので、4
元溶液(Al+Ga+In+As)中のV族溶質元素は
Asだけであり、4元溶液が飽和または過飽和状
態にあれば、In1-xGaxAs1-uPu活性層13からの
Asの溶解は起らなくなり良質のAlyGazIn1-y-zAs
キヤリア閉じ込め層14を成長させることができ
る。さらに、この4元キヤリア閉じ込め層14は
InPの格子定数に完全に格子整合することがで
き、エネルギギヤツプも大きく選択することがで
きるのでキヤリア閉じ込め効果も十分で、効率の
良いヘテロ構造をつくることができる。
In the embodiment shown in FIG. 3, Al y Ga z In 1-yz As was used as the carrier confinement layer 14, so 4
Group V solute elements in the original solution (Al+Ga+In+As) are
If the quaternary solution is saturated or supersaturated, In 1-x Ga x As 1-u P u from the active layer 13.
No dissolution of As occurs, resulting in high quality Al y Ga z In 1-yz As
A carrier confinement layer 14 may be grown. Furthermore, this quaternary carrier confinement layer 14 is
It can perfectly lattice match the lattice constant of InP, and the energy gap can be selected to be large, so the carrier confinement effect is sufficient and an efficient heterostructure can be created.

第4図は本発明の他の実施例を示すもので、第
3図に示した実施例と同一の部分は同一参照番号
を付して説明を省略する。
FIG. 4 shows another embodiment of the present invention, and the same parts as those in the embodiment shown in FIG. 3 are given the same reference numerals and their explanation will be omitted.

InGaAsP活性層13の両側をp形AlGaInAsキ
ヤリア閉じ込め層20、n形AlGaInAsキヤリア
閉じ込め層21ではさんだものである。
An InGaAsP active layer 13 is sandwiched between a p-type AlGaInAs carrier confinement layer 20 and an n-type AlGaInAs carrier confinement layer 21 on both sides.

以上の説明は発光ダイオードについてなされた
が半導体レーザに適用できることは勿論である。
Although the above description has been made regarding light emitting diodes, it is of course applicable to semiconductor lasers.

上述したように、本発明によれば、活性層の溶
解がなくキヤリア閉じ込め効果がこれ迄以上に十
分でかつ格子整合のとれた効率の良い半導体発光
素子を提供することができる。
As described above, according to the present invention, it is possible to provide a highly efficient semiconductor light-emitting device in which the active layer does not dissolve, the carrier confinement effect is more sufficient than ever, and lattice matching is achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は従来の半導体発光素子の断面
図、第3図は本発明にかかる半導体発光素子の一
実施例の断面図、第4図は本発明の他の実施例の
断面図である。 図において、11…InP基板、13…InGaAsP
活性層、14…AlGaInAsキヤリア閉じ込め層、
15…p電極、18…n電極。
1 and 2 are sectional views of a conventional semiconductor light emitting device, FIG. 3 is a sectional view of one embodiment of the semiconductor light emitting device according to the present invention, and FIG. 4 is a sectional view of another embodiment of the present invention. It is. In the figure, 11...InP substrate, 13...InGaAsP
active layer, 14...AlGaInAs carrier confinement layer,
15...p electrode, 18...n electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 InP基板を有しIn1-xCaxAs1-uPu(0≦x≦
1、0≦u≦1)を発光領域とし発光波長を1.5
〜1.7μmとしたヘテロ構造を持つ発光素子におい
て、発光領域の片側もしくは両側に配設されたキ
ヤリア閉じ込め層として、InPと格子整合をと
り、InPとほぼ同じまたはそれ以上のエネルギギ
ヤツプのAlyCazIn1-y-zAs(0≦y≦1、0≦z≦
1、y+z≦1)を用いることを特徴とする半導
体発光素子。
1 InP substrate has In 1-x Ca x As 1-u P u (0≦x≦
1, 0≦u≦1) is the emission region and the emission wavelength is 1.5
In a light emitting device with a heterostructure of ~1.7 μm, Al y Ca z is used as a carrier confinement layer disposed on one or both sides of the light emitting region, which is lattice matched with InP and has an energy gap almost the same as or larger than InP. In 1-yz As (0≦y≦1, 0≦z≦
1, y+z≦1).
JP601680A 1980-01-22 1980-01-22 Semiconductor light emission element Granted JPS56103485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP601680A JPS56103485A (en) 1980-01-22 1980-01-22 Semiconductor light emission element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP601680A JPS56103485A (en) 1980-01-22 1980-01-22 Semiconductor light emission element

Publications (2)

Publication Number Publication Date
JPS56103485A JPS56103485A (en) 1981-08-18
JPH0157510B2 true JPH0157510B2 (en) 1989-12-06

Family

ID=11626896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP601680A Granted JPS56103485A (en) 1980-01-22 1980-01-22 Semiconductor light emission element

Country Status (1)

Country Link
JP (1) JPS56103485A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63299186A (en) * 1987-05-29 1988-12-06 Hitachi Ltd Light emitting element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320881A (en) * 1976-08-11 1978-02-25 Nippon Telegr & Teleph Corp <Ntt> Photo semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320881A (en) * 1976-08-11 1978-02-25 Nippon Telegr & Teleph Corp <Ntt> Photo semiconductor device

Also Published As

Publication number Publication date
JPS56103485A (en) 1981-08-18

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